6-Bit Programmable 2- to 4-Phase Synchronous Buck Controller ADP3196 FUNCTIONAL BLOCK DIAGRAM FEATURES VCC RT 12 31 RAMPADJ 13 SHUNT REGULATOR SET + CMP – GND 18 + CMP – – 800mV EN 19 OD OSCILLATOR UVLO SHUTDOWN + 1 CURRENT BALANCING CIRCUIT – 1.8V CSREF + + CMP – RESET 30 PWM1 RESET 29 PWM2 RESET 28 PWM3 2-/3-/4-PHASE DRIVER LOGIC + CMP – + DAC – 250mV EN – CURRENT LIMIT PWRGD 2 DELAY CROWBAR 25 SW1 24 SW2 TTSENSE 10 APPLICATIONS Desktop PC power supplies for next generation AMD processors VRM modules VRMHOT 9 VRM_OFF 8 THERMAL THROTTLING CONTROL 23 SW3 22 SW4 17 CSCOMP ILIMIT 11 DELAY CURRENT MEASUREMENT AND LIMIT 7 + The ADP3196 is a highly efficient multiphase synchronous buck switching regulator controller optimized for converting a 12 V main supply into the core supply voltage required by high performance Advanced Micro Devices, Inc. (AMD) processors. It uses an internal 6-bit DAC to read a voltage identification (VID) code directly from the processor, which is used to set the output voltage between 0.3750 V and 1.55 V. This device uses a multimode PWM architecture to drive the logic-level outputs at a programmable switching frequency that can be optimized for VR size and efficiency. The phase relationship of the output signals can be programmed to provide 2-, 3-, or 4-phase operation, allowing for the construction of up to four complementary buck switching stages. The ADP3196 supports a programmable slope function to adjust the output voltage as a function of the load current so that it is always optimally positioned for a system transient. This can be disabled by connecting Pin LLSET to Pin CSREF. 1 Protected by U.S. Patent Number 6,683,441; others patents pending. 15 CSREF – 16 CSSUM GENERAL DESCRIPTION 1 27 PWM4 RESET 21 IMON IREF 20 COMP 4 FB – 5 + + PRECISION REFERENCE 14 LLSET – FBRTN 3 SOFT START CONTROL 6 SS VID DAC ADP3196 34 35 VID5 VID4 36 37 38 39 VID3 VID2 VID1 VID0 06371-001 Selectable 2-, 3-, or 4-phase operation at up to 1 MHz per phase ±10 mV worst-case differential sensing error over temperature Logic-level PWM outputs for interface to external high power drivers Enhanced PWM flex mode for excellent load transient performance Active current balancing between all output phases Built-in power-good/crowbar blanking supports on-the-fly VID code changes Digitally programmable 0.3750 V to 1.55 V output Programmable short-circuit protection with programmable latch-off delay Figure 1. Functional Block Diagram The ADP3196 also provides accurate and reliable short-circuit protection, adjustable current limiting, and a delayed powergood output that accommodates on-the-fly output voltage changes requested by the CPU. The ADP3196 has a built-in shunt regulator that allows the part to be connected to the 12 V system supply through a series resistor. The ADP3196 is specified over the extended commercial temperature range of 0°C to +85°C and is available in a 40-lead LFCSP. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. ADP3196 TABLE OF CONTENTS Features .............................................................................................. 1 Output Current Sensing ............................................................ 11 Applications....................................................................................... 1 Active Impedance Control Mode............................................. 11 General Description ......................................................................... 1 Current Control Mode and Thermal Balance ........................ 11 Functional Block Diagram .............................................................. 1 Voltage Control Mode ............................................................... 12 Table of Contents .............................................................................. 2 Current Reference ...................................................................... 12 Revision History ............................................................................... 2 Enhanced PWM Mode .............................................................. 12 Specifications..................................................................................... 3 Delay Timer................................................................................. 12 Test Circuits....................................................................................... 5 Soft Start ...................................................................................... 12 Absolute Maximum Ratings............................................................ 6 Current Limit, Short-Circuit, and Latch-Off Protection ...... 13 ESD Caution.................................................................................. 6 Dynamic VID ............................................................................. 14 Pin Configuration and Function Description .............................. 7 Power-Good Monitoring........................................................... 14 Typical Performance Characteristics ............................................. 9 Output Crowbar ......................................................................... 14 Theory of Operation ...................................................................... 10 Output Enable and UVLO ........................................................ 14 Start-Up Sequence...................................................................... 10 Thermal Monitoring .................................................................. 14 Phase Detection Sequence......................................................... 10 Layout and Component Placement ......................................... 17 Master Clock Frequency............................................................ 11 Outline Dimensions ....................................................................... 18 Output Voltage Differential Sensing ........................................ 11 Ordering Guide .......................................................................... 18 REVISION HISTORY 10/06—Revision 0: Initial Version Rev. 0 | Page 2 of 20 ADP3196 SPECIFICATIONS VCC = 5 V, FBRTN = GND, TA = 0°C to 85°C, unless otherwise noted. 1 Table 1. Parameter REFERENCE CURRENT Reference Bias Voltage Reference Bias Current Symbol Conditions Min Typ Max Unit VIREF IIREF RIREF = 100 kΩ 14.25 1.5 15 15.75 V μA ERROR AMPLIFIER Output Voltage Range 2 Accuracy VCOMP VFB 4.4 10 V mV mV LSB −7.5 −82 +1 −6 65 200 Relative to nominal DAC output, referenced to FBRTN, LLSET = CSREF (see Figure 2) CSREF – LLSET = 80 mV 0.05 −10 Load Line Positioning Accuracy Differential Nonlinearity Input Bias Current IFB FBRTN Current IFBRTN Output Current ICOMP FB forced to VOUT – 3% 500 Gain Bandwidth Product Slew Rate GBW(ERR) COMP = FB COMP = FB 20 25 VLLSET ILLSET Relative to CSREF VIL(VID) VIH(VID) IIN(VID) VID(X), VIDSEL VID(X), VIDSEL 1.4 VID code change to FB change 400 LLSET Input Voltage Range LLSET Input Bias Current VID INPUTS Input Low Voltage Input High Voltage Input Current VID Transition Delay Time2 OSCILLATOR Frequency Range2 Frequency Variation fOSC fPHASE Output Voltage VRT RAMPADJ Output Voltage RAMPADJ Input Current Range VRAMPADJ IRAMPADJ CURRENT SENSE AMPLIFIER Offset Voltage Input Bias Current Gain Bandwidth Product Slew Rate Input Common-Mode Range Output Voltage Range Output Current Current Limit Latch-Off Delay Time IMON Output CURRENT BALANCE AMPLIFIER Common-Mode Range Input Resistance Input Current VOS(CSA) IBIAS(CSSUM) GBW(CSA) IFB = 0.5 × IIREF −78 −1 −9 −80 −250 −10 +250 +10 RT = 243 kΩ to GND RAMPADJ – FB, DAC = 1.55 V CSSUM – CSREF (see Figure 3) 1.9 −50 1 4 220 2.1 +50 50 mV μA +1.0 mV +10 nA MHz 10 10 0 0.05 ICSCOMP 3.5 3.5 8 IMON 10 × (CSREF – CSCOMP) > 50mV −6 VSW(X)CM RSW(X) ISW(X) SW(X) = 0 V SW(X) = 0 V −600 10 8 Input Current Matching ΔISW(X) SW(X) = 0 V −4 CURRENT LIMIT COMPARATOR ILIMIT Bias Current IILIMIT IILIMIT = 2/3 × IIREF 9 10 11 VILIMIT RILIMIT = 121kΩ (VILIMIT = IILIMIT × RILIMIT) 1.21 1.33 VCL VCSREF – VCSCOMP, RILIMIT = 121 kΩ VCL/IILIMIT 1.09 3 80 100 82.6 125 17 12 V/μs V V μA ms 500 CDELAY = 10 nF Rev. 0 | Page 3 of 20 MHz kHz kHz kHz V −10 tOC(DELAY) ILIMIT Voltage Maximum Output Voltage Current Limit Threshold Voltage Current Limit Setting Ratio V V −1.0 CSSUM = CSCOMP CCSCOMP = 10 pF CSSUM and CSREF 200 400 800 2.0 V/μs mV nA μA ns −10 0.25 180 μA μA MHz 0.6 TA = 25°C, RT = 205 kΩ, 4 phase TA = 25°C, RT = 118 kΩ, 4 phase TA = 25°C, RT = 55 kΩ, 4 phase μA +6 % +200 26 20 mV kΩ +4 μA % μA V V mV mV/V ADP3196 Parameter DELAY TIMER Normal Mode Output Current Output Current in Current Limit Threshold Voltage SOFT START Output Current (Startup) Output Current (DAC Code Change) ENABLE INPUT Threshold Voltage Hysteresis Input Current Delay Time OD OUTPUT Symbol Conditions Min Typ Max Unit IDELAY IDELAY(CL) VDELAY(TH) IDELAY = IIREF IDELAY(CL) = 0.25 × IIREF 12 3.0 1.6 15 3.75 1.7 18 4.5 1.8 µA µA V ISS(STARTUP) During startup, ISS(STARTUP) = 0.25 × IIREF 3 3.75 4.5 μA ISS(DAC) DAC code change, ISS(DAC) = 1.25 × IIREF 15 18.75 22.5 μA 750 80 800 100 −1 850 125 mV mV VTH(EN) VHYS(EN) IIN(EN) tDELAY(EN) Output Low Voltage VOL(OD) Output High Voltage VOH(OD) OD Pull-Down Resistor THERMAL THROTTLING CONTROL TTSENSE Voltage Range TTSENSE Bias Current TTSENSE VRM_OFF Threshold Voltage TTSENSE VRMHOT Threshold Voltage TTSENSE Hysteresis VRM_OFF Output Low Voltage VRMHOT Output Low Voltage POWER-GOOD COMPARATOR Overvoltage Threshold 160 VOL(VRFAN) VOL(VRHOT) I VRFAN (SINK) = −4 mA I VRHOT (SINK) = −4 mA VPWRGD(OV) Relative to nominal DAC output; DAC = 0.5 V to 1.55 V Relative to nominal DAC output; DAC = 0.375 V to 0.4785 V Relative to nominal DAC output; DAC = 0.5 V to 1.55 V Relative to nominal DAC output; DAC = 0.375 V to 0.4785 V IPWRGD(SINK) = −4 mA VPWRGD(UV) Output Low Voltage Power-Good Delay Time During Soft Start2 VID Code Changing VOL(PWRGD) Relative to FBRTN Overvoltage to PWM going low VOL(PWM) IPWM(SINK) = −400 μA Output High Voltage VOH(PWM) IPWM(SOURCE) = 400 μA VCC DC Supply Current UVLO Turn On Current UVLO Threshold Voltage UVLO Threshold Voltage 60 kΩ 5 −111 1.06 1.105 1.15 μA V 765 810 855 mV 50 150 150 300 300 mV mV mV 250 250 −250 −250 150 300 310 −200 −190 300 mV mV mV mV mV 200 190 −300 −310 100 2 250 1.75 200 1.8 1.85 160 5 4.65 5 μs ns V μs ns 250 4.0 V ms 400 POWER SUPPLY mV V −123 100 VID Code Static PWM OUTPUTS Output Low Voltage 500 5 0 −135 CDELAY = 10 nF VCROWBAR tCROWBAR μA ms 2 4 Internally limited Undervoltage Threshold VID Code Static Crowbar Trip Point Crowbar Delay Time VID Code Changing EN > 950 mV, CDELAY = 10 nF 500 mV V VSYSTEM = 12 V, RSHUNT = 340Ω (see Figure 2) VCC IVCC 6.5 VUVLO VUVLO VCC rising VCC falling 5.55 25 11 V mA mA 9 4.1 1 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). 2 Guaranteed by design or bench characterization, not tested in production. Rev. 0 | Page 4 of 20 V ADP3196 TEST CIRCUITS 12V 680Ω 6-BIT CODE + 1µF 680Ω 100nF ADP3196 12V 1.25V 1kΩ 10nF 1 EN PWRGD FBRTN FB COMP SS DELAY VRM_OFF VRMHOT TTSENSE ADP3196 ILIMIT RT RAMPADJ LLSET CSREF CSSUM CSCOMP GND OD IREF 10nF NC VID0 VID1 VID2 VID3 VID4 VID5 NC NC VCC 40 680Ω PWM1 PWM2 PWM3 PWM4 NC SW1 SW2 SW3 SW4 IMON 680Ω VCC 31 FB 4 10kΩ FBRTN 3 LLSET 14 ΔV 100kΩ CSREF 15 1V 250kΩ – + VID DAC GND 20kΩ 100nF NC = NO CONNECT. 12V ADP3196 680Ω 680Ω VCC 31 CSCOMP 17 39kΩ 100nF CSSUM 16 1kΩ CSREF GND 18 VOS = CSCOMP – 1V 40 06371-003 15 1V ΔVFB = FBΔV = 80mV – FBΔV = 0mV Figure 4. Positioning Voltage Figure 2. Closed-Loop Output Voltage Accuracy Figure 3. Current Sense Amplifier VOS Rev. 0 | Page 5 of 20 06371-004 06371-002 18 ADP3196 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter VCC FBRTN PWM3 – PWM4, RAMPADJ SW1 – SW4 <200 ns All Other Inputs and Outputs Storage Temperature Operating Ambient Temperature Range Operating Junction Temperature Thermal Impedance (θJA) Lead Temperature Soldering (10 sec) Infrared (15 sec) Rating −0.3 V to +6 V −0.3 V to +0.3 V −0.3 V to VCC + 0.3 V −5 V to +25 V −10 V to +25 V −0.3 V to VCC + 0.3 V −65°C to +150°C 0°C to 85°C 125°C 100°C/W Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute maximum ratings apply individually only, not in combination. Unless otherwise specified all other voltages referenced to GND. ESD CAUTION 300°C 260°C Rev. 0 | Page 6 of 20 ADP3196 40 39 38 37 36 35 34 33 32 31 NC VID0 VID1 VID2 VID3 VID4 VID5 NC NC VCC PIN CONFIGURATION AND FUNCTION DESCRIPTION PIN 1 INDICATOR ADP3196 TOP VIEW (Not to Scale) 30 29 28 27 26 25 24 23 22 21 PWM1 PWM2 PWM3 PWM4 NC SW1 SW2 SW3 SW4 IMON NOTES 1. NC = NO CONNECT. 2. THE EXPOSED EPAD ON BOTTOM SIDE OF PACKAGE IS AN ELECTRICAL CONNECTION AND SHOULD BE SOLDERED TO GROUND. 06371-005 ILIMIT RT RAMPADJ LLSET CSREF CSSUM CSCOMP GND OD IREF 11 12 13 14 15 16 17 18 19 20 EN 1 PWRGD 2 FBRTN 3 FB 4 COMP 5 SS 6 DELAY 7 VRM_OFF 8 VRMHOT 9 TTSENSE 10 Figure 5. Pin Configuration Table 3. Pin Function Descriptions Pin No. 1 2 Mnemonic EN PWRGD 3 4 FBRTN FB 5 6 COMP SS 7 DELAY 8 VRM_OFF 9 VRMHOT 10 TTSENSE 11 ILIMIT 12 RT 13 RAMPADJ 14 LLSET 15 CSREF 16 CSSUM 17 CSCOMP 18 GND Description Power Supply Enable Input. Pulling this pin to GND disables the PWM outputs and pulls the PWRGD output low. Power-Good Output. Open-drain output that signals when the output voltage is outside of the proper operating range. Feedback Return. VID DAC and error amplifier reference for remote sensing of the output voltage. Feedback Input. Error amplifier input for remote sensing of the output voltage. An external resistor between this pin and the output voltage sets the no load offset point. Error Amplifier Output and Compensation Point. Soft Start Delay Setting Input. An external capacitor connected between this pin and GND sets the soft start ramp-up time and the VID on-the-fly slew rate. Delay Timer Setting Input. An external capacitor connected between this pin and GND sets the overcurrent latch-off delay time, EN delay time, and PWRGD delay time. VRM_OFF Signal. Open-drain output that asserts when the temperature at the monitoring point connected to TTSENSE exceeds the VRM_OFF threshold. Open-drain output that signals when the temperature at the monitoring point connected to TTSENSE exceeds the maximum operating temperature. For example, this can be connected to the PROCHOT# (a PC system signal) output from the CPU. VR Hot Thermal Throttling Sense Input. An NTC thermistor between this pin and GND is used to remotely sense the temperature at the desired thermal monitoring point. Current Limit Setpoint. An external resistor from this pin to GND sets the current limit threshold of the converter. Frequency Setting Resistor Input. An external resistor connected between this pin and GND sets the oscillator frequency of the device. PWM Ramp Current Input. An external resistor from the converter input voltage to this pin sets the internal PWM ramp. Output Load Line Programming Input. This pin can be directly connected to CSCOMP, or it can be connected to the center point of a resistor divider between CSCOMP and CSREF. Connecting LLSET to CSREF disables positioning. Current Sense Reference Voltage Input. The voltage on this pin is used as the reference for the current sense amplifier and the power-good and crowbar functions. This pin should be connected to the common point of the output inductors. Current Sense Summing Node. External resistors from each switch node to this pin sum the average inductor currents together to measure the total output current. Current Sense Compensation Point. A resistor and capacitor from this pin to CSSUM determines the gain of the current sense amplifier and the positioning loop response time. Ground. All internal biasing and the logic output signals of the device are referenced to this ground. Rev. 0 | Page 7 of 20 ADP3196 Pin No. 19 Mnemonic OD 20 IREF 21 22 to 25 IMON SW4 to SW1 26, 32, 33, 40 27 to 30 NC 31 VCC 34 to 39 VID5 to VID0 PWM4 to PMW1 Description Output Disable Logic Output. This pin is actively pulled low when the ADP3196 EN input is low or when VCC is below its UVLO threshold to signal to the driver IC that the driver high-side and low-side outputs should go low. Current Reference Input. An external resistor from this pin to ground sets the reference current for IFB, IDELAY, ISS, IILIMIT and ITTSENSE. Analog Output. Represents total load current. Current Balance Inputs. Inputs for measuring the current level in each phase. The SW pins of unused phases should be left open. No Connection. Logic Level PWM Outputs. Each output is connected to the input of an external MOSFET driver, such as the ADP3120A. Connecting the PWM3 and/or PWM4 outputs to the ADP3196 VCC pin causes that phase to turn off, allowing the ADP3196 to operate as a 2-, 3-, or 4-phase controller. A 340 Ω resistor should be placed between the 12 V system supply and the VCC pin. The internal shunt regulator maintains VCC = 5 V. Voltage Code DAC Inputs. These six pins are pulled down to GND, providing a logic zero if left open. When in normal operation mode, the DAC output programs the FB regulation voltage from 0.3750 V and 1.55 V (see Table 4). Rev. 0 | Page 8 of 20 ADP3196 TYPICAL PERFORMANCE CHARACTERISTICS 7200 6400 4800 4000 3200 2400 1600 800 0 0 100 200 300 400 500 600 700 RT (kΩ) 800 900 06371-015 FREQUENCY (kHz) 5600 Figure 6. Master Clock Frequency vs. RT Rev. 0 | Page 9 of 20 ADP3196 THEORY OF OPERATION The ADP3196 combines a multimode, fixed frequency PWM control with multiphase logic outputs for use in 2-, 3-, and 4-phase synchronous buck CPU core supply power converters. The internal VID DAC is designed to interface with the AMD 6-bit CPUs. 5V SUPPLY 0.8V ADP3196 EN Multiphase operation is important for producing the high currents and low voltages demanded by today’s microprocessors. Handling the high currents in a single-phase converter places high thermal demands on the components in the system, such as the inductors and MOSFETs. Balancing currents and thermals between phases • High speed response at the lowest possible switching frequency and output decoupling • Minimizing thermal switching losses by utilizing lower frequency operation • Tight load line regulation and accuracy • High current output due to 4-phase operation • Reduced output ripple due to multiphase cancellation • PC board layout noise immunity • Ease of use and design due to independent component selection • Flexibility in operation for tailoring design to low cost or high performance VDELAY(TH) (1.7V) DELAY VVID SS The multimode control of the ADP3196 ensures a stable, high performance topology for the following: • UVLO THRESHOLD VVID TD1 VCC_CORE TD2 VR READY (ADP3196 PWRGD) VID INVALID VID VALID 06371-006 CPU VID INPUTS TD3 Figure 7. System Start-Up Sequence PHASE DETECTION SEQUENCE START-UP SEQUENCE The ADP3196 follows the start-up sequence shown in Figure 7. After both the EN and UVLO conditions are met, the DELAY pin goes through one cycle (TD1). The first four clock cycles of TD2 are blanked from the PWM outputs and used for phase detection as explained in the Phase Detection Sequence section. Then, the soft start ramp is enabled (TD2) and the output comes up to the programmed DAC Voltage. After TD2 has been completed and the PWRGD masking time (equal to VID on-the-fly masking) is finished, a second ramp on the DELAY pin sets the PWRGD blanking (TD3). During startup, the number of operational phases and their phase relationship is determined by the internal circuitry that monitors the PWM outputs. Normally, the ADP3196 operates as a 4-phase PWM controller. Connecting the PWM4 pin to the VCC pin programs 3-phase operation while connecting the PWM4 pin and the PWM3 pin to the VCC pin programs 2-phase operation. While EN is low and prior to soft start, Pins PWM3 and PWM4 sink approximately 100 µA. An internal comparator checks the voltage of each pin vs. a threshold of 3 V. If the pin is tied to VCC, it is above the threshold. Otherwise, an internal current sink pulls the pin to GND, which is below the threshold. PWM1 and PWM2 are low during the phase detection interval, which occurs during the first four clock cycles of TD2. After this time, if the remaining PWM outputs are not pulled to VCC, the 100 µA current sink is removed and they function as normal PWM outputs. If they are pulled to VCC, the 100 µA current source is removed and the outputs are put into a high impedance state. The PWM outputs are logic-level devices intended for driving external gate drivers, such as the ADP3120A. Because each phase is monitored independently, operation approaching 100% duty cycle is possible. In addition, more than one output can be on at the same time to allow overlapping phases. Rev. 0 | Page 10 of 20 ADP3196 MASTER CLOCK FREQUENCY The clock frequency of the ADP3196 is set with an external resistor connected from the RT pin to ground. The frequency follows the graph in Figure 6. To determine the frequency per phase, the clock is divided by the number of phases in use. If all phases are in use, divide by 4. If PWM4 is tied to VCC, then divide the master clock by 3 for the frequency of the remaining phases. If PWM3 and PWM4 are tied to VCC, then divide by 2. OUTPUT VOLTAGE DIFFERENTIAL SENSING The ADP3196 combines differential sensing with a high accuracy VID DAC and reference and a low offset error amplifier. This maintains a worst-case specification of ±10 mV differential sensing error over its full operating output voltage and temperature range. The output voltage is sensed between the FB pin and the FBRTN pin. Pin FB should be connected through a resistor to the regulation point, usually the remote sense pin of the microprocessor. Pin FBRTN should be connected directly to the remote sense ground point. The internal VID DAC and precision reference are referenced to FBRTN, which has a minimal current of 65 μA to allow accurate remote sensing. The internal error amplifier compares the output of the DAC to the FB pin to regulate the output voltage. OUTPUT CURRENT SENSING The ADP3196 provides a dedicated current sense amplifier (CSA) to monitor the total output current for proper voltage positioning vs. load current and for current limit detection. Sensing the load current at the output gives the total average current being delivered to the load, which is an inherently more accurate method than peak current detection or sampling the current across a sense element, such as the low-side MOSFET. This amplifier can be configured several ways depending on the objectives of the system as follows: • Output inductor DCR sensing without a thermistor for lowest cost • Output inductor DCR sensing with a thermistor for improved accuracy with tracking of inductor temperature • Sense resistors for highest accuracy measurements The positive input of the CSA is connected to the CSREF pin, which is connected to the output voltage. The inputs to the amplifier are summed together through resistors from the sensing element, such as the switch node side of the output inductors, to the inverting input, CSSUM. The feedback resistor between CSCOMP and CSSUM sets the gain of the amplifier, and a filter capacitor is placed in parallel with this resistor. The gain of the amplifier is programmable by adjusting the feedback resistor. An additional resistor divider connected between CSREF and CSCOMP, with the midpoint connected to LLSET, can be used to set the load line required by the microprocessor. The current information is then given as CSREF – LLSET. This difference signal is used internally to offset the VID DAC for voltage positioning. The difference between CSREF and CSCOMP is then used as a differential input for the current-limit comparator. This allows the load line to be set independent of the current-limit threshold. In the event that the current-limit threshold and load line are not independent, the resistor divider between CSREF and CSCOMP can be removed and the CSCOMP pin can be directly connected to the LLSET pin. To disable voltage positioning entirely (that is, no load line), connect LLSET to CSREF. To provide the best accuracy for sensing current, the CSA is designed to have a low offset input voltage. In addition, the sensing gain is determined by external resistors to make it extremely accurate. ACTIVE IMPEDANCE CONTROL MODE For controlling the dynamic output voltage droop as a function of output current, a signal proportional to the total output current at the LLSET pin can be scaled to be equal to the droop impedance of the regulator times the output current. This droop voltage is then used to set the input control voltage to the system. The droop voltage is subtracted from the DAC reference input voltage directly to tell the error amplifier where the output voltage should be. This allows enhanced feed forward response. CURRENT CONTROL MODE AND THERMAL BALANCE The ADP3196 has individual inputs (SW1 to SW4) for each phase that are used for monitoring the current in each phase. This information is combined with an internal ramp to create a current balancing feedback system that has been optimized for initial current balance accuracy and dynamic thermal balancing during operation. This current balance information is independent of the average output current information used for positioning described previously in the Output Current Sensing section. The magnitude of the internal ramp can be set to optimize the transient response of the system. It also monitors the supply voltage for feed forward control for changes in the supply. A resistor connected from the power input voltage to the RAMPADJ pin determines the slope of the internal PWM ramp. External resistors can be placed in series with individual phases to create an intentional current imbalance, if desired, such as when one phase has better cooling and can support higher currents. Resistors RSW1 through RSW4 (see Figure 11) can be used for adjusting thermal balance. It is best to have the ability to add these resistors during the initial design, therefore, ensure that placeholders are provided in the layout. To increase the current in any given phase, make RSW for that phase larger (make RSW = 0 for the hottest phase and do not change during balancing). Increasing RSW to only 500 Ω makes a substantial increase in phase current. Increase each RSW value by small amounts to achieve balance, starting with the coolest phase first. Rev. 0 | Page 11 of 20 ADP3196 VOLTAGE CONTROL MODE DELAY TIMER A high gain, high bandwidth voltage mode error amplifier is used for the voltage mode control loop. The control input voltage to the positive input is set via the VID logic according to the voltages listed in Table 4. The delay times for the start-up timing sequence are set with a capacitor from the DELAY pin to ground. In UVLO or when EN is logic low, the DELAY pin is held at ground. After the UVLO and EN signals are asserted, the first delay time (TD1 in Figure 7) is initiated. A current flows out of the DELAY pin to charge CDLY. This current is equal to IREF, which is normally 15 µA. A comparator monitors the DELAY voltage with a threshold of 1.7 V. The voltage is also offset by the droop voltage for active positioning of the output voltage as a function of current, commonly known as active voltage positioning. The output of the amplifier is the COMP pin, which sets the termination voltage for the internal PWM ramps. The negative input (FB) is tied to the output sense location with Resistor RB and is used for sensing and controlling the output voltage at this point. A current source (equal to IREF/2) flows through RB into the FB pin and is used for setting the no load offset voltage from the VID voltage. The no load offset is positive with respect to the VID DAC. The main loop compensation is incorporated into the feedback network between FB and COMP. CURRENT REFERENCE The IREF pin is used to set an internal current reference. This reference current sets IFB, IDELAY, ISS, ILIMIT, and ITTSENSE. A resistor to ground programs the current based on the 1.5 V output. IREF = 1.5 V RIREF Typically, RIREF is set to 100 kΩ to program IREF = 15 µA. The following currents are then equal to: IFB = 1/2 (IREF) = 7.5 μA IDELAY = IREF = 15 μA ISS(STARTUP) = 1/4 (IREF) = 3.75 μA ISS(DAC) = 5/4 (IREF) = 18.75 μA ILIMIT = 2/3 (IREF) = 10 μA ITTSENSE = 8 (IREF) = 120 μA ENHANCED PWM MODE Enhanced PWM mode is intended to improve the transient response of the ADP3196 to a load stepup. In previous generations of controllers, when a load stepup occurred, the controller had to wait until the next turn on of the PWM signal to respond to the load change. Enhanced PWM mode allows the controller to respond immediately when a load stepup occurs. This allows the phases to respond when the load increase transition takes place. The delay time is therefore set by the IREF current charging a capacitor from 0 V to 1.7 V. This DELAY pin is used for two delay timings (TD1 and TD3) during the start-up sequence. In addition, DELAY is used for timing the current limit latch off as explained in the Current Limit, Short-Circuit, and Latch-Off Protection section. SOFT START The soft start ramp rates for the output voltage are set up with a capacitor from the soft start (SS) pin to ground. During startup, the SS pin sources a current of 3.75 μA. After startup, when a DAC code change occurs, the SS pin sinks or sources an 18.75 μA current to control the rate at which the output voltage can transition up or down. During startup (after TD1 and the phase detection cycle are complete), the SS time (TD2 in Figure 7) starts. The SS pin is disconnected from GND and the capacitor is charged up to the programmed DAC voltage by the SS amplifier, which has an output current equal to one quarter IREF (normally 3.75 µA). The voltage at the FB pin follows the ramping voltage on the SS pin, limiting the inrush current during startup. The soft start time depends on the value of the initial DAC voltage and CSS. Note that the DAC code must be set before the ADP3196 is enabled. Once the SS voltage is within 50 mV of the programmed DAC voltage, the power-good delay time (TD3) starts. Once TD2 has completed, the soft start current changes to 18.75 µA. If the programmed DAC code changes after startup, then the SS pin sources or sinks a current of 18.75 μA to or from the SS capacitor. This occurs until the SS voltage is within 50 mV of the newly programmed DAC voltage. If EN is taken low or VCC drops below UVLO, DELAY and SS are reset to ground in preparation for another soft start cycle. Figure 8 shows typical start-up waveforms for the ADP3196, while Figure 9 shows a typical DAC code change waveform. Rev. 0 | Page 12 of 20 ADP3196 A comparator monitors the DELAY voltage and shuts off the controller when the voltage reaches 1.7 V. The current limit latch-off delay time is therefore set by the current of IREF/4 charging the delay capacitor from 0 V to 1.7 V. This delay is four times longer then the delay time during the start-up sequence. 1 2 The current limit delay time only starts after the TD3 has completed. If there is a current limit during startup, the ADP3196 goes through TD1 to TD3, and then starts the latch-off time. Because the controller continues to cycle the phases during the latch-off delay time, if the short is removed before the 1.7 V threshold is reached, the controller returns to normal operation and the DELAY capacitor is reset to GND. 4 CH1 1V CH3 2V CH2 1V CH4 10V M 2ms A CH3 600mV 06371-007 3 Figure 8. Typical Start-Up Waveforms Channel 1: CSREF, Channel 2: SS, Channel 3: DELAY, Channel 4: Phase 1 Switch Node The latch-off function can be reset by either removing and reapplying the supply voltage to the ADP3196, or by toggling the EN pin low for a short time. To disable the short-circuit latch-off function, an external resistor should be placed in parallel with CDLY. This prevents the DELAY capacitor from charging up to the 1.7 V threshold. The addition of this resistor causes a slight increase in the delay times. During startup when the output voltage is below 200 mV, a secondary current limit is active. This is necessary because the voltage swing of CSCOMP cannot go below ground. This secondary current limit controls the internal COMP voltage to the PWM comparators to 1.5 V. This limits the voltage drop across the low-side MOSFETs through the current balance circuitry. 1 3 CH1 500mV CH3 5V CH2 500mV M 2ms A CH1 980mV 06371-008 2 An inherent per phase current limit protects individual phases if one or more phases stop functioning because of a faulty component. This limit is based on the maximum normal mode COMP voltage. Typical overcurrent latch-off waveforms are shown in Figure 10. Figure 9. Typical DAC Code Change Waveforms Channel 1: CSREF, Channel 2: SS, Channel 3: Phase 1 Switch Node CURRENT LIMIT, SHORT-CIRCUIT, AND LATCHOFF PROTECTION This current, through the external resistor, sets the ILIMIT voltage, which is internally scaled to give a current limit threshold of 82.6 mV/V. If the difference in voltage between CSREF and CSCOMP rises above the current limit threshold, the internal current limit amplifier controls the internal COMP voltage to maintain the average output current at the limit. If the limit is reached and TD3 has completed, a latch-off delay time starts, and the controller shuts down if the fault is not removed. The current limit delay time shares the DELAY pin timing capacitor with the start-up sequence timing. However, during current limit, the DELAY pin current is reduced to IREF/4. Rev. 0 | Page 13 of 20 1 2 3 4 CH1 1V CH3 2V CH2 2V CH4 10V M 2ms A CH1 600mV Figure 10. Overcurrent Latch-Off Waveforms Channel 1: CSREF, Channel 2: COMP, Channel 3: DELAY, Channel 4: Phase 1 Switch Node 06371-009 The ADP3196 compares a programmable current limit setpoint to the voltage from the output of the current sense amplifier. The level of current limit is set with the resistor from the ILIMIT pin to ground. During operation, the current from ILIMIT is equal to 2/3 of IREF, giving 10 µA normally. ADP3196 DYNAMIC VID The ADP3196 has the ability to respond to dynamically changing VID inputs while the controller is running. This allows the output voltage to change while the supply is running and supplying current to the load. This is commonly referred to as VID on-the-fly (OTF). A VID OTF can occur under either light or heavy load conditions. The processor signals the controller by changing the VID inputs in multiple steps from the start code to the finish code. This change can be positive or negative. When a VID input changes state, the ADP3196 detects the change and ignores the DAC inputs for a minimum of 400 ns. This time prevents a false code due to logic skew while the six VID inputs are changing. Additionally, the first VID change initiates the PWRGD and CROWBAR blanking functions for a minimum of 100 μs to prevent a false PWRGD or CROWBAR event. Each VID change resets the internal timer. POWER-GOOD MONITORING The power-good comparator monitors the output voltage via the CSREF pin. The PWRGD pin is an open-drain output whose high level, when connected to a pull-up resistor, indicates that the output voltage is within the nominal limits specified based on the VID voltage setting. PWRGD goes low if the output voltage is outside of this specified range, if the VID DAC inputs are in no CPU mode, or if the EN pin is pulled low. PWRGD is blanked during a VID OTF event for a period of 200 μs to prevent false signals during the time the output is changing. The PWRGD circuitry also incorporates an initial turn-on delay time (TD3) based on the DELAY timer. Prior to the SS voltage reaching the programmed VID DAC voltage and the PWRGD masking time finishing, the PWRGD pin is held low. Once the SS pin is within 50 mV of the programmed DAC voltage, the capacitor on the DELAY pin begins to charge. A comparator monitors the DELAY voltage and enables PWRGD when the voltage reaches 1.7 V. The PWRGD delay time is set, therefore, by a current of IREF charging a capacitor from 0 V to 1.7 V. OUTPUT CROWBAR To protect the load and output components of the supply, the PWM outputs are driven low which turns on the low-side MOSFETs when the output voltage exceeds the upper crowbar threshold. Turning on the low-side MOSFETs pulls down the output as the reverse current builds up in the inductors. If the output overvoltage is due to a short in the high-side MOSFET, this action current limits the input supply or blows its fuse, protecting the microprocessor from being destroyed. OUTPUT ENABLE AND UVLO For the ADP3196 to begin switching, the input supply (VCC) to the controller must be higher than the UVLO threshold, the EN pin must be higher than its 0.8 V threshold, and the DAC code must be valid. This initiates a system start-up sequence. If either UVLO or EN is less than their respective thresholds, the ADP3196 is disabled. This holds the PWM outputs at ground, shorts the DELAY capacitor to ground, and forces PWRGD, and OD signals low. In the application circuit, the OD pin should be connected to the OD inputs of the ADP3120A drivers. Grounding OD disables the drivers such that both DRVH and DRVL are grounded. This feature is important in preventing the discharge of the output capacitors when the controller is shut off. If the driver outputs are not disabled, a negative voltage can be generated during output due to the high current discharge of the output capacitors through the inductors. THERMAL MONITORING The ADP3196 includes a thermal monitoring circuit to detect when a point on the VR has exceeded two different userdefined temperatures. The thermal monitoring circuit requires an NTC thermistor to be placed between TTSENSE and GND. A fixed current of 8 × IREF (normally giving 123 μA) is sourced out of the TTSENSE pin and into the thermistor. The current source is internally limited to 5 V. An internal circuit compares the TTSENSE voltage to a 1.105 V and a 0.81 V threshold and outputs an open-drain signal at the VRM_OFF and VRMHOT outputs, respectively. The VRM_HOT open-drain output goes high once the voltage on the TTSENSE pin goes below the VRM_HOT thresholds and signals the system that an overtemperature event has occurred. The VRM_OFF output asserts when the voltage on the TTSENSE pin exceeds the VRM_OFF threshold. Because the TTSENSE voltage changes slowly with respect to time, 50 mV of hysteresis is built into these comparators. The thermal monitoring circuitry does not depend on EN and is active when UVLO is above its threshold. When UVLO is below its threshold, VRFAN and VRHOT are forced low. Rev. 0 | Page 14 of 20 ADP3196 Table 4. VID Codes OUTPUT 1.550 1.525 1.500 1.475 1.450 1.425 1.400 1.375 1.350 1.325 1.300 1.275 1.250 1.225 1.200 1.175 1.150 1.125 1.100 1.075 1.050 1.025 1.000 0.975 0.950 0.925 0.900 0.875 0.850 0.825 0.800 0.775 VID5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 VID2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 VID1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 OUTPUT 0.7625 0.7500 0.7375 0.7250 0.7125 0.7000 0.6875 0.6750 0.6625 0.6500 0.6375 0.6250 0.6125 0.6000 0.5875 0.5750 0.5625 0.5500 0.5375 0.5250 0.5125 0.5000 0.4875 0.4750 0.4625 0.4500 0.4375 0.4250 0.4125 0.4000 0.3875 0.3750 Rev. 0 | Page 15 of 20 VID5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 VID2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 VID1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Figure 11.Typical 4-Phase Application Circuit Rev. 0 | Page 16 of 20 2 1 R3 1Ω RA 18.7kΩ CDLY 18nF CA 630pF CFB 16pF RTH1 100kΩ, 5% NTC CSS 10nF C5 1nF C6 0.1µF 1 RT 130kΩ 1% RLIM 160kΩ 1% EN PWRGD FBRTN FB COMP SS DELAY VRM_OFF VRMHOT TTSENSE 40 + C4 1µF 680Ω FROM CPU C3 100µF (C3 OPTIONAL) 680Ω 12V C2 + ADP3196 U1 C7 1nF RPH3 RCS1 RCS2 35.7kΩ 88.7kΩ 140kΩ 1% CONNECT NEAR EACH INDUCTOR. CCS2 1nF 5% NPO CCS1 1nF 5% NPO RSW21 RPH4 140kΩ 1% RSW41 RSW31 RIREF 100kΩ PWM1 PWM2 PWM3 PWM4 NC SW1 SW2 SW3 SW4 IMON FOR A DESCRIPTION OF OPTIONAL RSW RESISTORS, SEE THE THEORY OF OPERATION SECTION. C8 1nF RB 2kΩ CB 630pF POWER GOOD VRM_OFF VRMHOT VTT I/O R2 169kΩ 1% 1µF 1kΩ C1 + NC VID0 VID1 VID2 VID3 VID4 VID5 NC NC VCC ILIMIT RT RAMPADJ LLSET CSREF CSSUM CSCOMP GND OD IREF VIN RTN 2700µF/16V/3.3A×2 SANYO MV-WX SERIES RPH2 140kΩ 1% RSW11 RPH1 140kΩ 1% C22 4.7µF D5 1N4148 C18 4.7µF D4 1N4148 C14 4.7µF D3 1N4148 C10 4.7µF D2 1N4148 C9 18nF PGND DRVL C13 18nF OD VCC R5 2.2Ω 3 4 C17 18nF DRVL PGND SW DRVH 5 6 7 8 C21 18nF 5 PGND DRVL VCC 4 SW DRVH OD IN 2 3 BST 1 5 6 7 8 C23 U5 ADP3120A 10nF R7 2.2Ω DRVL OD VCC 6 PGND 3 4 7 IN 8 SW BST 2 DRVH C19 U4 ADP3120A 10nF R6 2.2Ω VCC OD IN BST U3 C15 ADP3120A 10nF 5 1 4 3 2 1 7 SW IN 2 6 8 DRVH BST 1 U2 C11 ADP3120A 10nF R4 2.2Ω Q11 IPD09N03L Q8 IPD09N03L Q5 IPD09N03L Q2 IPD09N03L Q12 IPD09N03L L5 280nH/1.4mΩ Q10 IPD09N03L C24 4.7µF Q9 IPD09N03L L4 280nH/1.4mΩ Q7 IPD09N03L C20 4.7µF Q6 IPD09N03L L3 280nH/1.4mΩ Q4 IPD09N03L C16 4.7µF Q3 IPD09N03L + C25 RTH2 100kΩ, 5% NTC 10Ω2 10Ω2 10Ω2 10Ω2 + C32 560µF/4V × 7 L2 280nH/1.4mΩ SANYO SEPC SERIES 5mΩ EACH C12 4.7µF Q1 IPD09N03L VSS(SENSE) VCC(SENSE) 10µF × 8 MLCC VCC(CORE) RTN VCC(CORE) 0.375V TO 1.55V 100A TDC 06371-010 VIN 12V L1 370nH 18A ADP3196 ADP3196 LAYOUT AND COMPONENT PLACEMENT The following guidelines are recommended for optimal performance of a switching regulator in a PC system. General Recommendations For good results, a PCB with at least four layers is recommended. This provides the needed versatility for control circuitry interconnections with optimal placement, power planes for ground, input and output power, and wide interconnection traces in the remainder of the power delivery current paths. Keep in mind that each square unit of 1-ounce copper trace has a resistance of ~0.53 mΩ at room temperature. Whenever high currents must be routed between PCB layers, use vias liberally to create several parallel current paths, so the resistance and inductance introduced by these current paths is minimized and the via current rating is not exceeded. If critical signal lines (including the output voltage sense lines of the ADP3196) must cross through power circuitry, it is best to interpose a signal ground plane between those signal lines and the traces of the power circuitry. This serves as a shield to minimize noise injection into the signals at the expense of making signal ground a bit noisier. An analog ground plane should be used around and under the ADP3196 as a reference for the components associated with the controller. This plane should be tied to the nearest output decoupling capacitor ground and should not be tied to any other power circuitry to prevent power currents from flowing into it. The components around the ADP3196 should be located close to the controller with short traces. The most important traces to keep short and away from other traces are the FB pin and CSSUM pin. The output capacitors should be connected as close as possible to the load (or connector), for example, a microprocessor core, that receives the power. If the load is distributed, the capacitors should also be distributed and generally be in proportion to where the load tends to be more dynamic. Avoid crossing any signal lines over the switching power path loop (described in the Power Circuitry Recommendations section). Power Circuitry Recommendations The switching power path should be routed on the PCB to encompass the shortest possible length to minimize radiated switching noise energy (EMI) and conduction losses in the board. Failure to take proper precautions often results in EMI problems for the entire PC system and noise-related operational problems in the power converter control circuitry. The switching power path is the loop formed by the current path through the input capacitors and the power MOSFETs, including all interconnecting PCB traces and planes. Using short and wide interconnection traces is especially critical in this path for two reasons: it minimizes the inductance in the switching loop, which can cause high energy ringing; and it accommodates the high current demand with minimal voltage loss. When a power dissipating component, for example, a power MOSFET, is soldered to a PCB, it is recommended to liberally use the vias, both directly on the mounting pad and immediately surrounding it. Two important reasons for this are improved current rating through the vias and improved thermal performance from vias extended to the opposite side of the PCB, where a plane can more readily transfer the heat to the air. Make a mirror image of any pad being used to heat sink the MOSFETs on the opposite side of the PCB to achieve the best thermal dissipation in the air around the board. To further improve thermal performance, use the largest possible pad area. The output power path should also be routed to encompass a short distance. The output power path is formed by the current path through the inductor, the output capacitors, and the load. For best EMI containment, a solid power ground plane should be used as one of the inner layers extending fully under all the power components. Signal Circuitry Recommendations The output voltage is sensed and regulated between the FB pin and the FBRTN pin, which connect to the signal ground at the load. To avoid differential mode noise pickup in the sensed signal, the loop area should be small. Thus, the FB trace and FBRTN trace should be routed adjacent to each other on top of the power ground plane back to the controller. The feedback traces from the switch nodes should be connected as close as possible to the inductor. The CSREF signal should be connected to the output voltage at the nearest inductor to the controller. Rev. 0 | Page 17 of 20 ADP3196 OUTLINE DIMENSIONS 6.00 BSC SQ 0.60 MAX 0.60 MAX 31 30 PIN 1 INDICATOR TOP VIEW 0.50 BSC 5.75 BCS SQ 0.50 0.40 0.30 12° MAX 1.00 0.85 0.80 PIN 1 INDICATOR 40 1 4.25 4.10 SQ 3.95 EXPOSED PAD (BOTTOM VIEW) 10 11 21 20 0.25 MIN 4.50 REF 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.30 0.23 0.18 SEATING PLANE 0.20 REF COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2 Figure 12. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 6 mm × 6 mm Body, Very Thin Quad (CP-40) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option Ordering Qty ADP3196JCPZ-RL1 0°C to 85°C 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-40 2,500 1 Z= Pb-free part. Rev. 0 | Page 18 of 20 ADP3196 NOTES Rev. 0 | Page 19 of 20 ADP3196 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06371-0-10/06(0) Rev. 0 | Page 20 of 20