L6668 SMART PRIMARY CONTROLLER PRELIMINARY DATA 1 General Features Figure 1. Package MULTIPOWER BCD TECHNOLOGY LOAD-DEPENDENT CURRENT-MODE CONTROL: FIXED-FREQUENCY (HEAVY LOAD), FREQUENCY FOLDBACK (LIGHT LOAD), BURST-MODE (NO-LOAD) ■ ON-BOARD HIGH-VOLTAGE START-UP ■ IMPROVED STANDBY FUNCTION ■ LOW QUIESCENT CURRENT (< 2 mA) ■ SLOPE COMPENSATION ■ PULSE-BY-PULSE & HICCUP-MODE OCP ■ INTERFACE WITH PFC CONTROLLER ■ DISABLE FUNCTION (ON/OFF CONTROL) ■ LATCHED DISABLE FOR OVP/OTP FUNCTION ■ PROGRAMMABLE SOFT-START ■ 2% PRECISION REFERENCE VOLTAGE EXTERNALLY AVAILABLE ■ ±800 mA TOTEM POLE GATE DRIVER WITH INTERNAL CLAMP AND UVLO PULL-DOWN ■ BLUE ANGEL, ENERGY STAR, EU CODE OF CONDUCT COMPLIANT Figure 2. Block Diagram ■ ■ S-COMP SO-16 (Narrow) Table 1. Order Codes Part Number L6668 SO-16 L6668TR SO-16 in Tape & Reel SO16 PACKAGE ECOPACK® ■ 1.1 APPLICATIONS HI-END AC-DC ADAPTERS/CHARGERS FOR NOTEBOOKS. LCD/CRT MONITORS, LCD/CRT TV DIGITAL CONSUMER ■ ■ ■ V CC HV 15 Package 5 1 SLOPE COMP. VREG 25V Vref 16 RCT HV generator ON/OFF and UVLO management CLK TIMING 8 VREF Vcc_OK DIS R + 7 S Q - DIS 2.2V N.C. 15V 4 OUT 6 S BLANKING Q R 12 HICCUP R + ISEN + PWM - S Vcc_OK DIS OCP Q 3 VREG GND - - HYST. CTRL 1.5V + 0.4mA PFC_STOP 13 + 14 DIS OCP STANDBY 2.2/2.7V ST-BY 11R 0.8V 4R SOFT-START 11 9 SKIPADJ SS 10 COMP May 2005 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. Rev. 1 1/23 L6668 2 Description L6668 is a current-mode primary controller IC, designed to build single-ended converters. The IC drives the system at fixed frequency at heavy load and an improved Standby function causes a smooth frequency reduction as the load is progressively reduced. At very light load the device enters a special operating mode (burst-mode with fixed, externally programmed peak current) that, in addition to the on-board high-voltage start-up and the very low quiescent current, helps keep low the consumption from the mains and be compliant with energy saving regulations. To allow meeting compliance with these standards in power-factor-corrected systems too, an interface with the PFC controller is provided that enables to turn off the pre-regulator when the load level falls below a threshold. The IC includes also a programmable soft-start, slope compensation for stable operation at duty cycles greater then 50%, a disable function, a leading edge blanking on current sense to improve noise immunity, latched disable for OVP or OTP shutdown and an effective two-level OCP able to protect the system even in case the secondary diode fails short. Table 2. Absolute Maximum Ratings Symbol Pin Vcc 5 VHV IHV Value Unit IC Supply voltage (Icc = 20 mA) Self-limited V 1 High-voltage start-up generator voltage range -0.3 to 700 V 1 High-voltage start-up generator current Self-limited A Analog Inputs & Outputs, except pin 14 -0.3 to 8 V --- Parameter IPFC_STOP 14 Max. sink current (low state) 2 mA VPFC_STOP 14 Max. voltage (open state) 16 V 0.75 W Junction Temperature Operating range -25 to 150 °C Storage Temperature -55 to 150 °C Ptot Tj Tstg Power Dissipation @Tamb = 50°C Table 3. Thermal Data Symbol Rth j-amb Parameter Thermal Resistance Junction to AmbientMax Figure 3. Pin Connection (Top view) 2/23 HV RCT HVS S-COMP GND PFC_STOP OUT STBY Vcc ISEN N.C. SS DIS COMP VREF SKIPADJ Value Unit 120 °C/W L6668 Table 4. Pin Description Pin Number Pin Name Function 1 HV High-voltage start-up. The pin is to be connected directly to the rectified mains voltage. A 0.8 mA internal current source charges the capacitor connected between pin Vcc and GND to start up the IC. When the voltage on the Vcc pin reaches the start-up threshold the generator is shut down. Normally it is re-enabled when the voltage on the Vcc pin falls below 5V, except under latched shutdown conditions, when it is re-enabled as the Vcc voltage falls 0.5V below the start-up threshold. 2 HVS High-voltage spacer. The pin is not connected internally to isolate the high-voltage pin and comply with safety regulations (creepage distance) on the PCB. 3 GND Chip ground. Current return for both the gate-drive current and the bias current of the IC. All of the ground connections of the bias components should be tied to a track going to this pin and kept separate from any pulsed current return. 4 OUT Gate-drive output. The driver is capable of 0.8A min. source/sink peak current to drive MOSFET’s. The voltage delivered to the gate is clamped at about 15V so as to prevent too high values when the IC is supplied with a voltage close to or exceeding 20V. 5 Vcc Supply Voltage of both the signal part of the IC and the gate driver. The internal high voltage generator charges an electrolytic capacitor connected between this pin and GND as long as the voltage on the pin is below the start-up threshold of the IC, after that it is disabled. Sometimes a small bypass capacitor (0.1µF typ.) to GND might be useful to get a clean bias voltage for the signal part of the IC. 6 N.C. Connect the pin to GND. 7 DIS Latched device shutdown. Internally the pin connects a comparator that, when the voltage on the pin exceeds 2.2V, shuts the IC down and brings its consumption to a value barely higher than before start-up. The information is latched and it is necessary to recycle the input power to restart the IC: the latch is removed as the voltage on the Vcc pin goes below the UVLO threshold. Connect the pin to GND if the function is not used. 8 VREF Voltage reference. An internal generator furnishes an accurate voltage reference (5V±4%, all inclusive) that can be used to supply up to 5 mA to an external circuit. A small film capacitor (0.1µF typ.), connected between this pin and GND is recommended to ensure the stability of the generator and to prevent noise from affecting the reference. 9 SKIPADJ Burst-mode control threshold. A voltage is applied to this pin, derived from the reference voltage VREF via a resistor divider. When the control voltage at pin COMP falls 50 mV below the voltage on this pin the IC is shutdown and the consumption is reduced. The chip is re-enabled as the voltage on pin COMP exceeds the voltage on the pin. The high-voltage start-up generator is not invoked. The function is disabled during the soft-start ramp. The pin must always be biased between 0.8 and 2.5V. A voltage between 0.8 and 1.4V disables the function, if the pin is pulled below 0.8V the IC is shut down. 10 COMP Control input for PWM regulation. The pin is to be driven by the phototransistor (emittergrounded) of an optocoupler to modulate the voltage by modulating the current sunk from (sourced by) the pin (0.4 mA typ.). It is recommended to place a small filter capacitor between the pin and GND, as close to the IC as possible to reduce switching noise pick up, to set a pole in the output-to-control transfer function. A voltage 50 mV lower than that on pin SKIPADJ shuts down the IC and reduces its current consumption. 11 SS Soft start. An internal 20µA generator charges an external capacitor connected between the pin and GND generating a voltage ramp across it. This ramp clamps the voltage at pin COMP during start-up, thus the duty cycle of the power switch starts from zero. During the ramp all functions monitoring the voltage at pin COMP are disabled. The SS capacitor is quickly discharged as the chip goes into UVLO. 12 ISEN Current sense (PWM comparator) input. The voltage on this pin is internally compared with an internal reference derived from the voltage on pin COMP and when they are equal the gate drive output (previously asserted high by the clock signal generated by the oscillator) is driven low to turn off the power MOSFET. The pin is equipped with 200 ns. min. blanking time for improved noise immunity. A second comparison level located at 1.5V shuts the device down and brings its consumption almost to a “before start-up” level. 3/23 L6668 Table 4. Pin Description (continued) Pin Number Pin Name Function 13 STBY Standby function. This pin is a high-impedance one as long as the voltage on pin COMP is higher than 3V. When the voltage on pin COMP falls below 3V, the voltage on the pin tracks that on pin COMP and is capable of sinking current. A resistor connected from the pin to the oscillator allows programming frequency foldback at light load. 14 PFC_STOP Open-drain ON/OFF control of PFC controller. This pin is intended for driving the base of a PNP transistor in systems comprising a PFC pre-regulator, to stop the PFC controller at light load by cutting its supply. The pin, normally low, opens if the voltage on COMP is lower than 2.2V and goes back low when the voltage on pin COMP exceeds 2.7V. Whenever the IC is shutdown, either latched (DIS>1.5V, ISEN >1.5V) or not (UVLO, SKIPADJ<0.8), the pin is open as well. 15 S-COMP Voltage ramp for slope compensation. When the gate-drive output is high the pin delivers a voltage tracking the oscillator ramp (shifted down by one VBE); when the gate-drive output is low the voltage delivered is zero. The pin is to be connected to pin ISEN via a resistor to make slope compensation and allow stable operation at duty cycles close to and greater than 50%. 16 RCT Oscillator pin. A resistor to VREF and a capacitor to GND define the oscillator frequency (at full load). A resistor connect to STBY modifies the oscillator frequency when the voltage on pin COMP is lower than 3V. Table 5. Electrical Characteristcs (Tj = 0 to 105°C, Vcc=15V, Co=1nF; RT =13.3k , CT =1nF; unless otherwise specified) Symbol Parameter Test Condition Min. Typ. Max. Unit 22 V 12.5 13.5 14.5 V 8.0 8.7 9.4 V 24 28 V SUPPLY VOLTAGE Vcc Operating range After turn-on VCCOn Turn-on threshold (1) VCCOff Turn-off threshold (1) Hys Hysteresis VZ Zener Voltage After turn-on 9.4 4.0 Icc = 20 mA 22 V SUPPLY CURRENT Istart-up Iq Start-up Current Before turn-on, Vcc=VccON-0.5 Quiescent Current After turn-on ICC Operating Supply Current Iqdis Shutdown quiescent current 150 2 VDIS > 2.2, or VISEN > 1.5 µA 2.5 mA 4 mA 180 VSKIPADJ<0.8 1 0.8 <VCOMP < VSKIPADJ µA 1.8 1.3 mA mA HIGH-VOLTAGE START-UP GENERATOR VHV VHVstart Breakdown voltage IHV < 100 µA Start voltage IVcc < 100 µA Icharge Vcc charge current VHV > VHvstart, Vcc > 3V IHV, ON ON-state current IHV, OFF Leakage current (OFF state) VCCrestart HV generator restart voltage V 50 80 110 V 0.55 0.85 1 mA VHV > VHvstart, Vcc > 3V 1.6 mA VHV > VHvstart, Vcc = 0 0.8 VHV = 400 V (1) After 4/23 700 DIS tripping 40 µA 4.4 5 5.6 V 12 13 14 V L6668 Table 5. Electrical Characteristcs (continued) (Tj = 0 to 105°C, Vcc=15V, Co=1nF; RT =13.3k , CT =1nF; unless otherwise specified) Symbol Parameter Test Condition Min. Typ. Max. Unit 4.925 5 5.075 V REFERENCE VOLTAGE VREF Output voltage (2) VREF Total variation Vcc= 9.4 to 22 V, IREF = 1 to 5 mA 4.8 5.13 V IREF Short circuit current VREF = 0 10 30 mA Sink capability in UVLO Vcc = 6V; Isink = 0.5 mA 0.2 0.5 V 400 480 µA Tj = 25 °C; IREF = 1 mA PWM CONTROL VCOMPH Maximum level ICOMP =0 5.5 ICOMP Max. source current VCOMP = 1 V 320 RCOMP Dynamic resistance VCOMP = 2 to 4 V Dmax Maximum duty cycle VCOMP = 5 V Dmin Minimum duty cycle V 22 70 kΩ 75 % VCOMP = 1 V 0 % -1 µA ns CURRENT SENSE COMPARATOR IISEN Input Bias Current VISEN = 0 tLEB Leading Edge Blanking After gate drive low-to-high transition td(H-L) VISENdis 225 290 100 ns 3.56 3.75 3.94 V/V 0.725 0.8 0.875 V 1.35 1.5 1.65 V Delay to Output Gain VISENx 160 Maximum signal VCOMP = 5 V Hiccup-mode OCP level (2) STANDBY FUNCTION Vdrop Vth VCOMP - VSTBY ISTBY = 0.8 mA, VCOMP<3V Threshold on VCOMP (2) Voltage falling Hysteresis 35 mV 3 V 50 mV LATCHED DISABLE FUNCTION IDIS Input Bias Current VDIS = 0 to Vth Vth Disable threshold (2) voltage rising -1 µA 2.1 2.2 2.3 V 95 100 105 kHz OSCILLATOR fsw Oscillation Frequency Tj = 25°C, VCOMP = 5 V 93 100 107 kHz Vpk Oscillator peak voltage (2) 2.85 3 3.15 V Vvy Oscillator valley voltage (2) 0.75 0.9 1.05 V Vcc = 9.4 to 22V, VCOMP = 5 V SLOPE COMPENSATION S-COMPpk Ramp peak RS-COMP = 3 kΩ to GND, OUT pin high, VCOMP = 5 V 1.6 1.75 1.9 V S-COMPvy Ramp starting value RS-COMP = 3 kΩ to GND, OUT pin high 0.15 0.35 0.55 V Ramp voltage OUT pin low Source capability VS-COMP = VS-COMPpk 0.8 0 Tj = 25 °C 14 mA SOFT-START ISSC Charge current 20 26 µA 5/23 L6668 Table 5. Electrical Characteristcs (continued) (Tj = 0 to 105°C, Vcc=15V, Co=1nF; RT =13.3k , CT =1nF; unless otherwise specified) Symbol Parameter VSSsat Low saturation voltage VSSclamp High saturation voltage Test Condition Min. Typ. Duty cycle = 0 Max. Unit 0.6 V 7 V SKIPADJ FUNCTION Ibias VSKIP Input Bias Current VSKIP = 0 to 4.5 V -1 Operating range Hys Hysteresis Below VSKIP VOFF Shutdown threshold Voltage falling µA 1.4 2.5 V 25 85 mV 0.8 V PFC_STOP FUNCTION Ileak High level leakage current VPFC_STOP < 16V, VCOMP = 2V 1 µA VL Low saturation level IPFC_STOP = 1mA, VCOMP = 4V 0.1 V Vth Threshold for high level VCOMP falling Vth Threshold for high level VCOMP rising (2) (2) 2.1 2.2 2.3 V 2.55 2.7 2.85 V 1.0 V GATE DRIVER VOL Output Low Voltage Isink = 200 mA VOH Output High voltage Isource = 5 mA, Vcc = 12V Isourcepk Peak source current -0.8 A Isinkpk Peak sink current 0.8 A tf Current Fall Time 30 ns tr Current Rise Time 55 ns VOclamp (1), (2) Output clamp voltage Isource = 5mA; Vcc = 20V UVLO saturation Vcc= 0 to Vccon, Isink= 2mA 9.8 10 10.3 12 Parameters in tracking each other Figure 4. Typical System Block Diagram PFC PRE-REGULATOR DC-DC CONVERTER Vinac Voutdc PWM is turned off in case of PFC's anomalous operation, for safety L6561/2 or L6563 L6668 PFC can be turned off at light load to ease compliance with energy saving regulations. 6/23 V 15 V 1.1 V L6668 3 Typical Electrical Performance Figure 5. High-voltage generator ON-state sink current vs. Tj Figure 8. High-voltage generator start voltage vs. Tj HV IHV (pin 1) 120% 1.2 [mA] Vcc ≥ 3V 1 110% 0.8 VHV = 100 V 100% 0.6 90% 0.4 Vcc = 0 Values normalized to VHV @ 25°C 0.2 -50 0 50 100 80% -50 150 0 50 100 150 Tj (°C) Tj (°C) Figure 6. High-voltage generator output (Vcc charge current) vs. Tj Figure 9. High-voltage generator Vcc restart voltage vs. Tj Vcc (pin 5) Icc (pin 5) 14 120% [V] VHV = 100 V 12 while latched off 10 VHV = 100 V 110% 100% 8 90% normal operation 6 Values normalized to Icc @ 25°C 80% -50 0 50 100 150 4 -50 0 50 100 150 Tj (°C) Tj (°C) Figure 7. High-voltage pin leakage vs. Tj Figure 10. IC consumption vs. Tj Icc (pin 5) IHV (pin 1) 5 40 [mA] [µA] Operating 3 VHV = 400 V Vcc = 15V Quiescent 2 30 1 20 0.5 Disabled or during burst-mode Vcc = 15 V Co = 1 nF f = 100 kHz 0.3 10 0.2 Latched off Before start-up (Vcc=12V) 0 -50 0 50 Tj (°C) 100 150 0.1 -50 0 50 100 150 Tj (°C) 7/23 L6668 Figure 11. Start-up & UVLO vs. Tj Figure 14. COMP source current vs. Tj VCC (pin 5) (V) 14 ICOMP(pin 10) 140% ON Vcc = 15 V VCOMP= 1 V 13 12 OFF while latched off 120% 100% 11 10 80% 9 OFF Values normalized to COMP I @ 25°C 8 -50 0 50 100 60% -50 150 0 50 100 150 Tj (°C) Tj (°C) Figure 12. Vcc Zener voltage vs. Tj Figure 15. COMP dynamic resistance vs. Tj RCOMP VccZ (pin 5) (V) 26 (kW) (pin 10) 32 30 25 28 24 26 23 24 22 22 Vcc = 15 V 21 20 -50 20 0 50 100 150 18 -50 0 Tj (°C) 50 100 150 Tj (°C) Figure 13. COMP voltage upper clamp level vs. Tj Figure 16. Max. duty-cycle vs. Tj (%) VCOMP(pin 10) 7 (V) 75 Vcc = 15 V Vcc = 15 V 74 6.5 73 6 72 5.5 5 -50 71 0 50 Tj (°C) 8/23 100 150 70 -50 0 50 Tj (°C) 100 150 L6668 Figure 17. Oscillator frequency vs. Tj Figure 20. Disable level on current sense vs. Tj fsw Vpin12 (V) 2.0 102% Vcc = 22V RT = 13.3 kΩ CT = 1 nF 101.5% Vcc = 15 V 1.8 101% Vcc = 15V 100.5% 1.6 Vcc = 9.4V 1.4 100% 1.2 99.5% Values normalized to sf w @ Tj=25°C, Vcc=15V 99% -50 0 50 100 150 1.0 -50 0 50 Tj (°C) Figure 18. Oscillator ramp vs. Tj 150 Figure 21. Reference voltage vs. Tj Vpin14 (V) 100 Tj (°C) VREF (pin 8) (V) 5.1 3.5 Peak Vcc = 15 V 3.0 5.05 Vcc = 15 V 2.5 5 2.0 1.5 4.95 Valley 1.0 0.5 -50 0 50 100 150 4.9 -50 0 Tj (°C) Figure 19. Current sense clamp vs. Tj V ISENx (V) 1 50 100 150 Tj (°C) Figure 22. PFC_STOP open/low thresholds on VCOMP vs. Tj (pin 12) VCOMP (pin 10) (V) 2.8 PFC_STOP low (voltage rising) 2.7 Vcc = 15 V VCOMP= Upper clamp 0.9 2.6 Vcc = 15 V 2.5 0.8 2.4 2.3 0.7 PFC_STOP open (voltage falling) 2.2 0.6 -50 0 50 Tj (°C) 100 150 2.1 -50 0 50 100 150 Tj (°C) 9/23 L6668 Figure 23. Standby thresholds vs. Tj Figure 26. SKIPADJ hysteresis vs. Tj VCOMP (pin 10) 3.6 (V) Vpin9 100.0 (mV) Vcc = 15 V 3.4 3.2 80.0 Vcc = 15 V Disable (voltage rising) 60.0 Vskipadj = 2.5 V 3 Enable (voltage falling) 40.0 Vskipadj = 1.4 V 2.8 20.0 2.6 2.4 -50 0 50 100 0.0 -50 150 0 50 100 150 Tj (°C) Tj (°C) Figure 24. Standby pin dropout vs. Tj Figure 27. SKIPADJ disable threshold vs. Tj Vpin13 - Vpin10 Vpin9 1.0 0 (mV) (V) Vcc = 15 V VCOMP= 2V ISTBY = 0.8 mA -5 Vcc = 15 V 0.9 -10 0.8 -15 0.7 -20 0.6 -25 -30 -50 0 50 100 0.5 -50 150 0 50 100 150 Tj (°C) Tj (°C) Figure 25. DIS threshold vs. Tj Figure 28. Soft-start charge current vs. Tj V pin 7 2.5 (V) Iss ( pin11) 40.0 (µA) Vcc = 15 V Vcc = 15 V 2.4 30.0 2.3 20.0 2.2 10.0 2.1 2.0 -50 0 50 Tj (°C) 10/23 100 150 0.0 -50 0 50 Tj (°C) 100 150 L6668 Figure 29. S-COMP ramp vs. Tj Figure 32. Gate-drive output low saturation V pin4 [V] Vpin15 2.0 (V) 5 Tj = 25 °C Vcc = 12 V SINK Peak 4 Vcc = 15 V RS-SCOMP = 3 kΩ 1.5 3 1.0 2 0.5 1 Valley 0 0.0 -50 0 50 100 0 200 400 150 600 800 1,000 1,200 IGD [mA] Tj (°C) Figure 30. UVLO saturation vs. Tj Figure 33. Gate-drive output high saturation Vpin4 [V] Vpin4 (V) 1 Vcc = 0 V Tj = 25 °C Vcc = 12 V SOURCE Vcc - 2.0 0.9 Vcc - 3.0 0.8 Vcc - 4.0 0.7 Vcc - 5.0 0.6 Vcc - 6.0 0.5 -50 0 0 50 100 150 200 400 600 800 1,000 IGD [mA] Tj (°C) Figure 31. Gate-drive clamp vs. Tj Vpin4 clamp (V) 13 Vcc = 20 V 12.8 12.6 12.4 12.2 12 -50 0 50 100 150 Tj (°C) 11/23 L6668 4 Application Information The L6668 is a versatile current-mode PWM controller specific for offline fixed-frequency, peak-currentmode-controlled flyback converters. The device is able to operate in different modes (fig. 34), depending on the converter's load conditions: 1) Fixed frequency at heavy load. In this region the IC operates exactly like a standard current mode control chip: a relaxation oscillator, externally programmable with a capacitor and a resistor, generates a sawtooth and releases a clock pulse during the falling edge of the sawtooth; the power switch is turned on by the clock pulses and is turned off by the control loop. 2) Frequency-foldback mode at medium and light load. As the load is reduced the oscillator frequency is reduced as well by slowing down the charge of the timing capacitor proportionally to the load itself. 3) Burst-mode control with no or very light load. When the load is extremely light or disconnected, the converter will enter a controlled on/off operation with constant peak current. A load decrease will be then translated into a frequency reduction, which can go down even to few hundred hertz, thus minimizing all frequencyrelated losses and making it easier to comply with energy saving regulations. Being the peak current very low, no issue of audible noise arises. Burst mode Figure 34. Multi-mode operation of the L6668 Fixed-frequency mode Frequency foldback mode f sw 0 0 Pinmax Pin 4.1 High-voltage start-up generator Figure 35 shows the internal schematic of the high-voltage start-up generator (HV generator). It is made up of a high-voltage N-channel FET, whose gate is biased by a 15 MΩ resistor, with a temperature-compensated current generator connected to its source. Figure 35. High-voltage start-up generator: internal schematic HV L6668 1 15 MΩ Vcc_OK HV_EN IHV 5 Vcc CONTROL I charge 3 GND The HV generator is physically located on a separate chip, made with BCD off-line technology able to withstand 700V, controlled by a low-voltage chip, where all of the control functions reside. 12/23 L6668 With reference to the timing diagram of figure 36, when power is first applied to the converter the voltage on the bulk capacitor (Vin) builds up and, as it reaches about 80V, the HV generator is enabled to operate (HV_EN is pulled high) so that it draws about 1 mA. This current, diminished by the IC consumption, charges the bypass capacitor connected between pin Vcc (5) and ground and makes its voltage rise almost linearly. Figure 36. Timing diagram: normal power-up and power-down sequences Vin V HVstart regulation is lost here Vcc t Vcc ON Vcc OFF Vcc restart t OUT t HV_EN t Vcc_OK IHV t 1 mA Normal operation Power-up Power-down t As the Vcc voltage reaches the start-up threshold (13.5V typ.) the low-voltage chip starts operating and the HV generator is cut off by the Vcc_OK signal asserted high. The IC is powered by the energy stored in the Vcc capacitor until the self-supply circuit (typically an auxiliary winding of the transformer and a steering diode) develops a voltage high enough to sustain the operation. The residual consumption of this circuit is just the one on the 15MΩ resistor (≈10 mW at 400 Vdc), typically 50-70 times lower, under the same conditions, as compared to a standard start-up circuit made with an external dropping resistor. Figure 37. Timing diagram showing short-circuit behavior Vcc Short circuit occurs here Vcc ON Vcc OFF Vcc rest OUT Vcc_OK IHV t t t 1 mA t 13/23 L6668 At converter power-down the system will lose regulation as soon as the input voltage is so low that either peak current or maximum duty cycle limitation is tripped. Vcc will then drop and stop IC activity as it falls below the UVLO threshold (8.7V typ.). The Vcc_OK signal is de-asserted as the Vcc voltage goes below a threshold Vccrestart located at about 5V. The HV generator can now restart but, if Vin < Vinstart, as shown in figure 36, HV_EN is de-asserted too and the HV generator is disabled. This prevents converter's re-start attempts and ensures monotonic output voltage decay at power-down. The low restart threshold Vccrestart ensures that, during short circuits, the restart attempts of the L6668 will have a very low repetition rate, as shown in the timing diagram of figure 37, and that the converter will work safely with extremely low power throughput. 4.2 Frequency Foldback Block and operation at medium/light load At heavy load, namely as the voltage on pin COMP (VCOMP) is higher than 3V, the device works at a fixed frequency like a standard current mode PWM controller. As the load is reduced, and the VCOMP voltage falls below 3V (approximately corresponding to 50% of the maximum load in a fully DCM system), the oscillator frequency can be made dependent on converter's load conditions - the lower the load, the lower the frequency and vice versa. Figure 38. Frequency foldback function: oscillator frequency is a function of COMP voltage fosc L6668 RSTBY 13 STBY 8 COMP Vref + RT RSTBY 16 3.0V OSCILLATOR RCT CT VCOMP 1.4 3.0 4.4 This is done by adding an external resistor RSTBY between pins RCT (#16) and STBY (#13), which activates the circuit shown in figure 38. When VCOMP is below 3 V (oscillator's peak voltage) the voltage on the STBY pin, which is internally connected to a current sink, tracks VCOMP and then some of the current that charges CT is diverted to ground through the STBY pin. In this way the rate of rise of the voltage across CT is slowed down and the oscillator frequency decreased, the lower VCOMP the lower the frequency. Instead, when VCOMP is greater than 3 V the STBY pin features high impedance and the oscillator frequency fosc will be determined by RT and CT. These components can be then calculated as it is usually done with this type of oscillator: 1.4 R T C T = --------f osc 14/23 L6668 Figure 39. Standby function: frequency shift vs. timing resistors (normalized quantities) 1 0.9 0.8 0.7 f min f osc 0.6 0.5 V(SKIPADJ) = 1.6V 0.4 0.3 0.2 0. 2.5V V(SKIPADJ) = 1.5V 2.2V 2V V(SKIPADJ) = 1.4V 1.8V 1 10 RSTBY RT The determination of RSTBY can be done assuming that the minimum switching frequency before burstmode operation takes place (fmin) is specified. This value will be above the audible range to ensure a noise-free operation. With the aid of the diagrams in figure 39, which show the relationship between the frequency shift obtained and the ratio of RSTBY to RT for different values of the burst-mode threshold, it is possible to determine RSTBY. Draw an horizontal line corresponding to the desired fmin/fosc ratio as long as it intercepts the characteristic corresponding to the voltage set at the pin SKIPADJ (#9). From there, draw a vertical line: on the horizontal axis it is possible to read the required RSTBY/RT ratio. Note that the characteristic for V(SKIPADJ)=1.4V corresponds to the burst-mode operation not used (see next section). Note also that, for a given V(SKIPADJ), there is both a lower limit to the RSTBY/RT ratio and a maximum frequency shift allowed. Not observing these limits will result in erratic behavior. In applications where the switching frequency needs not be tightly fixed for some specific reason there is no major drawback to this technique. In case this function is not desired, the STBY pin shall be left open. 4.3 Operation at no load or very light load When the PWM control voltage at pin COMP falls about 50 mV below a threshold externally programmable via pin 9 (SKIPADJ), the IC is disabled with the MOSFET kept in OFF state and its consumption reduced at a very low value to minimize Vcc capacitor discharge. The soft-start capacitor is not discharged. The control voltage now will increase as a result of the feedback reaction to the energy delivery stop, the threshold will be exceeded and the IC will restart switching again. In this way the converter will work in burst-mode with a constant peak current defined by the disable level applied at pin 9. A load decrease will then cause a frequency reduction, which can go down even to few hundred hertz, thus minimizing all frequency-related losses and maximizing efficiency. This kind of operation is noise-free provided the peak current, which is user-defined by the bias voltage at pin 9, is very low. The timing diagram of figure 40 illustrates this kind of operation along with the other ones, showing the most significant signals. 15/23 L6668 Figure 40. Load-dependent operating modes: timing diagram COMP 3.0V 50 mV hyster. V(SKIPADJ) t fosc t OUT Fix. Freq. Mode Burst-mode Fix. Freq. Mode t Frequency Foldback Mode The operating range of the voltage V(SKIPADJ) is practically limited upwards by the onset of audible noise: typically, with a voltage above 2-2.1V some noise can be heard under some line/load conditions. If, instead, V(SKIPADJ) is set below the low saturation value of the PWM control voltage (1.4V typ.) burstmode operation will never take place. Always bias the pin at some voltage, a floating pin will result in anomalous behavior. The SKIPADJ pin doubles its function: if the voltage is pulled below 0.8V the IC is disabled completely, except for the externally available reference voltage VREF, and its quiescent consumption reduced. The soft-start capacitor is discharged so that, when the voltage on the SKIPADJ pin is pulled above 0.8V, the chip is soft-started just like exiting from UVLO. This function is useful for some kind of remote ON/OFF control. The comparator referenced to 0.8V does not have hysteresis; hence make sure that the voltage on the pin does not linger on the threshold to prevent uncertain behavior. 4.4 PWM control Block The device is specific for secondary feedback. Typically, there is a TL431 at the secondary side and an optocoupler that transfers output voltage information to the PWM control at the primary side, crossing the isolation barrier. The PWM control input (pin #10, COMP) is driven directly by the phototransistor's collector (the emitter is grounded to GND) to modulate the duty cycle. 4.5 Current Comparator, PWM Latch and Hiccup-mode OCP The current comparator senses the voltage across the current sense resistor (Rs) on pin 12 (ISEN) and, by comparing it with the programming signal derived form the control voltage on pin 10 (COMP), determines the exact time when the external MOSFET is to be switched off. The PWM latch avoids spurious switching of the MOSFET, which might result from the noise generated ("double-pulse suppression"). 16/23 L6668 Figure 41. Hiccup-mode OCP: timing diagram Secondary diode is shorted here Vcc Vcc ON Vcc OFF re V CS OUT 1.5 V t t OCP latch t Vcc_OK t t A second comparator senses the voltage on the current sense input and shuts the IC down if the voltage at the pin exceeds 1.5 V. Such an anomalous condition is typically generated by either a short circuit of the secondary rectifier or a shorted secondary winding or a saturated flyback transformer. This condition is latched as long as the IC is supplied. When the IC is disabled, however, no energy is coming from the self-supply circuit, then the voltage on the Vcc capacitor will decay and cross the UVLO threshold after some time, which clears the latch. The internal start-up generator is still off, then the Vcc voltage still needs to go below its restart voltage before the Vcc capacitor is charged again and the IC restarted. Ultimately, either of the above mentioned failures will result in a low-frequency intermittent operation (Hiccup-mode operation), with very low stress on the power circuit. The timing diagram of figure 41 illustrates this operation. 4.6 Power Management The L6668 is specifically designed to minimize converter's losses under light or no-load conditions, and a special function has been provided to help the designer meet energy saving requirements even in powerfactor-corrected systems where a PFC pre-regulator precedes the DC-DC converter. Actually EMC regulations require compliance with low-frequency harmonic emission limits at nominal load, no limit is envisaged when the converter operates with a light load. Then the PFC pre-regulator can be turned off, thus saving the no-load consumption of this stage (0.5 to 1W). To do so, the device provides the PFC_STOP (#14) pin: it is an open collector output, normally low, that becomes open when the voltage VCOMP falls below 2.2V. This signal will be externally used for switching off the PFC controller and the pre-regulator as shown in figure 42. To prevent intermittent operation of the PFC stage, 0.5V hysteresis is provided: the PFC_STOP pin is re-asserted low (which will re-enable the PFC pre-regulator) when VCOMP exceeds 2.7 V. A capacitor (and a limiting resistor in the hundred ohms), shown in dotted lines, may be used if one wants to delay PFC turn-off When the L6668 is in UVLO (Vcc<8.7V) the pin is kept high so as to ensure that the PFC pre-regulator will start up only after the DC-DC converter governed by the L6668 is activated. 17/23 L6668 Figure 43 shows a timing diagram where the PFC_STOP function operation is illustrated under different operating conditions. Figure 42. How the L6668 can switch off a PFC controller at light load BC557 Vcc Vcc 16 10 kΩ L6668 14 8.2 V PFC_STOP PFC controller 2.2 kΩ Figure 43. Operation of PFC_STOP function Vcc Vcc ON Vcc OFF PFC_STOP t COMP t 2.7V 2.2V t OUT t PFC Gate Drive Start-up Full-load Light-load Full-load t Figure 44. Operation after DIS pin activation: timing diagram DIS 2.2V t Vcc VccON VccON -0.5 VccOFF HV generator is turned on Disable latch is reset here Vccrest OUT HV generator is disabled here t Input source is removed here Vin t VHVstart t 18/23 L6668 4.7 Disable function Latched OTP or OVP functions can be easily realized with the L6668: the IC is equipped with a comparator whose non-inverting input is externally available on pin #7 (DIS), and whose inverting input is internally referenced to 2.2V. As the voltage on the pin exceeds the threshold the IC is immediately shut down and its consumption reduced at a low value. The information is latched and it is necessary to let the voltage on the Vcc pin go below the UVLO threshold to reset the latch and restart the IC. To keep the latch supplied as long as the converter is connected to the input source, the HV generator is activated periodically so that Vcc oscillates between the start-up threshold VccON and VccON - 0.5V. It is then necessary to disconnect the converter from the input source to restart the IC. This operation is shown in the timing diagram of figure 44. Activating the HV generator in this way cuts its power dissipation approximately by three and keeps peak silicon temperature close to the average value. 4.8 Slope compensation A pin of the device (#15, S-COMP) provides a voltage ramp during MOSFET's ON-time which is a repetition of the oscillator sawtooth, buffered (0.8 mA min. capability) and level shifted down by one Vbe. This ramp is intended for implementing additive slope compensation on current sense. This is needed to avoid the sub-harmonic oscillation that arises in all peak-current-mode-controlled converters working in continuous conduction mode with a duty cycle close to or exceeding 50%. Figure 45. Slope compensation waveforms RCT OUT t S-COMP t t The compensation will be realized by connecting a programming resistor between this pin and the current sense input (pin 12, ISEN). The pin has to be connected to the sense resistor with another resistor to make a summing node on the pin. Since no ramp is delivered during MOSFET OFF-time (see figure 45), no external component other than the programming resistor is needed to ensure a clean operation at light loads. If slope compensation is not required the pin shall be left floating. 19/23 L6668 Figure 46. Typical Application: 80W, WRM flyback; Electrical Schematic F1 T2A250V NTC1 BD1 DF04M J1 88 to264 Vac T1 C1 100 µF 400 V R1 3 MΩ D1 1.5KE200 R2 3 MΩ D2 N1 R5 47kΩ R3 10Ω 18V/4.5A C9 100 nF C8A,B,C 680 µF 25 V N2 J2 STTA106 C3 100 nF R4 330 kΩ D4 STPS20150CT D3 1N4148 C2 25 V 47 µF GND C12 2.2 nF Y1 N3 R6 9.1 kΩ VREF S-COMP STBY 8 VCC DIS 15 7 HV 5 1 OUT Q1 R710kΩ STP9NK65 4 R14 4.3 kΩ 13 R8 4.03 kΩ ISEN L6668 12 R13A,B 0.56 1/2 16 R9 6.2 kΩ RCT 6 N.C. 11 9 SS SKIPADJ 10 3 COMP R17 8.06 kΩ R12 1kΩ OC1 PC817A R15 1.2 kΩ GND C10 100 nF TL431 R10 82.5 kΩ C4 100 nF C5 3.3 nF OC1 PC817A C6 56 nF R11 47 kΩ R16 47 kΩ 1 3 C7 2.2 nF 2 R18 1.3 kΩ Table 6. Light load measurements on the circuit of figure 46 Output power Test condition Input power Pout = 0.5 W Vin= 110 Vac 0.71 W Vin= 230 Vac 0.86 W Vin= 110 Vac 0.09 W Vin= 230 Vac 0.17 W Pout = 0 W 5 Package information In order to meet environmental requirements, STMicroelectronics offers this device in ECOPACK® package. This package has a Lead-free second level interconnect. The category of second level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an STMicroelectronics trademark. ECOPACK specifications are available at: www.st.com. 20/23 L6668 Figure 47. SO16 (Narrow) Mechanical Data & Package Dimensions mm inch DIM. MIN. TYP. A a1 MAX. MIN. TYP. 1.75 0.1 0.25 a2 MAX. 0.069 0.004 0.009 1.6 0.063 b 0.35 0.46 0.014 0.018 b1 0.19 0.25 0.007 0.010 45° (typ.) 10 0.386 6.2 0.228 C 0.5 c1 D(1) 9.8 E 5.8 0.020 0.394 0.244 e 1.27 0.050 e3 8.89 0.350 F(1) 3.8 4.0 0.150 0.157 G 4.60 5.30 0.181 0.208 L 0.4 1.27 0.150 0.050 M S OUTLINE AND MECHANICAL DATA 0.62 0.024 8 ° (max.) SO16 (Narrow) (1) "D" and "F" do not include mold flash or protrusions - Mold flash or protrusions shall not exceed 0.15mm (.006inc.) 0016020 D 21/23 L6668 6 Revision History Table 7. Revision History 22/23 Date Revision May 2005 1 Description of Changes First Issue. L6668 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. 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