L6562 TRANSITION-MODE PFC CONTROLLER 1 ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ FEATURES Figure 1. Packages REALISED IN BCD TECHNOLOGY TRANSITION-MODE CONTROL OF PFC PREREGULATORS PROPRIETARY MULTIPLIER DESIGN FOR MINIMUM THD OF AC INPUT CURRENT VERY PRECISE ADJUSTABLE OUTPUT OVERVOLTAGE PROTECTION ULTRA-LOW (≤70µA) START-UP CURRENT LOW (≤4 mA) QUIESCENT CURRENT EXTENDED IC SUPPLY VOLTAGE RANGE ON-CHIP FILTER ON CURRENT SENSE DISABLE FUNCTION 1% (@ Tj = 25 °C) INTERNAL REFERENCE VOLTAGE -600/+800mA TOTEM POLE GATE DRIVER WITH UVLO PULL-DOWN AND VOLTAGE CLAMP DIP-8/SO-8 PACKAGES Table 1. Order Codes PFC PRE-REGULATORS FOR: – IEC61000-3-2 COMPLIANT SMPS Part Number Package L6562N DIP-8 L6562D SO-8 L6562DTR Tape & Reel DESKTOP PC, MONITOR) UP TO 300W – HI-END AC-DC ADAPTER/CHARGER – ENTRY LEVEL SERVER & WEB SERVER 2 DESCRIPTION The L6562 is a current-mode PFC controller operating in Transition Mode (TM). Pin-to-pin compatible with the predecessor L6561, it offers improved performance. 1.1 APPLICATIONS ■ SO-8 DIP-8 (TV, Figure 2. Block Diagram COMP MULT 2 3 CS 4 1 INV - MULTIPLIER AND THD OPTIMIZER + 40K 2.5V VOLTAGE OVERVOLTAGE DETECTION REGULATOR 5pF + - VCC 8 VCC INTERNAL SUPPLY 7V R 25 V 15 V Q S R1 7 GD + R2 VREF2 DRIVER UVLO - Starter stop ZERO CURRENT DETECTOR + 2.1 V 1.6 V STARTER - DISABLE 6 GND June 2004 5 ZCD REV. 6 1/16 L6562 2 DESCRIPTION (continued) The highly linear multiplier includes a special circuit, able to reduce AC input current distortion, that allows wide-range-mains operation with an extremely low THD, even over a large load range. The output voltage is controlled by means of a voltage-mode error amplifier and a precise (1% @Tj = 25°C) internal voltage reference. The device features extremely low consumption (≤70 µA before start-up and <4 mA running) and includes a disable function suitable for IC remote ON/OFF, which makes it easier to comply with energy saving norms (Blue Angel, EnergyStar, Energy2000, etc.). An effective two-step OVP enables to safely handle overvoltages either occurring at start-up or resulting from load disconnection. The totem-pole output stage, capable of 600 mA source and 800 mA sink current, is suitable for big MOSFET or IGBT drive which, combined with the other features, makes the device an excellent low-cost solution for EN61000-3-2 compliant SMPS's up to 300W. Table 2. Absolute Maximum Ratings Symbol Pin VCC 8 IGD 7 --- 1 to 4 IZCD 5 Ptot Tj Tstg Parameter Value Unit IC Supply voltage (Icc = 20 mA) self-limited V Output Totem Pole Peak Current ±0.8 A -0.3 to 8 V -50 (source) 10 (sink) mA 1 0.65 W Junction Temperature Operating range -40 to 150 °C Storage Temperature -55 to 150 °C Analog Inputs & Outputs Zero Current Detector Max. Current Power Dissipation @Tamb = 50°C (DIP-8) (SO-8) Figure 3. Pin Connection (Top view) INV 1 8 Vcc COMP 2 7 GD MULT 3 6 GND CS 4 5 ZCD Table 3. Thermal Data Symbol Rth j-amb 2/16 Parameter Max. Thermal Resistance, Junction-to-ambient SO8 Minidip Unit 150 100 °C/W L6562 Table 4. Pin Description N° Pin Function 1 INV Inverting input of the error amplifier. The information on the output voltage of the PFC preregulator is fed into the pin through a resistor divider. 2 COMP Output of the error amplifier. A compensation network is placed between this pin and INV (pin #1) to achieve stability of the voltage control loop and ensure high power factor and low THD. 3 MULT Main input to the multiplier. This pin is connected to the rectified mains voltage via a resistor divider and provides the sinusoidal reference to the current loop. 4 CS Input to the PWM comparator. The current flowing in the MOSFET is sensed through a resistor, the resulting voltage is applied to this pin and compared with an internal sinusoidal-shaped reference, generated by the multiplier, to determine MOSFET’s turn-off. 5 ZCD Boost inductor’s demagnetization sensing input for transition-mode operation. A negative-going edge triggers MOSFET’s turn-on. 6 GND Ground. Current return for both the signal part of the IC and the gate driver. 7 GD Gate driver output. The totem pole output stage is able to drive power MOSFET’s and IGBT’s with a peak current of 600 mA source and 800 mA sink. The high-level voltage of this pin is clamped at about 12V to avoid excessive gate voltages in case the pin is supplied with a high Vcc. 8 Vcc Supply Voltage of both the signal part of the IC and the gate driver. The supply voltage upper limit is extended to 22V min. to provide more headroom for supply voltage changes. Table 5. Electrical Characteristics (Tj = -25 to 125°C, VCC = 12, CO = 1 nF; unless otherwise specified) Symbol Parameter Test Condition Min. Typ. Max. Unit 22 V SUPPLY VOLTAGE VCC Operating range After turn-on VCCon Turn-on threshold (1) 11 12 13 V VCCOff Turn-off threshold (1) 8.7 9.5 10.3 V 2.8 V 28 V Hys VZ 10.3 Hysteresis Zener Voltage 2.2 ICC = 20 mA 22 25 SUPPLY CURRENT Istart-up Iq ICC Iq Start-up Current Before turn-on, VCC =11V 40 70 µA Quiescent Current After turn-on 2.5 3.75 mA Operating Supply Current @ 70 kHz 3.5 Quiescent Current During OVP (either static or dynamic) or VZCD =150 mV 5 mA 2.2 mA -1 µA MULTIPLIER INPUT IMULT Input Bias Current VMULT Linear Operation Range ∆V CS --------------------∆V MULT K VVFF = 0 to 4 V 0 to 3 V Output Max. Slope VMULT = 0 to 0.5V VCOMP = Upper clamp 1.65 1.9 Gain (2) VMULT = 1 V, VCOMP = 4 V 0.5 0.6 0.7 1/V 2.465 2.5 2.535 V V/V ERROR AMPLIFIER VINV IINV Voltage Feedback Input Threshold Tj = 25 °C 10.3 V < Vcc < 22 V Line Regulation Vcc = 10.3 V to 22V Input Bias Current VINV = 0 to 3 V (1) 2.44 2.56 2 5 mV -1 µA 3/16 L6562 Table 5. Electrical Characteristics (continued) (Tj = -25 to 125°C, VCC = 12, CO = 1 nF; unless otherwise specified) Symbol Parameter Gv Voltage Gain GB Gain-Bandwidth Product ICOMP Source Current VCOMP Lower Clamp Voltage Test Condition Open loop Min. Typ. Max. 60 80 dB 1 MHz -5 Unit VCOMP = 4V, VINV = 2.4 V -2 -3.5 mA Sink Current VCOMP = 4V, VINV = 2.6 V 2.5 4.5 Upper Clamp Voltage ISOURCE = 0.5 mA 5.3 5.7 6 V ISINK = 0.5 mA (1) 2.1 2.25 2.4 V -1 µA 200 350 ns 1.7 1.8 V mA CURRENT SENSE COMPARATOR ICS td(H-L) Input Bias Current Delay to Output VCS clamp Current sense reference clamp VCSoffset VCS = 0 Current sense offset VCOMP = Upper clamp 1.6 VMULT = 0 30 VMULT = 2.5V 5 mV ZERO CURRENT DETECTOR VZCDH Upper Clamp Voltage IZCD = 2.5 mA 5.0 5.7 6.5 V 0.3 0.65 1 V VZCDL Lower Clamp Voltage IZCD = -2.5 mA VZCDA Arming Voltage (positive-going edge) (3) 2.1 V VZCDT Triggering Voltage (negative-going edge) (3) 1.6 V IZCDb Input Bias Current VZCD = 1 to 4.5 V 2 µA IZCDsrc Source Current Capability -2.5 IZCDsnk Sink Current Capability 2.5 VZCDdis Disable threshold 150 VZCDen Restart threshold IZCDres Restart Current after Disable 30 75 Start Timer period 75 130 300 µs 35 40 45 µA -5.5 mA mA 200 250 mV 350 mV µA STARTER tSTART OUTPUT OVERVOLTAGE IOVP Dynamic OVP triggering current Hys Hysteresis (3) Static OVP threshold (1) 30 2.1 µA 2.25 2.4 V IGDsource = 20 mA 2 2.6 IGDsource = 200 mA 2.5 3 V IGDsink = 200 mA 0.9 1.9 V GATE DRIVER VOH Dropout Voltage VOL tf Voltage Fall Time 30 70 ns tr Voltage Rise Time 40 80 ns 12 15 1.1 V V VOclamp (1) (2) (3) 4/16 Output clamp voltage IGDsource = 5mA; Vcc = 20V UVLO saturation VCC = 0 to VCCon, Isink=10mA All parameters are in tracking The multiplier output is given by: V cs = K ⋅ VMU LT ⋅ ( V COM P – 2.5 ) Parameters guaranteed by design, functionality tested in production. 10 L6562 3 TYPICAL ELECTRICAL CHARACTERISTICS Figure 4. Supply current vs. Supply voltage Figure 6. IC consumption vs. Tj Icc 10 [mA] 5 ICC (mA) Operating Quiescent 10 2 5 1 1 0.5 0.5 0.1 0.2 0.05 Co = 1nF f = 70 kHz Tj = 25°C 0.01 0.005 5 10 15 20 Vcc = 12 V Co = 1 nF f = 70 kHz 0.1 Before start-up 0.05 0 0 Disabled or during OVP 25 0.02 -50 0 Vcc(V) 100 150 Tj (°C) Figure 7. Vcc Zener voltage vs. Tj Figure 5. Start-up & UVLO vs. Tj VccZ 28 (V) 12.5 VCC-ON (V) 50 12 27 11.5 26 11 25 10.5 24 10 23 VCC-OFF 9.5 (V) 9 -50 0 50 Tj (°C) 100 150 22 -50 0 50 100 150 Tj (°C) 5/16 L6562 Figure 11. Delay-to-output vs. Tj Figure 8. Feedback reference vs. Tj VREF 2.6 (V) tD(H-L) 500 (ns) Vcc = 12 V Vcc = 12 V 400 2.55 300 2.5 200 2.45 100 2.4 -50 0 50 100 0 -50 150 0 Figure 9. OVP current vs. Tj 150 Figure 12. Multiplier characteristic VCOMP(pin 2) (V) VCS (pin 4) (V) upper voltage 41 clamp Vcc = 12 V 1.6 40.5 3.5 5.0 1.4 4 .5 (µA) 100 Tj (°C) Tj (°C) IOVP 50 1.2 4.0 3.2 1.0 40 0.8 3.0 0.6 39.5 0.4 2.8 0.2 2.6 39 -50 0 50 100 150 0 0 Tj (°C) 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 VMULT(pin 3) (V) Figure 13. Multiplier gain vs. Tj Figure 10. E/A output clamp levels vs. Tj K Vpin2 (V) 6 1 Vcc = 12 V VCOMP =4 V VMULT =1V 0.8 Upper clamp Vcc = 12 V 5 0.6 4 0.4 3 0.2 Lower clamp 2 -50 0 50 Tj (°C) 6/16 100 150 0 -50 0 50 Tj (°C) 100 150 L6562 Figure 17. ZCD source capability vs. Tj Figure 14. Vcs clamp vs. Tj VCSx 2 (V) IZCDsrc 0 (mA) Vcc = 12 V VZCD = lower clamp 1.8 -2 1.6 -4 1.4 1.2 1 -50 Vcc = 12 V VCOMP= Upper clamp 0 -6 50 100 -8 -50 150 0 50 150 Tj (°C) Tj (°C) Figure 15. Start-up timer vs. Tj Tstart 150 (µs) 100 Figure 18. Gate-drive output low saturation Vpin7 [V] 4 Vcc = 12 V Tj = 25 °C Vcc = 11 V SINK 140 3 130 2 120 1 110 0 100 -50 0 50 100 150 0 200 800 1,000 Figure 19. Gate-drive output high saturation Figure 16. ZCD clamp levels vs. Tj (V) 600 IGD[mA] Tj (°C) VZCD 400 Vpin7 [V] 7 -1.5 Upper clamp 6 Tj = 25 °C Vcc = 11 V SOURCE -2 Vcc - 2.0 Vcc = 12 V I ZCD = ±2.5 mA 5 Vcc - -2.5 2.5 4 -3 Vcc - 3.0 3 Vcc - -3.5 3.5 2 -4 Vcc - 4.0 1 0 -50 Lower clamp -4.5 0 50 Tj (°C) 100 150 0 100 200 300 400 500 600 700 IGD[mA] 7/16 L6562 Figure 20. Gate-drive clamp vs. Tj Figure 21. UVLO saturation vs. Tj Vpin7 clamp 15 (V) Vpin7 (V) 1.1 Vcc = 0 V Vcc = 20 V 1 14 0.9 13 0.8 12 0.7 11 10 -50 0.6 0 50 100 150 0.5 -50 50 100 150 Tj (°C) Tj (°C) 4 0 APPLICATION INFORMATION 4.1 Overvoltage protection Under steady-state conditions, the voltage control loop keeps the output voltage Vo of a PFC pre-regulator close to its nominal value, set by the resistors R1 and R2 of the output divider. Neglecting ripple components, the current through R1, IR1, equals that through R2, IR2. Considering that the non-inverting input of the error amplifier is internally referenced at 2.5V, also the voltage at pin INV will be 2.5V, then: 2.5 Vo – 2.5 I R2 = -------- = I R1 = ---------------------- . R2 R1 If the output voltage experiences an abrupt change ∆Vo > 0 due to a load drop, the voltage at pin INV will be kept at 2.5V by the local feedback of the error amplifier, a network connected between pins INV and COMP that introduces a long time constant to achieve high PF (this is why ∆Vo can be large). As a result, the current through R2 will remain equal to 2.5/R2 but that through R1 will become: Vo – 2.5 + ∆Vo I' R1 = ---------------------------------------- . R1 The difference current ∆IR1=I'R1-IR2=I'R1-IR1=∆Vo/R1 will flow through the compensation network and enter the error amplifier output (pin COMP). This current is monitored inside the L6562 and if it reaches about 37 µA the output voltage of the multiplier is forced to decrease, thus smoothly reducing the energy delivered to the output. As the current exceeds 40 µA, the OVP is triggered (Dynamic OVP): the gate-drive is forced low to switch off the external power transistor and the IC put in an idle state. This condition is maintained until the current falls below approximately 10 µA, which re-enables the internal starter and allows switching to restart. The output ∆Vo that is able to trigger the Dynamic OVP function is then: ∆Vo = R1 ⋅ 40 ⋅ 10 –6 . An important advantage of this technique is that the OV level can be set independently of the regulated output voltage: the latter depends on the ratio of R1 to R2, the former on the individual value of R1. Another advantage is the precision: the tolerance of the detection current is 12%, that is 12% tolerance on ∆Vo. Since ∆Vo << Vo, the tolerance on the absolute value will be proportionally reduced. Example: Vo = 400 V, ∆Vo = 40 V. Then: R1=40V/40µA=1MΩ; R2=1MΩ·2.5/(400-2.5)=6.289kΩ. The tolerance on the OVP level due to the L6562 will be 40·0.12=4.8V, that is 1.2% of the regulated value. 8/16 L6562 When the load of a PFC pre-regulator is very low, the output voltage tends to stay steadily above the nominal value, which cannot be handled by the Dynamic OVP. If this occurs, however, the error amplifier output will saturate low; hence, when this is detected, the external power transistor is switched off and the IC put in an idle state (Static OVP). Normal operation is resumed as the error amplifier goes back into its linear region. As a result, the L6562 will work in burst-mode, with a repetition rate that can be very low. When either OVP is activated the quiescent consumption of the IC is reduced to minimize the discharge of the Vcc capacitor and increase the hold-up capability of the IC supply system. 4.2 THD optimizer circuit The L6562 is equipped with a special circuit that reduces the conduction dead-angle occurring to the AC input current near the zero-crossings of the line voltage (crossover distortion). In this way the THD (Total Harmonic Distortion) of the current is considerably reduced. A major cause of this distortion is the inability of the system to transfer energy effectively when the instantaneous line voltage is very low. This effect is magnified by the high-frequency filter capacitor placed after the bridge rectifier, which retains some residual voltage that causes the diodes of the bridge rectifier to be reverse-biased and the input current flow to temporarily stop. Figure 22. THD optimization: standard TM PFC controller (left side) and L6562 (right side) Input current Input current Rectified mains voltage Imains Input current Rectified mains voltage Imains Input current Vdrain MOSFET's drain voltage Vdrain MOSFET's drain voltage To overcome this issue the circuit embedded in the L6562 forces the PFC pre-regulator to process more energy near the line voltage zero-crossings as compared to that commanded by the control loop. This will result in both minimizing the time interval where energy transfer is lacking and fully discharging the highfrequency filter capacitor after the bridge. The effect of the circuit is shown in figure 23, where the key waveforms of a standard TM PFC controller are compared to those of the L6562. Essentially, the circuit artificially increases the ON-time of the power switch with a positive offset added to 9/16 L6562 the output of the multiplier in the proximity of the line voltage zero-crossings. This offset is reduced as the instantaneous line voltage increases, so that it becomes negligible as the line voltage moves toward the top of the sinusoid. To maximally benefit from the THD optimizer circuit, the high-frequency filter capacitor after the bridge rectifier should be minimized, compatibly with EMI filtering needs. A large capacitance, in fact, introduces a conduction dead-angle of the AC input current in itself - even with an ideal energy transfer by the PFC preregulator - thus making the action of the optimizer circuit little effective. Figure 23. Typical application circuit (250W, Wide-range mains) D3 1N5406 R4 R5 180 kΩ 180 kΩ BRIDGE FUSE 5A/250V Vac (85V to 265V) STBR606 C1 1 µF 400V C5 12 nF D1 STTH5L06 R14 100 Ω D2 1N5248B R1 1.5 MΩ + T D8 1N4150 NTC 2.5 Ω R50 10 kΩ R6 68 kΩ R11 750 kΩ Vo=400V Po=250W R12 750 kΩ C3 2.2 µF C23 680 nF R2 1.5 MΩ - 8 5 3 L6562 2 1 R7 10 Ω 7 C6 100 µF 450V MOS STP12NM50 7 °C/W heat sink 4 6 C2 10nF R3 22 kΩ C29 22 µF 25V C4 100 nF R9 0.33Ω 1W R10 0.33Ω 1W R13 9.53 kΩ - Boost Inductor Spec: EB0057-C (COILCRAFT) Figure 24. Demo board (EVAL6562-80W, Wide-range mains): Electrical schematic R4 R5 180 kΩ 180 kΩ BRIDGE Vac (85V to 265V) + DF06M C1 0.47 µF 400V D1 STTH1L06 R14 100 Ω NTC 2.5 Ω R50 12 kΩ R6 68 kΩ R11 750 kΩ Vo=400V Po=80W R12 750 kΩ C3 680 nF C23 330 nF R2 750 kΩ - 8 5 3 L6562 2 6 C2 10nF R3 10 kΩ C29 22 µF 25V Boost Inductor Spec (ITACOIL E2543/E) E25x13x7 core, 3C85 ferrite 1.5 mm gap for 0.7 mH primary inductance Primary: 105 turns 20x0.1 mm Secondary: 11 turns 0.1 mm 10/16 C5 12 nF D2 1N5248B R1 750 kΩ FUSE 4A/250V T D8 1N4150 C4 100 nF 1 R7 33 Ω 7 C6 47 µF 450V MOS STP8NM50 4 R9 0.82Ω 0.6 W R10 0.82Ω 0.6 W R13 9.53 kΩ - L6562 Figure 25. EVAL6562-80W: PCB and component layout (Top view, real size: 57 x 108 mm) Table 6. EVAL6562N: Evaluation results at full load Vin (VAC) Pin (W) Vo (VDC) ∆Vo(Vpk-pk) Po (W) η (%) PF THD (%) 85 86.4 394.79 12.8 80.16 92.8 0.998 3.6 110 84.6 394.86 12.8 80.20 94.8 0.996 4.2 135 83.8 394.86 12.8 80.20 95.7 0.991 4.9 175 83.2 394.87 15.5 80.20 96.4 0.981 6.5 220 82.9 394.87 15.7 80.20 96.7 0.956 7.8 265 82.7 394.87 15.9 80.20 97.0 0.915 9.2 Note: measurements done with the line filter shown in figure 23 Table 7. EVAL6562N: Evaluation results at half load Vin (VAC) Pin (W) Vo (VDC) ∆Vo(Vpk-pk) Po (W) η (%) PF THD (%) 85 42.8 394.86 6.6 40.20 93.9 0.994 5.5 110 42.5 394.90 6.6 40.20 94.6 0.985 6.2 135 42.5 394.91 6.7 40.20 94.6 0.967 7.1 175 42.5 394.93 8.0 40.19 94.6 0.939 8.3 220 42.6 394.94 8.2 40.19 94.3 0.869 9.8 265 42.6 394.94 8.3 40.19 94.3 0.776 11.4 Note: measurements done with the line filter shown in figure 23 11/16 L6562 Table 8. EVAL6562N: No-load measurements (*) Vin (VAC) Pin (W) Vo (VDC) ∆Vo(Vpk-pk) Po (W) 85 0.4 396.77 0.45 0 110 0.3 396.82 0.55 0 135 0.3 396.83 0.60 0 175 (*) 0.4 396.90 1.00 0 220 (*) 0.4 396.95 1.40 0 265 (*) 0.5 396.98 1.65 0 Vcc = 12V supplied externally Figure 26. Line filter (not tested for EMI compliance) used for EVAL6562N evaluation to the AC source B81133 470 nF, X2 EPCOS B81133 680 nF, X2 EPCOS B82732 47 mH, 1.3A EPCOS 12/16 to EVAL6562N L6562 Figure 27. DIP-8 Mechanical Data & Package Dimensions mm inch DIM. MIN. A TYP. MAX. MIN. 3.32 TYP. MAX. 0.131 a1 0.51 B 1.15 1.65 0.045 0.065 b 0.356 0.55 0.014 0.022 b1 0.204 0.304 0.008 0.012 0.020 D E 10.92 7.95 9.75 0.430 0.313 0.384 e 2.54 0.100 e3 7.62 0.300 e4 7.62 0.300 F 6.6 0.260 I 5.08 0.200 L Z 3.18 OUTLINE AND MECHANICAL DATA 3.81 1.52 0.125 0.150 DIP-8 0.060 13/16 L6562 Figure 28. SO-8 Mechanical Data & Package Dimensions mm inch DIM. MIN. TYP. MAX. MIN. TYP. MAX. A 1.35 1.75 0.053 0.069 A1 0.10 0.25 0.004 0.010 A2 1.10 1.65 0.043 0.065 B 0.33 0.51 0.013 0.020 C 0.19 0.25 0.007 0.010 D (1) 4.80 5.00 0.189 0.197 E 3.80 4.00 0.15 0.157 e 1.27 0.050 H 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.020 L 0.40 1.27 0.016 0.050 k ddd OUTLINE AND MECHANICAL DATA 0˚ (min.), 8˚ (max.) 0.10 0.004 Note: (1) Dimensions D does not include mold flash, protrusions or gate burrs. Mold flash, potrusions or gate burrs shall not exceed 0.15mm (.006inch) in total (both side). SO-8 0016023 C 14/16 L6562 Table 9. Revision History Date Revision Description of Changes January 2004 5 First Issue June 2004 6 Modified the Style-look in compliance with the “Corporate Technical Publications Design Guide”. Changed input of the power amplifier connected to Multiplier (Fig. 2). 15/16 L6562 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. 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