L6591 PWM controller for ZVS half-bridge Features ■ Complementary PWM control for soft-switched half-bridge with programmable dead-time ■ Up to 500 kHz operating frequency ■ On-board high-voltage start-up ■ Advanced light load management ■ Adaptive UVLO ■ Pulse-by-pulse OCP ■ OLP (latched or autorestart) ■ Transformer saturation detection ■ Interface with PFC controller ■ Latched disable input ■ Input for power-on sequencing or brownout protection ■ High power AC-DC adapter/charger ■ Desktop PC, entry-level server Programmable soft-start ■ Telecom SMPS ■ SO16 narrow SO-16 ■ 600 V-rail compatible high-side gate driver with integrated bootstrap diode and high dV/dt immunity ■ SO16N package Applications ■ 4 % precision external reference Figure 1. Typical application circuit HV V CC 9 16 5 CLK OSC TIMING 25 V Vre f HV ge nerator ON/O FFa nd a daptive UV LOmanag ement VREG VREF Vcc_OK 2 Low UVLO R DIS + S Sync hronou s bo otstra p diode Q - 4.5V DIS 15 BOOT - HICCUP BLANKI NG S Q P WM _CT L + ISEN R 3 + PWM Vc c_O K - DIS S HUT DO WN R PFC_STOP Q S 8 OCP2 LI NE_ OK OCP2 DI S VREG BURST- M ODE CTRL Ilimre f 0 .8 V max. 1.5V - 1 LINE LI NE_OK 1 5µA HVG 13 FGND V CC 10 LV G 1.7 5V - + 14 L EVEL SHIFTER 0.3 2mA + + OCP - Dead time adjustment & logic 1.5V L ow UV LO 11 GND 3R SOFT-START + R 2.0 V 4 7 SS June 2008 6 COMP Rev 1 1/32 www.st.com 32 Contents L6591 Contents 1 Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 2.1 Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.1 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.1 High-voltage start-up generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.2 Operation at no load or very light load . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.3 PWM control block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.4 PWM comparator, PWM latch and hiccup-mode OCP . . . . . . . . . . . . . . . 17 5.5 Latched shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.6 Oscillator and dead-time programming . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.7 Adaptive UVLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.8 Line sensing function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.9 Soft-start and delayed latched shutdown upon overcurrent . . . . . . . . . . . 23 6 Summary of L6591 power management functions . . . . . . . . . . . . . . . 25 7 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2/32 L6591 1 Device description Device description The L6591 is a double-ended PWM controller specific for the soft-switched half-bridge topology. It provides complementary PWM control, where the high-side switch is driven ON for a duty cycle D and the low-side switch for a duty cycle 1-D, with D 50 %. An externally programmable dead-time inserted between the turn-off of one switch and the turn-on of the other one guarantees soft-switching and enables high-frequency operation. To drive the high-side switch with the bootstrap approach, the IC incorporates a high-voltage floating structure able to withstand more than 600 V with a synchronous-driven high-voltage DMOS that replaces the external fast-recovery bootstrap diode. The IC enables the designer to set the operating frequency of the converter by means of an externally programmable oscillator: the maximum duty cycle is digitally clipped at 50 % by a T-flip-flop, so that the operating frequency will be half that of the oscillator. At very light load the IC enters a controlled burst-mode operation that, along with the built-in non-dissipative high-voltage start-up circuit and the low quiescent current, helps keep low the consumption from the mains and be compliant with energy saving recommendations. To allow compliance with these standards in two-stage power-factor-corrected systems as well, an interface with the PFC controller is provided that enables to switch off the preregulator between one burst and the following one. An innovative adaptive UVLO helps minimize the issues related to the fluctuations of the self-supply voltage with the output load, due to transformer's parasitic. IC's protection functions include: not-latched input undervoltage (brownout), a first-level OCP with delayed shutdown able to protect the system during overload and short circuit conditions (either auto-restart or latch mode can be selected) and a second-level OCP that latches off the IC when the transformer saturates or one of the secondary diodes fails short. Finally, a latched disable function allows easy implementation of OTP or OVP. Programmable soft-start and digital leading-edge blanking on current sense input pin complete the equipment of the IC. Figure 2. Typical system block diagram PFC PRE-REGULATOR ZVS HALF-BRIDGE Voutd c Vinac PW M is turned off in case of PFC's anomalous oper ation, for safety L6561/2 or L6563 L6591 PFC can be turn ed off at light load to ease compliance with energy saving r egulatio ns. 3/32 Pin settings L6591 2 Pin settings 2.1 Connection Figure 3. Pin connection (top view) 2.2 1 16 HVSTART DIS 2 15 BOOT ISEN 3 14 HVG SS 4 13 FGND OSC 5 12 N.C. VREF 6 11 GND COMP 7 10 LVG PFC_STOP 8 9 Vcc Functions Table 1. Pin N. 1 2 4/32 LINE Pin functions Name Function LINE Line sensing input. The pin is to be connected to the high-voltage input bus with a resistor divider. A voltage below 1.25 V shuts down the IC, lowers its consumption and discharges the soft-start capacitor. IC’s operation is reenabled as the voltage exceeds 1.25 V. The comparator is provided with current hysteresis: an internal 15 µA current generator is ON as long as the voltage applied at the pin is below 1.25 V and is OFF if this value is exceeded. Bypass the pin with a capacitor to GND (#11) to reduce noise pick-up. The pin is intended for either power-on sequencing in systems with PFC, or brownout protection. Tie to Vcc (#9) with a 220 to 330 kW resistor if the function is not used. DIS Latched device shutdown. Internally the pin connects a comparator that, when the voltage on the pin exceeds 4.5 V, shuts the IC down and brings its consumption to a value barely higher than before start-up. The information is latched and it is necessary to recycle the input power to restart the IC: the latch is removed as the voltage on the Vcc pin (#9) goes below the UVLO threshold. Connect the pin to GND (#11) if the function is not used. L6591 Pin settings Table 1. Pin N. 3 4 5 6 7 8 Pin functions (continued) Name Function ISEN Current sense (PWM comparator) input. The voltage on this pin is internally compared with an internal reference derived from the voltage on pin COMP and when they are equal the high-side gate drive output (previously asserted high by the clock signal generated by the oscillator) is driven low to turn off the upper power MOSFET; the lower MOSFET is turned on after a delay programmed by the timing capacitor at pin OSC (#5). The pin is equipped with 200 ns blanking time for improved noise immunity. A second comparator referenced at 0.8 V turns off the upper MOSFET if the voltage at the pin exceeds the threshold, overriding the PWM comparator (pulse-bypulse OCP). A third comparison level located at 1.5 V shuts the device down and brings its consumption almost to a “before start-up” level (hiccupmode OCP) to prevent uncontrolled current rise. A logic circuit improves sensitivity to temporary disturbances. SS Soft-start. An internal 20 µA generator charges an external capacitor connected between the pin and GND (#11) generating a voltage ramp. During the ramp, the internal reference for pulse-by-pulse OCP (see pin #3, ISEN) rises linearly starting from zero to its final value, thus causing the duty cycle of the upper MOSFET to rise starting from zero as well, and all the functions monitoring pin COMP (#7) are disabled. The same capacitor is used to delay IC’s shutdown (latch-off or auto-restart mode selectable) after detecting an overcurrent condition. The SS capacitor is quickly discharged as the chip goes into UVLO. OSC Oscillator pin. A resistor to VREF (#6) and a capacitor from the pin to GND (#11) define the oscillator frequency. The maximum duty cycle is limited below 50 % by an internal T-flip-flop. As a result, the switching frequency will be half that of the oscillator. The capacitor value defines the dead-time separating the conduction state of either MOSFET. This capacitor should not be lower than 220 pF. VREF Voltage reference. An internal generator furnishes an accurate voltage reference (5 V±4 %, all inclusive) that can be used to supply up to 5 mA to an external circuit. A small film capacitor (0.1 µF typ.), connected between this pin and GND (#11) is recommended to ensure the stability of the generator and to prevent noise from affecting the reference. COMP Control input for PWM regulation. The pin is to be driven by the phototransistor (emitter-grounded) of an octocoupler to modulate the voltage by modulating the current sunk from (sourced by) the pin (0.4 mA typ.). It is recommended to place a small filter capacitor between the pin and GND (#11), as close to the IC as possible to reduce switching noise pick up, to set a pole in the output-to-control transfer function. A voltage lower than 1.75 V shuts down the IC and reduces its current consumption. The chip restarts as the voltage exceeds 1.8 V. This function realizes burstmode operation at light load. Open-drain ON/OFF control of PFC controller. This pin is intended for temporarily stopping the PFC controller at light load in systems comprising a PFC pre-regulator, during burst-mode operation (see pin COMP, #7). The pin, normally open, goes low if the voltage on COMP is lower than 1.75 V PFC_STOP and opens when the voltage on pin COMP exceeds 1.8V. Whenever the IC is shut down (SS > 5 V, DIS>4.5, ISEN >1.5 V) the pin is low as well, provided the supply voltage of the IC is above the restart threshold (typ. 5 V). It is open during UVLO. Leave the pin open if not used 5/32 Pin settings L6591 Table 1. Pin N. Name Function 9 Vcc Supply voltage of both the signal part of the IC and the low-side gate driver. The internal high voltage generator charges an electrolytic capacitor connected between this pin and GND (#11) as long as the voltage on the pin is below the start-up threshold of the IC, after that it is disabled and the chip turns on. Sometimes a small bypass capacitor (0.1 µF typ.) to GND might be useful to get a clean bias voltage for the signal part of the IC. The minimum operating voltage (UVLO) is adapted to the loading conditions of the converter to ease burst-mode operation, during which the available supply voltage for the IC drops. 10 LVG Low-side gate-drive output. The driver is capable of 0.3 A min. source and 0.8A min. sink peak current to drive the gate of the lower MOSFET of the half-bridge leg. The pin is actively pulled to GND (#11) during UVLO. 11 GND Chip ground. Current return for both the low-side gate-drive current and the bias current of the IC. All of the ground connections of the bias components should be tied to a track going to this pin and kept separate from any pulsed current return. 12 N.C. High-voltage spacer. The pin is not connected internally to isolate the group of high-voltage pins and comply with safety regulations (creepage distance) on the PCB. 13 FGND High-side gate-drive floating ground. Current return for the high-side gatedrive current. Layout carefully the connection of this pin to avoid too large spikes below ground. HVG High-side floating gate-drive output. The driver is capable of 0.3 A min. source and 0.8 A min. sink peak current to drive the gate of the upper MOSFET of the half-bridge leg. A pull-down resistor between this pin and pin 13 (FGND) makes sure that the gate is never floating during UVLO. BOOT High-side gate-drive floating supply voltage. The bootstrap capacitor connected between this pin and pin 13 (FGND) is fed by an internal synchronous bootstrap diode driven in-phase with the low-side gate-drive. This patented structure can replace the normally used external diode. HVSTART High-voltage start-up. The pin is to be connected directly to the rectified mains voltage. A 0.8 mA internal current source charges the capacitor connected between pin Vcc (#9) and GND (#11) until the voltage on the Vcc pin reaches the start-up threshold. Normally it is re-enabled when the voltage on the Vcc pin falls below 5 V, except under latched shutdown conditions, in which case it is re-enabled as the Vcc voltage falls 1 V below the start-up threshold to keep the latch active. 14 15 16 6/32 Pin functions (continued) L6591 Electrical data 3 Electrical data 3.1 Maximum ratings Table 2. Absolute maximum ratings Symbol Pin VHVSTART 16 IHVS Value Unit Voltage range (referred to ground) -0.3 to 700 V 16 Input current Self-limited A VBOOT 15 Floating supply voltage -1 to 618 V VFGND 13 Floating ground voltage -3 to VBOOT -18 V dVFGND/dt 13 Floating ground slew rate 50 V/ns VCC 9 IC supply voltage (Icc = 20 mA) Self-limited V IHVG, ILVG 10, 14 Gate-drives peak current Self-limited A IPFC_STOP 8 Max. sink current (VPFC_STOP = 25 V) Self-limited A VLINEmax 1 Maximum pin voltage (Ipin ≤ 1 mA) Self-limited V --- 2 to 7 -0.3 to 7 V ISEN 3 -3 to 7 V 0.75 W Junction temperature operating range -40 to 150 °C Storage temperature -55 to 150 °C Analog inputs and outputs Current sense input Power dissipation @ TA = 50 °C PTOT TJ TSTG 3.2 Parameter Thermal data Table 3. Symbol RthJA Thermal data Parameter Thermal resistance junction to ambient (1) Value Unit 120 °C/W 1. Value depending on PCB copper area and thickness. 7/32 Electrical characteristics 4 L6591 Electrical characteristics Table 4. Electrical characteristics (TJ = 0 to 105 °C, Vcc = 15 V, VBOOT = 12 V, CHVG = CLVG = 1 nF; RT = 22 kΩ, CT = 330 pF; unless otherwise specified) Symbol Parameter Test condition Min Typ Max Unit IC supply voltage Vcc VccOn VccOff Operating range after turn-on VCOMP > VCOMPL 11.3 22 VCOMP = VCOMPL 9.2 22 Turn-on threshold (1) 13 14 15 VCOMPL 9.7 10.5 11.3 = VCOMPL 8.2 8.7 9.2 Turn-off threshold (1) V COMP > (1) V COMP V V V Hys Hysteresis VCOMP > VCOMPL 3.0 3.5 V VZ Vcc clamp voltage Icc = 15 mA 22 25 28 V Supply current Start-up current Before turn-on, Vcc = 12.5 V 190 250 µA Iq Quiescent current After turn-on 2.8 3.5 mA Icc Operating supply current 5.3 8 mA VDIS > 4.5 V, VISEN > 1.5 V 0.35 mA VCOMP = 1.64 V 2.2 mA VLINE < 1.44 V 0.35 mA 17 V 800 µA 10 µA Istart-up Iqdis Shutdown quiescent current High-side floating gate-drive supply VBOOT Operating supply voltage Referred to FGND pin IqBOOT Quiescent current VFGND = 0 High-voltage leakage VFGND = VBOOT = VHVG = 600 V Synchronous bootstrap diode on-resistance VLVG = HIGH ILK RDS(on) 500 Ω 125 High-voltage start-up generator VHV Breakdown voltage IHV < 100 µA 700 Start voltage IVcc < 100 µA 60 75 90 V Icharge Vcc charge current VHV > VHvstart, Vcc> 3V 0.55 0.75 1 mA IHV, ON ON-state current VHVstart IHV, OFF 8/32 V VHV > VHvstart, Vcc> 3 V 1.6 VHV > VHvstart, Vcc = 0 0.8 Leakage current (OFF-state) VHV = 400 V mA 40 µA L6591 Electrical characteristics Table 4. Electrical characteristics (continued) (TJ = 0 to 105 °C, Vcc = 15 V, VBOOT = 12 V, CHVG = CLVG = 1 nF; RT = 22 kΩ, CT = 330 pF; unless otherwise specified) Symbol Parameter VCCrestart HV generator restart voltage Test condition (1) (1) After DIS tripping Min Typ Max Unit 4.4 5 5.6 V 12.2 13.2 14.2 V 5 5.1 V Reference voltage (2) VREF Output voltage TJ = 25 °C; IREF = 1 mA 4.9 VREF Total variation Vcc= 9.2 to 22 V, IREF = 1 to 5 mA 4.8 5.2 V IREF Short circuit current VREF = 0 10 30 mA Sink capability in UVLO Vcc = 6 V; Isink = 0.5 mA 0.5 V -1 µA 0.2 Current sense comparator IISEN Input bias current VISEN = 0 tLEB Leading edge blanking After VHVG low-to-high transition td(H-L) Delay to output Gain VISENx 200 Maximum signal VISENdis Hiccup-mode OCP level (2) V COMP =5V ns 170 ns 3.8 4 4.2 V/V 0.76 0.8 0.84 V (2) 1.4 1.5 1.65 V ICOMP = 0 5.5 VCOMP = 2 V 240 PWM control and burst-mode control VCOMPH Maximum level ICOMP Source current RCOMP Dynamic resistance VCOMPBon Burst-mode on threshold VCOMP = 2 to 4 V (2) VCOMP falling V 320 400 kΩ 25 1.68 Hys Burst-mode hysteresis VCOMP rising Dmax Maximum duty cycle VCOMP = 5 V 45 (2) 1.9 1.75 µA 1.82 70 V mV 50 % 2 2.1 V Adaptive UVLO VCOMPL UVLO shift threshold Line sensing Vth Threshold voltage Voltage rising or falling 1.22 1.25 1.28 V IHys Current hysteresis Vcc > 5 V 13.2 14.7 16.2 µA Clamp level ILINE = 1 mA 2.8 3 Vclamp V 9/32 Electrical characteristics Table 4. L6591 Electrical characteristics (continued) (TJ = 0 to 105 °C, Vcc = 15 V, VBOOT = 12 V, CHVG = CLVG = 1 nF; RT = 22 kΩ, CT = 330 pF; unless otherwise specified) Symbol Parameter Test condition Min Typ Max Unit -1 µA DIS function IOTP Input bias current Vth Disable threshold VDIS = 0 to Vth 4.275 4.5 4.725 V TJ = 25 °C 170 180 190 kHz Vcc = 9.2 to 22 V 168 180 192 kHz Oscillator peak voltage (2) 2.85 3 3.15 V Oscillator valley voltage (2) 0.75 0.9 1.05 V Oscillator and dead-time programming fosc Vpk Vvy Oscillation frequency Dead-time (VHVG high-to-low to VLVG low-to-high transition) Tdead 0.42 CT = 1 nF 1.0 µs Dead-time (VLVG high-to-low to VHVG low-to-high transition) 0.42 CT = 1 nF 1.0 Soft-start ISSC ISsdis Charge current Discharge current VSsclamp High saturation voltage TJ = 25 °C, VSS < 1.5 V, VCOMP = 4 V 14 17 20 TJ = 25 °C, VSS > 1.5 V, VCOMP = VCOMPH 3.0 4.2 5.4 VSS > 1.5 V 3.0 4.2 5.4 µA VCOMP = 4 V VSSDIS Disable level (2) VSSLAT Latch-off level VCOMP = VCOMPH VCOMP = VCOMPH 2 4.85 5 µA V 5.15 6.4 V V PFC_STOP function Ileak VL High level leakage current VPFC_STOP = Vcc, VCOMP = 2 V 1 µA Low saturation level IPFC_STOP = 2 mA VCOMP = 1.5 V 0.1 V 1.0 V Low-side gate driver (voltages referred to GND) VLVGL Output low voltage VLVGH Output high voltage Isourcepk Peak source current Isinkpk tf 10/32 Peak sink current Fall time (3) Isink = 200 mA Isource = 5 mA (3) 12.8 13.3 V -0.3 A 0.8 A 40 ns L6591 Electrical characteristics Table 4. Electrical characteristics (continued) (TJ = 0 to 105 °C, Vcc = 15 V, VBOOT = 12 V, CHVG = CLVG = 1 nF; RT = 22 kΩ, CT = 330 pF; unless otherwise specified) Symbol tr Parameter Test condition Min Rise time Typ Max 80 Vcc = 0 to VccOn, Isink = 1 mA UVLO saturation Unit ns 1.1 V 1.5 V High-side gate driver (voltages referred to FGND) VHVGL Output low voltage VHVGH Output high voltage Isourcepk Peak source current Isinkpk Isink = 200 mA Isource = 5 mA (3) Peak sink current (3) 11 11.9 V -0.3 A 0.8 A tf Fall time 40 ns tr Rise time 80 ns Pull-down resistor 25 kΩ 1. Parameters in tracking each other 2. Parameters in tracking each other 3. Parameters guaranteed by design 11/32 Application information 5 L6591 Application information The L6591 is an advanced current-mode PWM controller specific for fixed-frequency, peakcurrent-mode-controlled ZVS half-bridge converters. In these converters the switches (MOSFET’s) are controlled with complementary duty cycle: the high-side MOSFET is driven ON for a duty cycle D and the low-side MOSFET for a duty cycle 1-D. For a proper operation the maximum allowed duty cycle must be limited below 50 %. An externally programmable dead-time TD inserted between the turn-off of one MOSFET and the turn-on of the other one ensures soft-switching and enables high-frequency operation with high efficiency and low EMI emissions. See Section 5.6: Oscillator and deadtime programming on page 19 section for more information on how to program TD. The device is able to operate in different modes (Figure 4), depending on the converter’s load conditions: 1. Fixed frequency at heavy load. A relaxation oscillator, externally programmable with a capacitor and a resistor generates a sawtooth and releases clock pulses during the falling edges of the sawtooth. In this region the low-side MOSFET is turned off by the even pulses of the clock signal and the high-side MOSFET is turned on after a delay; the high-side MOSFET is turned off and, after a delay, the low-side MOSFET is turned on in response to the control loop. 2. Burst-mode control with no or very light load. When the load is extremely light or disconnected, the converter will enter a controlled on/off operation with fixed duty cycle, where a series of few switching cycles are spaced out by long periods where both MOSFET’s are in OFF-state. A load decrease will be then translated into a frequency reduction, which can go down even to few hundred hertz, thus minimizing all frequency-related losses and making it easier to comply with energy saving regulations. Being the peak current very low, no issue of audible noise arises. Figure 4. 12/32 Multi-mode operation L6591 5.1 Application information High-voltage start-up generator Figure 5 shows the internal schematic of the high-voltage start-up generator (HV generator). It is made up of a high-voltage N-channel FET, whose gate is biased by a 15 MW resistor, with a temperature-compensated current generator connected to its source. With reference to the timing diagram of Figure 6, when power is first applied to the converter the voltage on the bulk capacitor (Vin) builds up and, as it reaches about 80 V, the HV generator is enabled to operate (HV_EN is pulled high) and draws about 1 mA. This current, diminished by the IC consumption, charges the bypass capacitor connected between pin Vcc (9) and ground and makes its voltage rise almost linearly. As the Vcc voltage reaches the start-up threshold (13.5 V typ.) the IC starts operating and the HV generator is cut off by the Vcc_OK signal asserted high. The IC is powered by the energy stored in the Vcc capacitor until the self-supply circuit develops a voltage high enough to sustain the operation. The residual consumption of this circuit is just the one on the 15 MW resistor (≈10 mW at 400 Vdc), typically 50-70 times lower, under the same conditions, as compared to a standard start-up circuit made with an external dropping resistor. Figure 5. High-voltage start-up generator: internal schematic H VST ART L6591 16 15 MΩ& Vcc_OK HV_EN I HV 9 Vcc CONT ROL Icharge 11 GN D 13/32 Application information Figure 6. L6591 Timing diagram: normal power-up and power-down sequences Vi n VH s tart Vcc Vccon regulation is lost here t Vccoff Vcc res tart t PFC_STOP HVG, LVG t HV_EN t Vcc_OK Icharg e t 0.75 mA t Power-on Normal operation Power-off At converter power-down the system will lose regulation as soon as the input voltage is so low that either peak current or maximum duty cycle limitation is tripped. Vcc will then drop and stop IC’s activity as it falls below the UVLO threshold (10.5 V typ.). The Vcc_OK signal is de-asserted as the Vcc voltage goes below a threshold Vccrest located at about 5 V. The HV generator can now restart but, if Vin < Vinstart, as shown in Figure 6, HV_EN is deasserted too and the HV generator is disabled. This prevents converter’s restart attempts and ensures monotonic output voltage decay at power-down. The low restart threshold Vccrest ensures that, during short circuits, the restart attempts of the L6591 will have a very low repetition rate, as shown in the timing diagram of Figure 7, and that the converter will work safely with extremely low power throughput. The restart threshold of the HV generator is changed when any latched disable function of the IC is invoked to ensure a real latch-off. For more details see “Latched shutdown” section. 14/32 L6591 Application information Figure 7. Timing diagram showing short-circuit behavior (SS pin clamped below 5 V) Vcc LVG,HVG Vcc_OK 5.2 Operation at no load or very light load When the PWM control voltage at pin COMP falls below a threshold located at 1.75 V, the IC is disabled with both the high-side and the low-side MOSFET kept in OFF-state, the oscillator stopped and the quiescent consumption very much reduced to minimize Vcc capacitor discharge. The control voltage now will increase as a result of the feedback reaction to the energy delivery stop and, as it exceeds 1.82 V, the IC will restart switching. After a while, the control voltage will go down again in response to the energy burst and stop the IC. In this way the converter will work in a burst-mode fashion with a nearly constant peak current. A further load decrease will then cause a frequency reduction, which can go down even to few hundred hertz, thus minimizing all frequency-related losses and making it easier to comply with energy saving regulations. The timing diagram of Figure 8 illustrates this kind of operation, showing the most significant signals. If it is necessary to decrease the intervention threshold of the burst-mode operation, this can be done by adding a small DC offset on the current sense pin as shown in Figure 9. Note: The offset reduces the available dynamics of the current signal; thereby, the value of the sense resistor must be determined taking this offset into account. 15/32 Application information Figure 8. L6591 Load-dependent operating modes: timing diagram COMP 1.82V 1.75V t fosc t L VG, HVG t PF C_STOP PFC GATE-DR IVE Fi x. Fr eq . M od e Figure 9. Bu rst-mo d e Fi x. Fre q . Mo de Addition of an offset to the current sense lowers the burst-mode operation threshold Vo = Vref R R + Rc Vref 6 10 LVG L6591 Rc R 4 11 I SEN GND Rs To help the designer meet energy saving requirements even in power-factor-corrected systems, where a PFC pre-regulator precedes the DC-DC converter, the L6591 allows that the PFC pre-regulator can be turned off during burst-mode operation, hence eliminating the no-load consumption of this stage (0.5÷1 W). There is no compliance issue in that because EMC regulations on low-frequency harmonic emissions refer to nominal load, no limit is envisaged when the converter operates with light or no load. To do so, the L6591 provides the PFC_STOP (#8) pin: it is an open collector output, normally open, that is asserted low when the IC is idle during burst-mode operation. This signal will be externally used for switching off the PFC controller and the pre-regulator as shown in Figure 10. When the L6591 is in UVLO the pin is kept open, to let the PFC controller starts first. 16/32 L6591 Application information Figure 10. How the L6591 can switch off a PFC controller at light load ZCD Vref 5.6 kΩ k 6 47 kΩ k L6591 8 PFC_STOP B C547 B C547 8 5.3 L6591 L6562 PFC_STOP L6563 PFC_OK (AC_OK) PWM control block The device is specific for secondary feedback. Typically, there is a TL431 at the secondary side and an optocoupler that transfers output voltage information to the PWM control at the primary side, crossing the isolation barrier. The PWM control input (pin #7, COMP) is driven directly by the phototransistor’s collector (the emitter is grounded) to modulate the duty cycle. It is recommended to place a small filter capacitor between the pin and GND (#11), as close to the IC as possible to reduce switching noise pick up, to set a pole in the output-tocontrol transfer function. 5.4 PWM comparator, PWM latch and hiccup-mode OCP The PWM comparator senses the voltage across the current sense resistor (Rs) and, by comparing it with the programming signal derived by the voltage on pin COMP (#7), determines the exact time when the high-side MOSFET is to be switched off. The PWM latch avoids spurious switching, which might be caused by the noise generated (“doublepulse suppression”). A second comparator senses the voltage on the current sense input and shuts the IC down if the voltage at the pin exceeds 1.5 V. Such an anomalous condition is typically generated by either a short circuit of one of the secondary rectifiers or a shorted secondary winding or a saturated transformer. This condition is latched as long as the IC is supplied; hence if the IC is supplied by an external source it is necessary to disconnect the source to restart the IC. To distinguish an actual malfunction from a disturbance (e.g. induced during ESD tests), the first time the comparator is tripped the protection circuit enters a “warning state”. If in the next switching cycle the comparator is not tripped, a temporary disturbance is assumed and the protection logic will be reset in its idle state; if the comparator will be tripped again a real malfunction is assumed and the L6591 will be stopped. If the device is self-supplied no energy is coming from the self-supply circuit, then the voltage on the Vcc capacitor will decay and cross the UVLO threshold after some time, which clears the latch. The internal start-up generator is still off, then the Vcc voltage still needs to go below its restart voltage before the Vcc capacitor is charged again and the IC restarted. Ultimately, either of the above mentioned failures will result in a low-frequency intermittent operation (Hiccup-mode operation), with very low stress on the power circuit. The timing diagram of Figure 11 illustrates this operation. 17/32 Application information L6591 Figure 11. Hiccup-mode OCP: timing diagram (device self-supplied) Sec on da ry di od e i s s ho rted he re Vc c Vcc on Vcc off Vccr esta rt VC S 1.5 V LVG, HV G t t OC P la tc h t Vc c_ OK t PFC _S top t t 5.5 Latched shutdown The L6591 is equipped with a comparator having the non-inverting input externally available at the pin DIS (#2) and with the inverting input internally referenced to 4.5 V. As the voltage on the pin exceeds the internal threshold, the IC is immediately shut down and its consumption reduced at a low value. The information is latched and it is necessary to let the voltage on the Vcc pin go below the UVLO threshold to reset the latch and restart the IC. To keep the latch supplied as long as the converter is connected to the input source, the HV generator is activated periodically so that Vcc oscillates between the start-up threshold VccON and VccON – 1 V. It is then necessary to disconnect the converter from the input source to restart the IC. This operation is shown in the timing diagram of Figure 12. Activating the HV generator in this way cuts its power dissipation approximately by three (as compared to the case of continuous conduction) and keeps peak silicon temperature close to the average value. 18/32 L6591 Application information Figure 12. Operation after latched disable activation: timing diagram DIS 4 .5V V cc t Vcc on Vcc on - 1 Vcco ff Disa ble la tch i s re set h ere H V g ene ra to r i s turn ed on Vcc re sta rt LVG, H VG HV gen erator tu rn-on i s d isabl ed he re P FC_ STOP Inpu t sou rce i s re moved he re t t Vin VHsta rt t This function is useful to implement a latched over temperature protection very easily by biasing the pin with a divider from VREF, where the upper resistor is an NTC physically located close to a heating element like the MOSFET, or the secondary diode or the transformer. An OVP can be implemented as well, e.g. by sensing the output voltage and transferring an overvoltage condition via an optocoupler. 5.6 Oscillator and dead-time programming The oscillator is programmed externally by means of a resistor-capacitor network (RT, CT) connected from pin OSC (#5) to VREF (#6) and to ground respectively. Once chosen the oscillator frequency and the dead-time duration needed, the values of RT and CT can be calculated as: Equation 1 R T = 50 + 1150 ( fosc Td − 125 ⋅ 10 −9 ) Equation 2 C T = 1.39 ⋅ 1 fosc ⋅ R T − 1200 R T (R T − 50 ) After having selected the commercial values for RT and CT, the oscillator frequency (fosc) can be verified with good approximation using the following formula: 19/32 Application information L6591 Equation 3 fosc ≈ 1.39 (C T (R T + 1150)) During the negative-going ramp of the sawtooth a clock pulse is released. A T flip-flop, along with a logic circuit, separates the odd and the even clock pulses. The even ones turn off the low-side MOSFET first and, after a dead time Td, turn on the high-side MOSFET. Normally, the high-side MOSFET is turned off (and the low-side MOSFET turned on after the dead time Td) in response to the control loop; in case of overload it will be the overcurrent comparator to do the job or, in case of open control loop, the odd clock pulses will limit the maximum ON-time within one oscillator cycle. In this way, the maximum duty cycle will be limited right below 50 % and the operating frequency of the converter will be half that of the oscillator. Precisely, with reference to the waveforms in Figure 15, where Tsw= 2/fosc, the maximum achievable duty cycle is: Equation 4 Dmax TSW − Td T = 2 = 0.5 − d = 0.5 (1 − Td fosc ) TSW TSW At start-up the first clock pulse will turn on the low-side MOSFET for 10 oscillator cycles to charge the bootstrap capacitor and then the high-side MOSFET will switch on. When the IC resumes switching during burst-mode operation the first clock pulse will turn-on the low-side MOSFET first to charge the bootstrap capacitor, and just after the second clock pulse the high-side MOSFET will switch-on. In this way the bootstrap capacitor will always be charged and ready to supply the high-side floating driver. The oscillator waveforms are illustrated in Figure 15 as well. The dead-time Td equals the duration of the negative-going ramp of the oscillator sawtooth plus an internal delay of 125 ns; hence it depends on the timing capacitor CT and the resistor RT and is given by the approximate relationship: Equation 5 Td = C T 2 .1 2.54 ⋅ 10 −3 3.05 − RT + 125 ⋅ 10 −9 There is an internal 325 ns limit to the minimum Td value, to make sure that no hazardous condition of shoot-through can be generated, however it is recommended not to use capacitor values lower than 220 pF. 20/32 L6591 Application information Figure 13. Oscillator waveforms and their relationship with gate-driving signals OSC t Clock t HVG t LVG Td Td T on Td t Tsw Adaptive UVLO A major problem when optimizing a converter for minimum no-load consumption is that the voltage generated by the self-supply system under these conditions falls considerably as compared even to a few mA load. This very often causes the IC's supply voltage Vcc to drop and go below the UVLO threshold of the controller so that the operation becomes intermittent, which is undesired. A low UVLO threshold would be helpful but it could be an issue to drive the MOSFETS with a sufficient gate-drive voltage at heavy load during power off. To help the designer overcome this problem, the L6591, besides reducing its own consumption during burst-mode operation, also features a proprietary adaptive UVLO function. It consists of shifting the UVLO threshold downwards at light load, namely when the voltage at pin COMP falls below a threshold VCOMPL internally fixed, so as to provide more headroom. To prevent any malfunctioning during transients from minimum to maximum load the normal (higher) UVLO threshold is re-established when the voltage at pin COMP exceeds VCOMPL (with some mV hysteresis) and Vcc has exceeded the normal UVLO threshold (see Figure 16). The normal UVLO threshold ensures that under heavy load conditions the MOSFETS will be driven with an appropriate gate voltage. Figure 14. Adaptive UVLO block VCOMP Vcc 9 VCOMPO VCOMPL + R - COMP 7 S + SW Vcc t VCC OFF1 - VCOMPL UVLO Q + 5.7 PFC_ ST OP logic VCC OFF1 (*) VCC OFF2 VCC OFF2 (*) L6591 8 Q t PFC _STOP (*) V CC OF F2 < V CC OFF1 is selected when Q is high t 21/32 Application information 5.8 L6591 Line sensing function This function basically stops the IC as the input voltage to the converter falls below the specified range and lets it restart as the voltage goes back within the range. The sensed voltage can be either the rectified and filtered mains voltage, in which case the function will act as a brownout protection, or, in systems with a PFC pre-regulator front-end, the output voltage of the PFC stage, in which case the function will serve as a power-on and power-off sequencing. L6591 shutdown upon input under voltage is accomplished by means of an internal comparator, as shown in the block diagram of Figure 17, whose non-inverting input is available at the LINE pin (#1). The comparator is internally referenced to 1.25 V and disables the IC if the voltage applied at the LINE pin is below the internal reference. Under these conditions the soft-start discharged, the pin PFC_STOP is open and the consumption of the IC is reduced. PWM operation is re-enabled as the voltage on the pin is above the reference. The comparator is provided with current hysteresis instead of a more usual voltage hysteresis: an internal 15 µA current sink is ON as long as the voltage applied at the LINE pin is below the reference and is OFF if the voltage is above the reference. Figure 15. Line sensing function: internal block diagram and timing diagram HV Input bus VinON VinOFF LINE t 1.25V HV Input bus t Vcc Vin OK 9 IHYS RH LINE 1 + 15µA RL t 15µA 3V 1.25V Vin OK - L6591 Vcc t t LVG, HVG Vout t t This approach provides an additional degree of freedom: it is possible to set the ON threshold and the OFF threshold separately by properly choosing the resistors of the external divider (see below). With voltage hysteresis, instead, fixing one threshold automatically fixes the other one depending on the built-in hysteresis of the comparator. With reference to Figure 17, the following relationships can be established for the ON (VinON) and OFF (VinOFF) thresholds of the input voltage: 22/32 L6591 Application information Equation 6 Vin ON − 1.25 1.25 = 15 ⋅ 10 − 6 + RH RL VinOFF − 1.25 1.25 = RH RL Which, solved for RH and RL, yield: Equation 7 RH = VinON − VinOFF 15 ⋅ 10 −6 ; RL = RH 1.25 VinOFF − 1.25 While the line undervoltage is active the start-up generator keeps on working but there is no PWM activity, thus the Vcc voltage continuously oscillates between the start-up and the UVLO thresholds, as shown in the timing diagram of Figure 17. The LINE pin, while the device is operating, is a high impedance input connected to high value resistors, thus it is prone to pick up noise, which might alter the OFF threshold or give origin to undesired switch-off of the IC during ESD tests. It is possible to bypass the pin to ground with a small film capacitor (e.g. 1-10 nF) to prevent any malfunctioning of this kind. If the function is not used the pin has to be connected to the VREF pin (#6) through a resistor in the range of 10 to 100 kΩ. 5.9 Soft-start and delayed latched shutdown upon overcurrent At device start-up, a capacitor (Css) connected between the SS pin (#4) and ground is charged by an internal current generator, ISS1, from zero up to about 2 V where it is clamped. During this ramp, the overcurrent setpoint progressively raises from zero the final value (0.8 V). The time needed for the overcurrent setpoint to reach its steady state value, referred to as soft-start time, is approximately: Equation 8 TSS = 0.8 CSS ISS1 During the ramp, the MOSFET duty cycle increases progressively, hence controlling the start-up inrush current. Furthermore, all the functions that monitor the voltage on pin COMP are disabled. The soft-start pin is also invoked whenever the control voltage (COMP) saturates high, which reveals an open-loop condition for the feedback system. This condition very often occurs at start-up, but may be also caused by either a control loop failure or a converter overload/short circuit. 23/32 Application information L6591 Figure 16. Soft-start pin operation under different operating conditions While in case of feedback loop failure the system must be stopped quickly to prevent the output voltage from reaching too high values, an overload or a short circuit does not generally need such fast intervention. The L6591 makes it easier to handle such conditions: the 2 V clamp on the SS pin is removed and a second internal current generator ISS2 = ISS1 /4 keeps on charging Css. If the voltage reaches 5 V the IC will be disabled, if it is allowed to reach 2 VBE over 5 V, the IC will be latched off. In the former case the resulting behavior will be identical to that under short circuit illustrated in Figure 11; in the latter case the result will be identical to that of Figure 12. The time delay before stopping switching upon overload is: Equation 9 Tdelay = 12 C SS ISS1 If the overload disappears before the SS voltage reaches 5 V the ISS2 generator will be turned off and the voltage gradually brought back down to 2 V. A diode, with the anode to the SS pin and the cathode connected to the VREF pin (#6) allows the designer to select either an auto-restart mode or a latch-mode behavior upon overload. If latch-mode behavior is desired also for converter ’s short circuit, make sure that the supply voltage of the IC never falls below the UVLO threshold before activating the latch. Figure 18 shows soft-start pin behavior under different operating conditions. Figure 17 shows a typical high-power adapter application that uses the L6591 in conjunction with the L6563 PFC controller. 24/32 L6591 6 Summary of L6591 power management functions Summary of L6591 power management functions It has been seen that the device is provided with a number of power management functions: different operating mode upon loading conditions, protection functions, as well as interaction with the PFC pre-regulator. To help the designer familiarize with these functions, in the following tables all of theme are summarized with their respective activation mechanism and the resulting status of the most important pins. This can be useful not only for a correct use of the IC but also for diagnostic purposes: especially at prototyping/debugging stage, it is quite common to bump into unwanted activation of some function, and these tables can be used as a sort of quick troubleshooting guide. Table 5. Light load management Description Caused by Vcc IC Consumption restart PFC_STOP behavior [mA] [V] Controlled ON-OFF operation for Burst mode low power consumption at light load VCOMP < VCOMPBon Pulse skipping operation Extended Vcc range at light load VCOMP < VCOMPL UVLO threshold reduction Feature Adaptive UVLO Table 6. OSC N.A. 2 mA max when VCOMP < VCOMPBon Active (low) when VCOMP < VCOMPBon No change Stopped when VCOMP < VCOMPBon N.A. N.A. No change No change Run Protections Vcc IC IC Iq VREF restart behavior [mA] [V] [V] SS VCOMP [V] OSC [V] PFC_STOP 5 N.A. 0 Stop Active (low) 0.35 max 0 N.A. 0 Stop Active (low) 5 1.2 5 N.A. 0 Stop Active (low) 13 0.35 max 0 N.A. 0 Stop Active (low) Protection Description Caused by OLP Output overload protection VCOMP = VCOMPH VSS > VSSDIS Auto restart (1) 5 1.2 VCOMP = VCOMPH VSS > VSSLAT Latched 13 VCOMP = VCOMPH VSS > VSSDIS Auto restart (1) VCOMP = VCOMPH VSS > VSSLAT Latched Short circuit protection SS Output short circuit protection 25/32 Summary of L6591 power management functions Table 6. Protection L6591 Protections (continued) Description Caused by 2nd OCP Transformer VISEN > saturation or 1.5 V for 2 shorted consecutive secondary switching diode cycles protection DISABLE Externally programmabl e latched protection Brownout Mains undervoltage protection Vcc IC IC Iq VREF restart behavior [mA] [V] [V] SS VCOMP [V] OSC [V] PFC_STOP (2) 5 0.35 max 0 0 0 Stop Active (low) VDIS > 4.5 V Latched 13 0.35 max 0 0 0 Stop Active (low) VLINE < 1.25 V Auto restart 5 0.35 max 0 0 0 Stop Not active (high Z) Latched 1. Use one external diode from SS (#14) to VREF (#10), cathode to VREF. 2. The condition is latched as long as the IC is supplied; the HV generator is not invoked. 3. All values are typical unless otherwise specified. It is worth reminding that “auto-restart” means that the device will work intermittently as long as the condition that is activating the function is not removed; “Latched” means that the device is stopped as long as the unit is connected to the input power source and the unit must be disconnected for some time from the source in order for the device (and the unit) to restart. 26/32 L6591 Summary of L6591 power management functions Figure 17. L6591 typical application: 180 W, WRM, power-factor-corrected AC-DC adapter F1 T4A Vin = 88 to 264 V ac NTC1 10 LF1-A R1A 2M BD1 FBI 6K5F1 LF2-A CX1 0.47 F R1B 2M CX2 0. 68 F LF1-B R2 68k C1 11 0.47 F 630V 8 R13 47 8 R7 10 L6563 12 14 BOOT 15 9 13 10 HVG 5 R8A, B 0.27 R5 C7 330k 1nF Q2 TBD R14 TBD D3 1N4148 C13 100n R15 TBD R10 9.53k 3 L659 1 C14 TBD T2 L1 TB D D6 TBD C21 TBD DIS 1/ 2 PC817A 3 GND_OUT LVG Q3 TB D ISEN D7 TBD R19 TBD R20 TBD OSC SS OC1 GND 4 3 NTC1 TBD R21 TB D C16 100 nF D5 1N4148 (optional) C17 TBD 1 R22 TBD 2 R23 1.2 k COMP 4 OC2B C15 TBD V REF PC817A C18 TBD C19 TBD C22 TBD C23 TBD 11 7 Vout +18V / 10A D4 1N4148 R16 TB D R18 TB D 4 R12 21k C8 10nF T2B R17 TBD 5 C9 150 µF 450V 13 10 4 FGND IC2 6 R11B 2M D2 1N4148 14 2 R11A 2M R9B 1M Q1 STP20NM50 9 7 1 I C1 R9A 1M R6 100k Vcc 16 1 2 C12 47 F 25V HVSTART C3 1µF C5 C6 220n 470nF C11 220n LI NE 6 C4 3. 3nF R2 33k PFC_STOP R4 4. 7k 3 LF2-B C10 10n D1 STTH1L06 T1 R3 33 C2 DZ1 10nF 15V C20 TBD DZ2 18V OC2A R24 TBD I C3 TL431 C24 TBD R25 TBD R26 TBD 1 2 1/2 PC817A R27 TBD 27/32 Package mechanical data 7 L6591 Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. 28/32 L6591 Package mechanical data Figure 18. SO16N package dimensions mm inch DIM. MIN. TYP. A a1 MAX. MIN. TYP. 1.75 0.1 0.25 a2 MAX. 0.069 0.004 0.009 1.6 0.063 b 0.35 0.46 0.014 0.018 b1 0.19 0.25 0.007 0.010 45° (typ.) C 0.5 c1 0.020 D(1) 9.8 10 0.386 0.394 E 5.8 6.2 0.228 0.244 e 1.27 e3 0.050 8.89 0.350 F(1) 3.8 G 4.60 5.30 0.181 0.208 L 0.4 1.27 0.150 0.050 M S OUTLINE AND MECHANICAL DATA 4.0 0.150 0.62 0.157 0.024 8 ° (max.) SO16N SO16 (Narrow) (1) "D" and "F" do not include mold flash or protrusions - Mold flash or protrusions shall not exceed 0.15mm (.006inc.) 0016020 D 29/32 Order codes 8 Order codes Table 7. 30/32 L6591 Order codes Order codes Package Packaging L6591 SO16N Tube L6591TR SO16N Tape and reel L6591 9 Revision history Revision history Table 8. Document revision history Date Revision 19-Jun-2008 1 Changes Initial release 31/32 L6591 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK. Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2008 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 32/32