STMICROELECTRONICS M25PE80

M25PE80
8 Mbit, Low Voltage, Page-Erasable Serial Flash Memory with
Byte-Alterability, 50MHz SPI Bus, Standard Pin-out
PRELIMINARY DATA
FEATURES SUMMARY
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Industrial Standard SPI Pin-out
8 Mbits of Page-Erasable Flash Memory
Page Write (up to 256 Bytes) in 11ms (typical)
Page Program (up to 256 Bytes) in 1.2ms
(typical)
Page Erase (256 Bytes) in 10ms (typical)
Sector Erase (512 Kbits)
Bulk Erase (8 Mbits)
2.7 to 3.6V Single Supply Voltage
SPI Bus Compatible Serial Interface
50MHz Clock Rate (maximum)
Deep Power-down Mode 1µA (typical)
Electronic Signature
– JEDEC Standard Two-Byte Signature
(8014h)
More than 100,000 Write Cycles
More than 20 Year Data Retention
Hardware Write Protection of the Top Sector
(64KB)
Software Write Protection on a 64KByte
Sector Basis
Software Write Protection on a 4KByte Subsector Basis for Sector 0 and Sector 15
August 2005
Figure 1. Packages
VDFPN8 (MP)
6 x 5mm (MLP8)
8
1
SO8W (MW)
208 mils width
1/43
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
M25PE80
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1.
Figure 2.
Table 1.
Figure 3.
Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
VDFPN and SO Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Serial Data Output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Serial Data Input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Reset (Reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Top Sector Lock (TSL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
SPI MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. Bus Master and Memory Devices on the SPI Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 5. SPI Modes Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
OPERATING FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Sharing the Overhead of Modifying Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
An Easy Way to Modify Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
A Fast Way to Modify Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Polling During a Write, Program or Erase Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Active Power, Standby Power and Deep Power-Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 2. Status Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 3. Software Protection Truth Table (Sectors 1 to 14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 4. Software Protection Scheme Truth Table (Sectors 0 and 15) . . . . . . . . . . . . . . . . . . . . . 10
Figure 6. Software Protection Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 5. Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 7. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 6. Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 8. Write Enable (WREN) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
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M25PE80
Figure 9. Write Disable (WRDI) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Read Identification (RDID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 7. Read Identification (RDID) Data-Out Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 10.Read Identification (RDID) Instruction Sequence and Data-Out Sequence . . . . . . . . . . 16
Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 11.Read Status Register (RDSR) Instruction Sequence and Data-Out Sequence . . . . . . . 17
Read Data Bytes (READ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 12.Read Data Bytes (READ) Instruction Sequence and Data-Out Sequence . . . . . . . . . . . 18
Read Data Bytes at Higher Speed (FAST_READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 13.Read Data Bytes at Higher Speed (FAST_READ) Instruction Sequence
and Data-Out Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Read Lock Register (RDLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 8. Lock Register Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 14.Read Lock Register (RDLR) Instruction Sequence and Data-Out Sequence . . . . . . . . . 20
Page Write (PW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 15.Page Write (PW) Instruction Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Page Program (PP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 16.Page Program (PP) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Write to Lock Register (WRLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 17.Write to Lock Register (WRLR) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 9. Lock Register In. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Page Erase (PE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 18.Page Erase (PE) Instruction Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Sector Erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 19.Sector Erase (SE) Instruction Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Bulk Erase (BE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 20.Bulk Erase (BE) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Deep Power-down (DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 21.Deep Power-down (DP) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Release from Deep Power-down (RDP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 22.Release from Deep Power-down (RDP) Instruction Sequence. . . . . . . . . . . . . . . . . . . . 29
POWER-UP AND POWER-DOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 23.Power-up Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 10. Power-Up Timing and VWI Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
INITIAL DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 11. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 12. Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 13. AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
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M25PE80
Figure 24.AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 14. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 15. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 16. AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 25.Serial Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 26.Top Sector Lock Setup and Hold Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 27.Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 17. Reset Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 28.Reset AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 29.MLP8, 8-lead Very thin Dual Flat Package No lead, 6x5mm, Package Outline . . . . . . . 39
Table 18. MLP8, 8-lead Very thin Dual Flat Package No lead, 6x5mm,
Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 30.SO8 wide – 8 lead Plastic Small Outline, 208 mils body width, Package Outline . . . . . . 40
Table 19. SO8 wide – 8 lead Plastic Small Outline, 208 mils body width, Mechanical Data . . . . . . 40
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 20. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 21. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
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M25PE80
SUMMARY DESCRIPTION
Table 1. Signal Names
The M25PE80 is an 8 Mbit (1Mb x 8) Serial Paged
Flash Memory accessed by a high speed SPIcompatible bus.
The memory can be written or programmed 1 to
256 Bytes at a time, using the Page Write or Page
Program instruction. The Page Write instruction
consists of an integrated Page Erase cycle followed by a Page Program cycle.
The memory is organized as 16 sectors, each containing 256 pages. Each page is 256 Bytes wide.
Thus, the whole memory can be viewed as consisting of 4096 pages, or 1,048,576 Bytes.
The memory can be erased a page at a time, using
the Page Erase instruction, a sector at a time, using the Sector Erase instruction, or as a whole, using the Bulk Erase instruction.
The memory can be Write Protected by either
Hardware or Software, with a protection granularity of either 64 KBytes (sector granularity) or 4
KBytes (sub-sector granularity inside sector 0 and
sector 15 only).
Figure 2. Logic Diagram
C
Serial Clock
D
Serial Data Input
Q
Serial Data Output
S
Chip Select
TSL
Top Sector Lock
Reset
Reset
VCC
Supply Voltage
VSS
Ground
Figure 3. VDFPN and SO Connections
M25PE80
S
Q
TSL
VSS
1
2
3
4
8
7
6
5
VCC
Reset
C
D
AI10780
VCC
D
Note: 1. There is an exposed die paddle on the underside of the
MLP8 package. This is pulled, internally, to VSS, and
must not be allowed to be connected to any other voltage
or signal line on the PCB.
2. See PACKAGE MECHANICAL section for package dimensions, and how to identify pin-1.
Q
C
S
M25PE80
TSL
Reset
VSS
AI10779
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M25PE80
SIGNAL DESCRIPTION
Serial Data Output (Q). This output signal is
used to transfer data serially out of the device.
Data is shifted out on the falling edge of Serial
Clock (C).
Low selects the device, placing it in the Active
Power mode.
After Power-up, a falling edge on Chip Select (S)
is required prior to the start of any instruction.
Serial Data Input (D). This input signal is used to
transfer data serially into the device. It receives instructions, addresses, and the data to be programmed. Values are latched on the rising edge of
Serial Clock (C).
Reset (Reset). The Reset (Reset) input provides
a hardware reset for the memory.
When Reset (Reset) is driven High, the memory is
in the normal operating mode. When Reset (Reset) is driven Low, the memory will enter the Reset
mode. In this mode, the output is high impedance.
Driving Reset (Reset) Low while an internal operation is in progress will affect this operation (write,
program or erase cycle) and data may be lost.
Serial Clock (C). This input signal provides the
timing of the serial interface. Instructions, addresses, or data present at Serial Data Input (D) are
latched on the rising edge of Serial Clock (C). Data
on Serial Data Output (Q) changes after the falling
edge of Serial Clock (C).
Chip Select (S). When this input signal is High,
the device is deselected and Serial Data Output
(Q) is at high impedance. Unless an internal Read,
Program, Erase or Write cycle is in progress, the
device will be in the Standby mode (this is not the
Deep Power-down mode). Driving Chip Select (S)
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Top Sector Lock (TSL). This input signal puts
the device in the Hardware Protected mode, when
Top Sector Lock (TSL) is connected to VSS, causing the top 256 pages (upper addresses) of the
memory to become read-only (protected from
write, program and erase operations).
When Top Sector Lock (TSL) is connected to VCC,
the top 256 pages of memory behave like the other
pages of memory.
M25PE80
SPI MODES
These devices can be driven by a microcontroller
with its SPI peripheral running in either of the two
following modes:
– CPOL=0, CPHA=0
– CPOL=1, CPHA=1
For these two modes, input data is latched in on
the rising edge of Serial Clock (C), and output data
is available from the falling edge of Serial Clock
(C).
The difference between the two modes, as shown
in Figure 5., is the clock polarity when the bus
master is in Stand-by mode and not transferring
data:
– C remains at 0 for (CPOL=0, CPHA=0)
– C remains at 1 for (CPOL=1, CPHA=1)
Figure 4. Bus Master and Memory Devices on the SPI Bus
SDO
SPI Interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
SDI
SCK
C Q D
C Q D
C Q D
SPI Memory
Device
SPI Memory
Device
SPI Memory
Device
Bus Master
(ST6, ST7, ST9,
ST10, Others)
CS3
CS2
CS1
S
TSL RP
S
TSL RP
S
TSL RP
AI10741
Note: The Top Sector Lock (TSL) signal should be driven, High or Low as appropriate.
Figure 5. SPI Modes Supported
CPOL
CPHA
0
0
C
1
1
C
D
Q
MSB
MSB
AI01438B
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M25PE80
OPERATING FEATURES
Sharing the Overhead of Modifying Data
To write or program one (or more) data Bytes, two
instructions are required: Write Enable (WREN),
which is one Byte, and a Page Write (PW) or Page
Program (PP) sequence, which consists of four
Bytes plus data. This is followed by the internal cycle (of duration tPW or tPP).
To share this overhead, the Page Write (PW) or
Page Program (PP) instruction allows up to 256
Bytes to be programmed (changing bits from 1 to
0) or written (changing bits to 0 or 1) at a time, provided that they lie in consecutive addresses on the
same page of memory.
An Easy Way to Modify Data
The Page Write (PW) instruction provides a convenient way of modifying data (up to 256 contiguous Bytes at a time), and simply requires the start
address, and the new data in the instruction sequence.
The Page Write (PW) instruction is entered by
driving Chip Select (S) Low, and then transmitting
the instruction Byte, three address Bytes (A23-A0)
and at least one data Byte, and then driving Chip
Select (S) High. While Chip Select (S) is being
held Low, the data Bytes are written to the data
buffer, starting at the address given in the third address Byte (A7-A0). When Chip Select (S) is driven High, the Write cycle starts. The remaining,
unchanged, Bytes of the data buffer are automatically loaded with the values of the corresponding
Bytes of the addressed memory page. The addressed memory page then automatically put into
an Erase cycle. Finally, the addressed memory
page is programmed with the contents of the data
buffer.
All of this buffer management is handled internally,
and is transparent to the user. The user is given
the facility of being able to alter the contents of the
memory on a Byte-by-Byte basis.
For optimized timings, it is recommended to use
the Page Write (PW) instruction to write all consecutive targeted Bytes in a single sequence versus using several Page Write (PW) sequences
with each containing only a few Bytes (see Page
Write (PW) section and Table 16., AC Characteristics).
A Fast Way to Modify Data
The Page Program (PP) instruction provides a fast
way of modifying data (up to 256 contiguous Bytes
at a time), provided that it only involves resetting
bits to 0 that had previously been set to 1.
8/43
This might be:
– when the designer is programming the device
for the first time
– when the designer knows that the page has
already been erased by an earlier Page Erase
(PE), Sector Erase (SE) or Bulk Erase (BE)
instruction. This is useful, for example, when
storing a fast stream of data, having first
performed the erase cycle when time was
available
– when the designer knows that the only
changes involve resetting bits to 0 that are still
set to 1. When this method is possible, it has
the additional advantage of minimising the
number of unnecessary erase operations, and
the extra stress incurred by each page.
For optimized timings, it is recommended to use
the Page Program (PP) instruction to program all
consecutive targeted Bytes in a single sequence
versus using several Page Program (PP) sequences with each containing only a few Bytes
(see Page Program (PP) section and Table
16., AC Characteristics).
Polling During a Write, Program or Erase Cycle
A further improvement in the write, program or
erase time can be achieved by not waiting for the
worst case delay (tPW, tPP, tPE, tSE or tBE). The
Write In Progress (WIP) bit is provided in the Status Register so that the application program can
monitor its value, polling it to establish when the
previous cycle is complete.
Reset
An internal Power-On Reset circuit helps protect
against inadvertent data writes. Addition protection is provided by driving Reset (RESET) Low
during the Power-on process, and only driving it
High when VCC has reached the correct voltage
level, VCC(min).
Active Power, Standby Power and Deep
Power-Down Modes
When Chip Select (S) is Low, the device is selected, and in the Active Power mode.
When Chip Select (S) is High, the device is deselected, but could remain in the Active Power mode
until all internal cycles have completed (Program,
Erase, Write). The device then goes in to the
Standby Power mode. The device consumption
drops to ICC1.
The Deep Power-down mode is entered when the
specific instruction (the Deep Power-down (DP) in-
M25PE80
struction) is executed. The device consumption
drops further to ICC2. When in this mode, only the
Release from Deep Power-down instruction is accepted. All other instructions are ignored. The device remains in the Deep Power-down mode until
the Release from Deep Power-down instruction is
executed. This can be used as an extra software
protection mechanism, when the device is not in
active use, to protect the device from inadvertent
Write, Program or Erase instructions.
–
–
■
Status Register
The Status Register contains two status bits that
can be read by the Read Status Register (RDSR)
instruction.
■
WIP bit. The Write In Progress (WIP) bit indicates
whether the memory is busy with a Write, Program
or Erase cycle.
■
WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
Table 2. Status Register Format
■
b7
0
b0
0
0
0
0
0
WEL
WIP
Note: WEL and WIP are volatile read-only bits (WEL is set and reset by specific instructions; WIP is automatically set and reset by the internal logic of the device).
Protection Modes
The environments where non-volatile memory devices are used can be very noisy. No SPI device
can operate correctly in the presence of excessive
noise. To help combat this, the M25PE80 features
the following data protection mechanisms:
■
Power On Reset and an internal timer (tPUW)
can provide protection against inadvertant
changes while the power supply is outside the
operating specification.
■
Program, Erase and Write instructions are
checked that they consist of a number of clock
pulses that is a multiple of eight, before they
are accepted for execution.
■
All instructions that modify data must be
preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch
(WEL) bit. This bit is returned to its reset state
by the following events:
– Power-up
– Reset (RESET) driven Low
– Write Disable (WRDI) instruction
completion
– Page Write (PW) instruction completion
Page Program (PP) instruction completion
Write to Lock Register (WRLR) instruction
completion
– Page Erase (PE) instruction completion
– Sector Erase (SE) instruction completion
– Bulk Erase (BE) instruction completion
The Hardware Protected mode is entered
when Top Sector Lock (TSL) is driven Low,
causing the top 256 pages of memory to
become read-only. When Top Sector Lock
(TSL) is driven High, the top 256 pages of
memory behave like the other pages of
memory
The Reset (Reset) signal can be driven Low to
protect the contents of the memory during any
critical time, not just during Power-up and
Power-down.
In addition to the low power consumption
feature, the Deep Power-down mode offers
extra software protection from inadvertant
Write, Program and Erase instructions while
the device is not in active use.
The Software Protection is managed by
specific Lock Registers assigned to each
sector and sub-sector as follows:
– each 64KB sector has a Lock Register
– inside sector 0 and sector 15, each 4KB
sub-sector also has a Lock Register (in
addition to the Lock Register at sector
level)
The Lock Registers can be read and written
using the Read Lock Register (RDLR) and
Write to Lock Register (WRLR) instructions.
In each Lock Register two bits control the
protection of each sector/sub-sector: the Write
Lock Bit and the Lock Down Bit.
– Write Lock Bit:
The Write Lock Bit determines whether
the contents of the sector/sub-sector can
be modified (using the Write, Program or
Erase instructions). When the Write Lock
Bit is set, ‘1’, the sector/sub-sector is write
protected – any operations that attempt to
change the data in the sector/sub-sector
will fail. When the Write Lock Bit is reset to
‘0’, the sector/sub-sector is not write
protected by the Lock Register, and may
be modified, unless TSL is Low (in which
case the top sector will remain write
protected).
– Lock Down Bit:
The Lock Down Bit provides a mechanism
for protecting software data from simple
hacking and malicious attack. When the
Lock Down Bit is set, ‘1’, further
9/43
M25PE80
modification to the Write Lock and Lock
Down Bits cannot be performed. A reset,
or power-up, is required before changes to
these bits can be made. When the Lock
Down Bit is reset, ‘0’, the Write Lock and
Lock Down Bits can be changed.
The Write Lock Bit and the Lock Down Bit are
volatile and their value is reset to ‘0’ after a
Power-Down or a Reset.
The definition of the Lock Register bits is given
in Table 8., Lock Register Out.
Refer to Table 3. and Table 4. for details on
the Software Protection for sectors 1 to 14 and
0 and 15, respectively. Figure 6.shows the the
Software Protection scheme.
Table 3. Software Protection Truth Table (Sectors 1 to 14)
Sector Lock
Register
Protection Status
Lock
Down
Bit
Write
Lock
Bit
0
0
Sector Unprotected from Program/Erase/Write operations, Protection Status Reversible
0
1
Sector Protected from Program/Erase/Write operations, Protection Status Reversible
1
0
Sector Unprotected from Program/Erase/Write operations,
Sector Protection Status cannot be changed except by a Reset or Power-up.
1
1
Sector Protected from Program/Erase/Write operations,
Sector Protection Status cannot be changed except by a Reset or Power-up.
Table 4. Software Protection Scheme Truth Table (Sectors 0 and 15)
Sector Lock
Register
Lock
Down
Bit
Write
Lock
Bit
Sub-Sector
Lock Register
Protection Status
Lock
Down
Bit
Write
Lock
Bit
0
0
Current Sub-Sector Unprotected from Program/Erase/Write operations,
Current Sub-Sector Protection Status Reversible
0
1
Current Sub-Sector Protected from Program/Erase/Write operations,
Current Sub-Sector Protection Status Reversible.
1
0
Current Sub-Sector Unprotected from Program/Erase/Write operations, Current
Sub-Sector Protection Status cannot be changed except by a Reset or Power-up.
1
1
Current Sub-Sector Protected from Program/Erase/Write operations, Current
Sub-Sector Protection Status cannot be changed except by a Reset or Power-up.
0
1
All Sub-Sectors Protected from Program/Erase/Write operations, Current SubSector Protection Status Reversible
1
1
All Sub-Sectors Protected from Program/Erase/Write operations, Current Subsector Protection Status cannot be changed except by a Reset or Power-up.
1
0
Current Sub-Sector Unprotected from Program/Erase/Write operations, All Subsectors Protection Status cannot be changed except by a Reset or Power-up
1
1
Current Sub-Sector Protected from Program/Erase/Write operations, All Subsectors Protection Status cannot be changed except by a Reset or Power-up
1
1
All Sub-sectors Protected with their Protection Status cannot be changed except
by a Reset or Power-up.
0
0
1
0
1
1
Note: 1. All other bits combinations are not-applicable.
2. For more details, refer to the description of the Write to Lock Register (WRLR) instruction.
10/43
M25PE80
Figure 6. Software Protection Scheme
±
Sub-Sector 15.15 (4KB)
Sub-Sector 15.15 Lock Register
Sub-Sector Modify Protected
WL bit
LD bit
SECTOR 15 LOCK REGISTER
±
SECTOR 15
Sub-Sector 15.15 Lock Register Frozen
±
Sub-Sector 15.0 (4KB)
±
All Sub-Sectors Modify Protected
Sub-Sector 15.0 Lock Register
Sub-Sector Modify Protected
WL bit
LD bit
LD bit
WL bit
±
All Sub-Sector Lock Registers Frozen
±
SECTOR 14
(64KBx 14)
Sub-Sector 15.0 Lock Register Frozen
±
SECTOR LOCK REGISTER 14
Sector Modify Protected
LD bit
WL bit
±
Sector Lock Register Frozen
±
SECTOR LOCK REGISTER 1
Sector Modify Protected
WL bit
LD bit
±
SECTOR 1
(64KBx 14)
Sector Lock Register Frozen
±
Sub-Sector 0.15 (4KB)
Sub-Sector 0.15 Lock Register
Sub-Sector Modify Protected
WL bit
LD bit
±
Sub-Sector 0.15 Lock Register Frozen
SECTOR 0
±
Sub-Sector 0.0 (4KB)
Sub-Sector 0.0 Lock Register
Sub-Sector Modify Protected
WL bit
LD bit
SECTOR 0 LOCK REGISTER
±
All Sub-Sectors Modify Protected
LD bit
WL bit
±
All Sub-Sector Lock Registers Frozen
±
Sub-Sector 0.0 Lock Register Frozen
AI11305a
Note: 1. LD Lock Down bit; WL Write Lock bit.
11/43
M25PE80
MEMORY ORGANIZATION
The memory is organized as:
■
4096 pages (256 Bytes each).
■
1,048,576 Bytes (8 bits each)
■
16 sectors (512 Kbits, 65536 Bytes each)
Each page can be individually:
– programmed (bits are programmed from 1 to
0)
– erased (bits are erased from 0 to 1)
– written (bits are changed to either 0 or 1)
The device is Page, Sector or Bulk Erasable (bits
are erased from 0 to 1).
12/43
Table 5. Memory Organization
Sector
Address Range
15
F0000h
FFFFFh
14
E0000h
EFFFFh
13
D0000h
DFFFFh
12
C0000h
CFFFFh
11
B0000h
BFFFFh
10
A0000h
AFFFFh
9
90000h
9FFFFh
8
80000h
8FFFFh
7
70000h
7FFFFh
6
60000h
6FFFFh
5
50000h
5FFFFh
4
40000h
4FFFFh
3
30000h
3FFFFh
2
20000h
2FFFFh
1
10000h
1FFFFh
0
00000h
0FFFFh
M25PE80
Figure 7. Block Diagram
Reset
TSL
High Voltage
Generator
Control Logic
S
C
D
I/O Shift Register
Q
Address Register
and Counter
Status
Register
256 Byte
Data Buffer
FFFFFh
Top 256 Pages can
be made read-only
by using the TSL pin
EFFFFh
Y Decoder
Whole Memory Array can
be made read-only
on a 64KB or 4KB basis
through the Lock Registers
00000h
000FFh
256 Bytes (Page Size)
X Decoder
AI10782b
13/43
M25PE80
INSTRUCTIONS
All instructions, addresses and data are shifted in
and out of the device, most significant bit first.
Serial Data Input (D) is sampled on the first rising
edge of Serial Clock (C) after Chip Select (S) is
driven Low. Then, the one-Byte instruction code
must be shifted in to the device, most significant bit
first, on Serial Data Input (D), each bit being
latched on the rising edges of Serial Clock (C).
The instruction set is listed in Table 6.
Every instruction sequence starts with a one-Byte
instruction code. Depending on the instruction,
this might be followed by address Bytes, or by data
Bytes, or by both or none.
In the case of a Read Data Bytes (READ), Read
Data Bytes at Higher Speed (Fast_Read), Read
Identification (RDID), Read Status Register (RDSR), or Read Lock Register (RDLR) instruction,
the shifted-in instruction sequence is followed by a
data-out sequence. Chip Select (S) can be driven
High after any bit of the data-out sequence is being shifted out.
In the case of a Page Write (PW), Page Program
(PP), Write to Lock Register (WRLR), Page Erase
(PE), Sector Erase (SE), Bulk Erase (BE), Write
Enable (WREN), Write Disable (WRDI), Deep
Power-down (DP) or Release from Deep Powerdown (RDP) instruction, Chip Select (S) must be
driven High exactly at a Byte boundary, otherwise
the instruction is rejected, and is not executed.
That is, Chip Select (S) must driven High when the
number of clock pulses after Chip Select (S) being
driven Low is an exact multiple of eight.
All attempts to access the memory array during a
Write cycle, Program cycle or Erase cycle are ignored, and the internal Write cycle, Program cycle
or Erase cycle continues unaffected.
Table 6. Instruction Set
Instruction
Description
One-Byte Instruction Code
Address
Bytes
Dummy
Bytes
Data
Bytes
WREN
Write Enable
0000 0110
06h
0
0
0
WRDI
Write Disable
0000 0100
04h
0
0
0
RDID
Read Identification
1001 1111
9Fh
0
0
1 to 3
RDSR
Read Status Register
0000 0101
05h
0
0
1 to ∞
WRLR
Write to Lock Register
1110 0101
E5h
3
0
1
RDLR
Read Lock Register
1110 1000
E8h
3
0
1
READ
Read Data Bytes
0000 0011
03h
3
0
1 to ∞
0000 1011
0Bh
3
1
1 to ∞
FAST_READ Read Data Bytes at Higher Speed
PW
Page Write
0000 1010
0Ah
3
0
1 to 256
PP
Page Program
0000 0010
02h
3
0
1 to 256
PE
Page Erase
1101 1011
DBh
3
0
0
SE
Sector Erase
1101 1000
D8h
3
0
0
BE
Bulk Erase
1100 0111
C7h
0
0
0
DP
Deep Power-down
1011 1001
B9h
0
0
0
Release from Deep Power-down
1010 1011
ABh
0
0
0
RDP
14/43
M25PE80
Write Enable (WREN)
(BE) and Write to Lock Register (WRLR) instructions.
The Write Enable (WREN) instruction is entered
by driving Chip Select (S) Low, sending the instruction code, and then driving Chip Select (S)
High.
The Write Enable (WREN) instruction (Figure 8.)
sets the Write Enable Latch (WEL) bit.
The Write Enable Latch (WEL) bit must be set prior to every Page Write (PW), Page Program (PP),
Page Erase (PE), Sector Erase (SE), Bulk Erase
Figure 8. Write Enable (WREN) Instruction Sequence
S
0
1
2
3
4
5
6
7
C
Instruction
D
High Impedance
Q
AI02281E
–
–
–
–
Write Disable (WRDI)
The Write Disable (WRDI) instruction (Figure 9.)
resets the Write Enable Latch (WEL) bit.
The Write Disable (WRDI) instruction is entered by
driving Chip Select (S) Low, sending the instruction code, and then driving Chip Select (S) High.
The Write Enable Latch (WEL) bit is reset under
the following conditions:
– Power-up
Write Disable (WRDI) instruction completion
Page Write (PW) instruction completion
Page Program (PP) instruction completion
Write to Lock Register (WRLR) instruction
completion
Page Erase (PE) instruction completion
Sector Erase (SE) instruction completion
Bulk Erase (BE) instruction completion
–
–
–
Figure 9. Write Disable (WRDI) Instruction Sequence
S
0
1
2
3
4
5
6
7
C
Instruction
D
High Impedance
Q
AI03750D
15/43
M25PE80
Read Identification (RDID)
The Read Identification (RDID) instruction allows
the 8-bit manufacturer identification to be read, followed by two Bytes of device identification. The
manufacturer identification is assigned by JEDEC,
and has the value 20h for STMicroelectronics. The
device identification is assigned by the device
manufacturer, and indicates the memory type in
the first Byte (80h), and the memory capacity of
the device in the second Byte (14h).
Any Read Identification (RDID) instruction while
an Erase or Program cycle is in progress, is not
decoded, and has no effect on the cycle that is in
progress.
The device is first selected by driving Chip Select
(S) Low. Then, the 8-bit instruction code for the instruction is shifted in. This is followed by the 24-bit
device identification, stored in the memory, being
shifted out on Serial Data Output (Q), each bit being shifted out during the falling edge of Serial
Clock (C).
The instruction sequence is shown in Figure 10..
The Read Identification (RDID) instruction is terminated by driving Chip Select (S) High at any time
during data output.
When Chip Select (S) is driven High, the device is
put in the Stand-by Power mode. Once in the
Stand-by Power mode, the device waits to be selected, so that it can receive, decode and execute
instructions.
Table 7. Read Identification (RDID) Data-Out Sequence
Device Identification
Manufacturer Identification
20h
Memory Type
Memory Capacity
80h
14h
Figure 10. Read Identification (RDID) Instruction Sequence and Data-Out Sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18
28 29 30 31
C
Instruction
D
Manufacturer Identification
Device Identification
High Impedance
Q
15 14 13
MSB
3
2
1
0
MSB
AI06809b
16/43
M25PE80
Read Status Register (RDSR)
WIP bit. The Write In Progress (WIP) bit indicates
whether the memory is busy with a Write, Program
or Erase cycle. When set to 1, such a cycle is in
progress, when reset to 0 no such cycle is in
progress.
The Read Status Register (RDSR) instruction allows the Status Register to be read. The Status
Register may be read at any time, even while a
Program, Erase or Write cycle is in progress.
When one of these cycles is in progress, it is recommended to check the Write In Progress (WIP)
bit before sending a new instruction to the device.
It is also possible to read the Status Register continuously, as shown in Figure 11..
The status bits of the Status Register are as follows:
WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When set to 1 the internal Write Enable Latch is
set, when set to 0 the internal Write Enable Latch
is reset and no Write, Program or Erase instruction
is accepted.
Figure 11. Read Status Register (RDSR) Instruction Sequence and Data-Out Sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
C
Instruction
D
Status Register Out
Status Register Out
High Impedance
Q
7
MSB
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
MSB
AI02031E
17/43
M25PE80
Read Data Bytes (READ)
next higher address after each Byte of data is shifted out. The whole memory can, therefore, be read
with a single Read Data Bytes (READ) instruction.
When the highest address is reached, the address
counter rolls over to 000000h, allowing the read
sequence to be continued indefinitely.
The Read Data Bytes (READ) instruction is terminated by driving Chip Select (S) High. Chip Select
(S) can be driven High at any time during data output. Any Read Data Bytes (READ) instruction,
while an Erase, Program or Write cycle is in
progress, is rejected without having any effects on
the cycle that is in progress.
The device is first selected by driving Chip Select
(S) Low. The instruction code for the Read Data
Bytes (READ) instruction is followed by a 3-Byte
address (A23-A0), each bit being latched-in during
the rising edge of Serial Clock (C). Then the memory contents, at that address, is shifted out on Serial Data Output (Q), each bit being shifted out, at
a maximum frequency fR, during the falling edge of
Serial Clock (C).
The instruction sequence is shown in Figure 12..
The first Byte addressed can be at any location.
The address is automatically incremented to the
Figure 12. Read Data Bytes (READ) Instruction Sequence and Data-Out Sequence
S
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
C
Instruction
24-Bit Address
23 22 21
D
3
2
1
0
MSB
Data Out 1
High Impedance
Q
7
6
5
4
3
2
Data Out 2
1
0
7
MSB
AI03748D
Note: Address bits A23 to A19 are Don’t Care.
18/43
M25PE80
Read Data Bytes at Higher Speed
(FAST_READ)
next higher address after each Byte of data is shifted out. The whole memory can, therefore, be read
with a single Read Data Bytes at Higher Speed
(FAST_READ) instruction. When the highest address is reached, the address counter rolls over to
000000h, allowing the read sequence to be continued indefinitely.
The Read Data Bytes at Higher Speed
(FAST_READ) instruction is terminated by driving
Chip Select (S) High. Chip Select (S) can be driven High at any time during data output. Any Read
Data Bytes at Higher Speed (FAST_READ) instruction, while an Erase, Program or Write cycle
is in progress, is rejected without having any effects on the cycle that is in progress.
The device is first selected by driving Chip Select
(S) Low. The instruction code for the Read Data
Bytes at Higher Speed (FAST_READ) instruction
is followed by a 3-Byte address (A23-A0) and a
dummy Byte, each bit being latched-in during the
rising edge of Serial Clock (C). Then the memory
contents, at that address, is shifted out on Serial
Data Output (Q), each bit being shifted out, at a
maximum frequency fC, during the falling edge of
Serial Clock (C).
The instruction sequence is shown in Figure 13.
The first Byte addressed can be at any location.
The address is automatically incremented to the
Figure 13. Read Data Bytes at Higher Speed (FAST_READ) Instruction Sequence
and Data-Out Sequence
S
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
C
Instruction
24 BIT ADDRESS
23 22 21
D
3
2
1
0
High Impedance
Q
S
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
C
Dummy Byte
D
7
6
5
4
3
2
1
0
DATA OUT 2
DATA OUT 1
Q
7
MSB
6
5
4
3
2
1
0
7
MSB
6
5
4
3
2
1
0
7
MSB
AI04006
Note: Address bits A23 to A19 are Don’t Care.
19/43
M25PE80
Read Lock Register (RDLR)
bit being shifted out, at a maximum frequency fC,
during the falling edge of Serial Clock (C).
The instruction sequence is shown in Figure 14.
The Read Lock Register (RDLR) instruction is terminated by driving Chip Select (S) High at any
time during data output.
Any Read Lock Register (RDLR) instruction, while
an Erase, Program or Write cycle is in progress, is
rejected without having any effects on the cycle
that is in progress.
The device is first selected by driving Chip Select
(S) Low. The instruction code for the Read Lock
Register (RDLR) instruction is followed by a 3Byte address (A23-A0) pointing to any location inside the concerned sector (or sub-sector). Each
address bit is latched-in during the rising edge of
Serial Clock (C). Then the value of the Lock Register is shifted out on Serial Data Output (Q), each
Table 8. Lock Register Out
Bit
Bit Name
Value
Function
b7-b4
b3
b2
b1
b0
Reserved
‘1’
The Write Lock and Lock Down Bits cannot be changed Once a ‘1’ is
written to the Lock Down Bit it cannot be cleared to ‘0’ except by a
Reset or power-up.
‘0’
The Write Lock and Lock Down Bits can be changed by writing new
values to them. (Default value).
‘1’
Write, Program and Erase operations in this sub-sector will not be
executed. The memory contents will not be changed.
‘0’
Write, Program and Erase operations in this sub-sector are executed
and will modify the sub-sector contents. (Default value).
‘1’
The Write Lock and Lock Down Bits cannot be changed. Once a ‘1’ is
written to the Lock Down Bit it cannot be cleared to ‘0’, except by a
Reset or power-up.
‘0’
The Write Lock and Lock Down Bits can be changed by writing new
values to them. (Default value).
‘1’
Write, Program and Erase operations in this sector will not be
executed. The memory contents will not be changed.
‘0’
Write, Program and Erase operations in this sector are executed and
will modify the sector contents. (Default value).
Sub-sector Lock Down(1)
Sub-sector Write Lock(1)
Sector Lock Down
Sector Write Lock
Note: 1. Valid only for sector 0 and sector 15 (the value ‘0’ is returned for other sectors).
Figure 14. Read Lock Register (RDLR) Instruction Sequence and Data-Out Sequence
S
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
C
Instruction
24-Bit Address
23 22 21
D
3
2
1
0
MSB
Lock Register Out
High Impedance
Q
7
6
5
4
3
2
1
0
MSB
AI10783
20/43
M25PE80
Page Write (PW)
requested addresses without having any effects
on the other Bytes of the same page.
For optimized timings, it is recommended to use
the Page Write (PW) instruction to write all consecutive targeted Bytes in a single sequence versus using several Page Write (PW) sequences
with each containing only a few Bytes
Chip Select (S) must be driven High after the
eighth bit of the last data Byte has been latched in,
otherwise the Page Write (PW) instruction is not
executed.
As soon as Chip Select (S) is driven High, the selftimed Page Write cycle (whose duration is tPW) is
initiated. While the Page Write cycle is in progress,
the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In
Progress (WIP) bit is 1 during the self-timed Page
Write cycle, and is 0 when it is completed. At some
unspecified time before the cycle is complete, the
Write Enable Latch (WEL) bit is reset.
A Page Write (PW) instruction applied to a page
that is Hardware or Software Protected is not executed.
Any Page Write (PW) instruction, while an Erase,
Program or Write cycle is in progress, is rejected
without having any effects on the cycle that is in
progress.
The Page Write (PW) instruction allows Bytes to
be written in the memory. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable
(WREN) instruction has been decoded, the device
sets the Write Enable Latch (WEL).
The Page Write (PW) instruction is entered by
driving Chip Select (S) Low, followed by the instruction code, three address Bytes and at least
one data Byte on Serial Data Input (D). The rest of
the page remains unchanged if no power failure
occurs during this write cycle.
The Page Write (PW) instruction performs a page
erase cycle even if only one Byte is updated.
If the 8 least significant address bits (A7-A0) are
not all zero, all transmitted data exceeding the addressed page boundary roll over, and are written
from the start address of the same page (the one
whose 8 least significant address bits (A7-A0) are
all zero). Chip Select (S) must be driven Low for
the entire duration of the sequence.
The instruction sequence is shown in Figure 15.
If more than 256 Bytes are sent to the device, previously latched data are discarded and the last 256
data Bytes are guaranteed to be written correctly
within the same page. If less than 256 Data Bytes
are sent to device, they are correctly written at the
Figure 15. Page Write (PW) Instruction Sequence
S
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
C
Instruction
24-Bit Address
23 22 21
D
3
2
Data Byte 1
1
0
7
6
5
4
3
2
0
1
MSB
MSB
S
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
C
Data Byte 2
D
7
6
5
4
3
2
Data Byte 3
1
MSB
0
7
MSB
6
5
4
3
2
Data Byte n
1
0
7
6
5
4
3
2
1
0
MSB
AI04045
Note: 1. Address bits A23 to A19 are Don’t Care
2. 1 ≤n ≤256
21/43
M25PE80
Page Program (PP)
For optimized timings, it is recommended to use
the Page Program (PP) instruction to program all
consecutive targeted Bytes in a single sequence
versus using several Page Program (PP) sequences with each containing only a few Bytes
(see Table 16., AC Characteristics).
Chip Select (S) must be driven High after the
eighth bit of the last data Byte has been latched in,
otherwise the Page Program (PP) instruction is not
executed.
As soon as Chip Select (S) is driven High, the selftimed Page Program cycle (whose duration is tPP)
is initiated. While the Page Program cycle is in
progress, the Status Register may be read to
check the value of the Write In Progress (WIP) bit.
The Write In Progress (WIP) bit is 1 during the selftimed Page Program cycle, and is 0 when it is
completed. At some unspecified time before the
cycle is complete, the Write Enable Latch (WEL)
bit is reset.
A Page Program (PP) instruction applied to a page
that is Hardware or software Protected is not executed.
Any Page Program (PP) instruction, while an
Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that
is in progress.
The Page Program (PP) instruction allows Bytes
to be programmed in the memory (changing bits
from 1 to 0, only). Before it can be accepted, a
Write Enable (WREN) instruction must previously
have been executed. After the Write Enable
(WREN) instruction has been decoded, the device
sets the Write Enable Latch (WEL).
The Page Program (PP) instruction is entered by
driving Chip Select (S) Low, followed by the instruction code, three address Bytes and at least
one data Byte on Serial Data Input (D). If the 8
least significant address bits (A7-A0) are not all
zero, all transmitted data exceeding the addressed page boundary roll over, and are programmed from the start address of the same page
(the one whose 8 least significant address bits
(A7-A0) are all zero). Chip Select (S) must be driven Low for the entire duration of the sequence.
The instruction sequence is shown in Figure 16.
If more than 256 Bytes are sent to the device, previously latched data are discarded and the last 256
data Bytes are guaranteed to be programmed correctly within the same page. If less than 256 Data
Bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other Bytes of the same
page.
Figure 16. Page Program (PP) Instruction Sequence
S
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
C
Instruction
24-Bit Address
23 22 21
D
3
2
Data Byte 1
1
0
7
6
5
4
3
2
0
1
MSB
MSB
S
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
C
Data Byte 2
D
7
6
5
4
3
2
MSB
Data Byte 3
1
0
7
MSB
6
5
4
3
2
Data Byte n
1
0
7
6
5
4
3
2
1
0
MSB
AI04044
Note: 1. Address bits A23 to A19 are Don’t Care
2. 1 ≤n ≤256
22/43
M25PE80
Write to Lock Register (WRLR)
The Write to Lock Register (WRLR) instruction allows bits to be changed in the Lock Registers. Before it can be accepted, a Write Enable (WREN)
instruction must previously have been executed.
After the Write Enable (WREN) instruction has
been decoded, the device sets the Write Enable
Latch (WEL).
The Write to Lock Register (WRLR) instruction is
entered by driving Chip Select (S) Low, followed
by the instruction code, three address Bytes
(pointing to any address in the targeted sector/
sub-sector) and one data Byte on Serial Data Input
(D).
The instruction sequence is shown in Figure 17.
Chip Select (S) must be driven High after the
eighth bit of the data Byte has been latched in, otherwise the Write to Lock Register (WRLR) instruction is not executed.
When the Write to Lock Register (WRLR) instruction has been successfully executed, the Write Enable Latch (WEL) bit is reset after a delay time less
than tSHSL minimum value.
Any Write to Lock Register (WRLR) instruction,
while an Erase, Program or Write cycle is in
progress, is rejected without having any effects on
the cycle that is in progress.
Figure 17. Write to Lock Register (WRLR) Instruction Sequence
S
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
C
Instruction
23 22 21
D
Lock Register
In
24-Bit Address
MSB
3
2
1
0
7
6
5
4
3
2
1
0
MSB
AI10784
Table 9. Lock Register In
Sector
All Sectors Except for Sector 0
and Sector 15
Bit
Value
b7-b2
‘0’
b1
Sector Lock Down Bit Value (refer to Table 8.)
b0
Sector Write Lock Bit Value (refer to Table 8.)
‘1’
Only b3 and b2 are taken into account to modify the subsector Write Lock and Lock Down bits(1)
‘0’
Only b1 and b0 are taken into account to modify the sector
Write Lock and Lock Down bits(2)
b7
Sector 0
Sector 15
b3
Sub-sector Lock Down Bit value (refer to Table 8.)
b2
Sub-sector Write Lock Bit Value (refer to Table 8.)
b1
Sector Lock Down Bit Value (refer to Table 8.)
b0
Sector Write Lock Bit Value (refer to Table 8.)
Note: 1. b6-b4 and b1-b0 must be reset to ‘0’.
2. b6-b2 must be reset to ‘0’.
23/43
M25PE80
Protection always prevails:
■
When the Lock Down Bit of Sector 0 or Sector
15 is set to ‘1’.
– If the Lock Down Bit of Sector 0 is ‘1’, all
the Lock Down Bits of the sub-sectors in
Sector 0 are forced to ‘1’.
– If the Lock Down Bit of Sector 15 is ‘1’, all
the Lock Down Bits of the sub-sectors in
Sector 15 are forced to ‘1’
■
When the Write Lock Bit of Sector 0 or Sector
15 is set to ‘1’.
– if the Write Lock Bit of Sector 0 is ‘1’, the
Write Lock Bits of all the sub-sectors in
Sector 0 are forced to ‘1’ (even if their
Lock Down Bits are set to ‘1’).
– if the Write Lock Bit of Sector 15 is ‘1’, the
Write Lock Bits of all the sub-sectors in
Sector 15 are forced to ‘1’ (even if their
Lock Down Bits are set to ‘1’).
■
When the Write Lock Bit of Sector 0 or Sector
15 is reset to ‘0’.
– if the Write Lock Bit of Sector 0 is ‘0’, all
the sub-sectors in Sector 0 whose Lock
24/43
Down Bit is ‘0’ have their Write Lock Bits
forced to ‘0’.
– if the Write Lock Bit of Sector 15 is ‘0’, all
the sub-sectors in Sector 15 whose Lock
Down Bit is ‘0’ have their Write Lock Bits
forced to ‘0’.
■
When the Write Lock Bit of any sector or subsector is set to ‘1’, any instruction that may
modify the contents of this sector or subsector will be rejected (including Sector Erase
and Bulk Erase).
Note that when the WRLR instruction acts both on
Write Lock (WL) and Lock Down (LD) bits, it firstly
programs the WL bit, and then the LD bit.
As an example, if a sub-sector Lock Register settings are xxxx0101b and a WRLR instruction is issued with a Lock Register In data set to
00000010b:
1. the sector WL bit is first set to ‘0’ (and all subsectors that are not locked-down will have
their WL bit reset to ‘0’).
2. the sector LD bit and all sub-sectors LD bits
are set to ‘1’.
In this case, the final value of the above sub-sector
Lock Register is xxxx1010b.
M25PE80
Page Erase (PE)
tion is not executed. As soon as Chip Select (S) is
driven High, the self-timed Page Erase cycle
(whose duration is tPE) is initiated. While the Page
Erase cycle is in progress, the Status Register
may be read to check the value of the Write In
Progress (WIP) bit. The Write In Progress (WIP)
bit is 1 during the self-timed Page Erase cycle, and
is 0 when it is completed. At some unspecified
time before the cycle is complete, the Write Enable
Latch (WEL) bit is reset.
A Page Erase (PE) instruction applied to a page
that is Hardware or software Protected is not executed.
Any Page Erase (PE) instruction, while an Erase,
Program or Write cycle is in progress, is rejected
without having any effects on the cycle that is in
progress.
The Page Erase (PE) instruction sets to 1 (FFh) all
bits inside the chosen page. Before it can be accepted, a Write Enable (WREN) instruction must
previously have been executed. After the Write
Enable (WREN) instruction has been decoded,
the device sets the Write Enable Latch (WEL).
The Page Erase (PE) instruction is entered by
driving Chip Select (S) Low, followed by the instruction code, and three address Bytes on Serial
Data Input (D). Any address inside the Page is a
valid address for the Page Erase (PE) instruction.
Chip Select (S) must be driven Low for the entire
duration of the sequence.
The instruction sequence is shown in Figure 18..
Chip Select (S) must be driven High after the
eighth bit of the last address Byte has been
latched in, otherwise the Page Erase (PE) instrucFigure 18. Page Erase (PE) Instruction Sequence
S
0
1
2
3
4
5
6
7
8
9
29 30 31
C
Instruction
D
24 Bit Address
23 22
2
1
0
MSB
AI04046
Note: Address bits A23 to A19 are Don’t Care.
25/43
M25PE80
Sector Erase (SE)
struction is not executed. As soon as Chip Select
(S) is driven High, the self-timed Sector Erase cycle (whose duration is tSE) is initiated. While the
Sector Erase cycle is in progress, the Status Register may be read to check the value of the Write
In Progress (WIP) bit. The Write In Progress (WIP)
bit is 1 during the self-timed Sector Erase cycle,
and is 0 when it is completed. At some unspecified
time before the cycle is complete, the Write Enable
Latch (WEL) bit is reset.
A Sector Erase (SE) instruction applied to a sector
that contains a page that is Hardware or software
Protected is not executed.
Any Sector Erase (SE) instruction, while an Erase,
Program or Write cycle is in progress, is rejected
without having any effects on the cycle that is in
progress.
The Sector Erase (SE) instruction sets to 1 (FFh)
all bits inside the chosen sector. Before it can be
accepted, a Write Enable (WREN) instruction
must previously have been executed. After the
Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL).
The Sector Erase (SE) instruction is entered by
driving Chip Select (S) Low, followed by the instruction code, and three address Bytes on Serial
Data Input (D). Any address inside the Sector (see
Table 5.) is a valid address for the Sector Erase
(SE) instruction. Chip Select (S) must be driven
Low for the entire duration of the sequence.
The instruction sequence is shown in Figure 19..
Chip Select (S) must be driven High after the
eighth bit of the last address Byte has been
latched in, otherwise the Sector Erase (SE) inFigure 19. Sector Erase (SE) Instruction Sequence
S
0
1
2
3
4
5
6
7
8
9
29 30 31
C
Instruction
D
24 Bit Address
23 22
2
1
0
MSB
AI03751D
Note: Address bits A23 to A19 are Don’t Care.
26/43
M25PE80
Bulk Erase (BE)
cuted. As soon as Chip Select (S) is driven High,
the self-timed Bulk Erase cycle (whose duration is
tBE) is initiated. While the Bulk Erase cycle is in
progress, the Status Register may be read to
check the value of the Write In Progress (WIP) bit.
The Write In Progress (WIP) bit is 1 during the selftimed Bulk Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle
is completed, the Write Enable Latch (WEL) bit is
reset.
Any Bulk Erase (BE) instruction, while an Erase,
Program or Write cycle is in progress, is rejected
without having any effects on the cycle that is in
progress. A Bulk Erase (BE) instruction is ignored
if at least one sector or sub-sector is write-protected (Hardware or Software protection).
The Bulk Erase (BE) instruction sets all bits to 1
(FFh). Before it can be accepted, a Write Enable
(WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction
has been decoded, the device sets the Write Enable Latch (WEL).
The Bulk Erase (BE) instruction is entered by driving Chip Select (S) Low, followed by the instruction
code on Serial Data Input (D). Chip Select (S)
must be driven Low for the entire duration of the
sequence.
The instruction sequence is shown in Figure 20.
Chip Select (S) must be driven High after the
eighth bit of the instruction code has been latched
in, otherwise the Bulk Erase instruction is not exeFigure 20. Bulk Erase (BE) Instruction Sequence
S
0
1
2
3
4
5
6
7
C
Instruction
D
AI03752D
27/43
M25PE80
Deep Power-down (DP)
Executing the Deep Power-down (DP) instruction
is the only way to put the device in the lowest consumption mode (the Deep Power-down mode). It
can also be used as an extra software protection
mechanism, while the device is not in active use,
since in this mode, the device ignores all Write,
Program and Erase instructions.
Driving Chip Select (S) High deselects the device,
and puts the device in the Standby mode (if there
is no internal cycle currently in progress). But this
mode is not the Deep Power-down mode. The
Deep Power-down mode can only be entered by
executing the Deep Power-down (DP) instruction,
subsequently reducing the standby current (from
ICC1 to ICC2, as specified in Table 15.).
Once the device has entered the Deep Powerdown mode, all instructions are ignored except the
Release from Deep Power-down (RDP) instruction. Issuing the Release from Deep Power-down
(RDP) instruction will cause the device to exit the
Deep Power-down mode.
The Deep Power-down mode automatically stops
at Power-down, and the device always Powers-up
in the Standby mode.
The Deep Power-down (DP) instruction is entered
by driving Chip Select (S) Low, followed by the instruction code on Serial Data Input (D). Chip Select (S) must be driven Low for the entire duration
of the sequence.
The instruction sequence is shown in Figure 21..
Chip Select (S) must be driven High after the
eighth bit of the instruction code has been latched
in, otherwise the Deep Power-down (DP) instruction is not executed. As soon as Chip Select (S) is
driven High, it requires a delay of tDP before the
supply current is reduced to ICC2 and the Deep
Power-down mode is entered.
Any Deep Power-down (DP) instruction, while an
Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that
is in progress.
Figure 21. Deep Power-down (DP) Instruction Sequence
S
0
1
2
3
4
5
6
7
tDP
C
Instruction
D
Stand-by Mode
28/43
Deep Power-down Mode
AI03753D
M25PE80
Release from Deep Power-down (RDP)
Once the device has entered the Deep Powerdown mode, all instructions are ignored except the
Release from Deep Power-down (RDP) instruction. Executing this instruction takes the device out
of the Deep Power-down mode.
The Release from Deep Power-down (RDP) instruction is entered by driving Chip Select (S) Low,
followed by the instruction code on Serial Data Input (D). Chip Select (S) must be driven Low for the
entire duration of the sequence.
The instruction sequence is shown in Figure 22..
The Release from Deep Power-down (RDP) instruction is terminated by driving Chip Select (S)
High. Sending additional clock cycles on Serial
Clock (C), while Chip Select (S) is driven Low,
cause the instruction to be rejected, and not executed.
After Chip Select (S) has been driven High, followed by a delay, tRDP, the device is put in the
Standby mode. Chip Select (S) must remain High
at least until this period is over. The device waits
to be selected, so that it can receive, decode and
execute instructions.
Any Release from Deep Power-down (RDP) instruction, while an Erase, Program or Write cycle
is in progress, is rejected without having any effects on the cycle that is in progress.
Figure 22. Release from Deep Power-down (RDP) Instruction Sequence
S
0
1
2
3
4
5
6
7
tRDP
C
Instruction
D
High Impedance
Q
Deep Power-down Mode
Stand-by Mode
AI06807
29/43
M25PE80
POWER-UP AND POWER-DOWN
At Power-up and Power-down, the device must
not be selected (that is Chip Select (S) must follow
the voltage applied on VCC) until VCC reaches the
correct value:
– VCC(min) at Power-up, and then for a further
delay of tVSL
– VSS at Power-down
Usually a simple pull-up resistor on Chip Select (S)
can be used to ensure safe and proper Power-up
and Power-down.
To avoid data corruption and inadvertent write operations during power-up, a Power On Reset
(POR) circuit is included. The logic inside the device is held reset while VCC is less than the Power
On Reset (POR) threshold voltage, VWI – all operations are disabled, and the device does not respond to any instruction.
Moreover, the device ignores all Write Enable
(WREN), Page Write (PW), Page Program (PP),
Page Erase (PE), Sector Erase (SE), Bulk Erase
(BE) and Write to Lock Register (WRLR) instructions until a time delay of tPUW has elapsed after
the moment that VCC rises above the VWI threshold. However, the correct operation of the device
is not guaranteed if, by this time, VCC is still below
VCC(min). No Write, Program or Erase instructions
should be sent until the later of:
– tPUW after VCC passed the VWI threshold
– tVSL after VCC passed the VCC(min) level
These values are specified in Table 10..
If the delay, tVSL, has elapsed, after VCC has risen
above VCC(min), the device can be selected for
READ instructions even if the tPUW delay is not yet
fully elapsed.
As an extra protection, the Reset (Reset) signal
could be driven Low for the whole duration of the
Power-up and Power-down phases.
At Power-up, the device is in the following state:
– The device is in the Standby mode (not the
Deep Power-down mode).
– The Write Enable Latch (WEL) bit is reset.
Normal precautions must be taken for supply rail
decoupling, to stabilize the VCC supply. Each device in a system should have the VCC rail decoupled by a suitable capacitor close to the package
pins. (Generally, this capacitor is of the order of
0.1µF).
At Power-down, when VCC drops from the operating voltage, to below the Power On Reset (POR)
threshold voltage, VWI, all operations are disabled
and the device does not respond to any instruction. (The designer needs to be aware that if a
Power-down occurs while a Write, Program or
Erase cycle is in progress, some data corruption
can result.)
Figure 23. Power-up Timing
VCC
VCC(max)
Program, Erase and Write Commands are Rejected by the Device
Chip Selection Not Allowed
VCC(min)
Reset State
of the
Device
tVSL
Read Access allowed
Device fully
accessible
VWI
tPUW
time
30/43
AI04009C
M25PE80
Table 10. Power-Up Timing and VWI Threshold
Symbol
1
Parameter
Min.
Max.
Unit
VCC(min) to S low
30
tPUW1
Time delay before the first Write, Program or Erase instruction
1
10
ms
VWI1
Write Inhibit Voltage
1.5
2.5
V
tVSL
µs
Note: 1. These parameters are characterized only, over the temperature range –40°C to +85°C.
INITIAL DELIVERY STATE
The device is delivered with the memory array
erased: all bits are set to 1 (each Byte contains
FFh). All usable Status Register bits are 0.
31/43
M25PE80
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings table may cause permanent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions above those indicated in the
Operating sections of this specification is not im-
plied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality documents.
Table 11. Absolute Maximum Ratings
Symbol
Parameter
TSTG
Storage Temperature
TLEAD
Lead Temperature during Soldering
Min.
Max.
Unit
–65
150
°C
See note 1
°C
VIO
Input and Output Voltage (with respect to Ground)
–0.6
4.0
V
VCC
Supply Voltage
–0.6
4.0
V
VESD
Electrostatic Discharge Voltage (Human Body model) 2
–2000
2000
V
Note: 1. Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the ST ECOPACK® 7191395 specification, and
the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU
2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω)
32/43
M25PE80
DC AND AC PARAMETERS
This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC
and AC Characteristic tables that follow are derived from tests performed under the Measure-
ment Conditions summarized in the relevant
tables. Designers should check that the operating
conditions in their circuit match the measurement
conditions when relying on the quoted parameters.
Table 12. Operating Conditions
Symbol
VCC
TA
Parameter
Min.
Max.
Unit
Supply Voltage
2.7
3.6
V
Ambient Operating Temperature
–40
85
°C
Min.
Max.
Unit
Table 13. AC Measurement Conditions
Symbol
CL
Parameter
Load Capacitance
30
Input Rise and Fall Times
pF
5
ns
Input Pulse Voltages
0.2VCC to 0.8VCC
V
Input and Output Timing Reference Voltages
0.3VCC to 0.7VCC
V
Note: Output Hi-Z is defined as the point where data out is no longer driven.
Figure 24. AC Measurement I/O Waveform
Input Levels
Input and Output
Timing Reference Levels
0.8VCC
0.7VCC
0.3VCC
0.2VCC
AI00825B
Table 14. Capacitance
Symbol
COUT
CIN
Parameter
Output Capacitance (Q)
Input Capacitance (other pins)
Test Condition
Min.
Max.
Unit
VOUT = 0V
8
pF
VIN = 0V
6
pF
Note: Sampled only, not 100% tested, at TA=25°C and a frequency of 20 MHz.
33/43
M25PE80
Table 15. DC Characteristics
Symbol
Parameter
Test Condition
(in addition to those in Table 12.)
Min.
Max.
Unit
ILI
Input Leakage Current
±2
µA
ILO
Output Leakage Current
±2
µA
ICC1
Standby Current
(Standby and Reset modes)
S = VCC, VIN = VSS or VCC
50
µA
ICC2
Deep Power-down Current
S = VCC, VIN = VSS or VCC
10
µA
ICC3
Operating Current (FAST_READ)
C = 0.1VCC / 0.9.VCC at 50MHz,
Q = open
6
mA
ICC4
Operating Current (PW)
S = VCC
15
mA
ICC5
Operating Current (SE)
S = VCC
15
mA
VIL
Input Low Voltage
– 0.5
0.3VCC
V
VIH
Input High Voltage
0.7VCC
VCC+0.4
V
VOL
Output Low Voltage
IOL = 1.6 mA
0.4
V
VOH
Output High Voltage
IOH = –100 µA
34/43
VCC–0.2
V
M25PE80
Table 16. AC Characteristics
Test conditions specified in Table 12. and Table 13.
Symbol
fC
Alt.
Parameter
Min.
fC
Clock Frequency for the following
instructions: FAST_READ, RDLR, PW,
PP, WRLR, PE, SE, DP, RDP, WREN,
WRDI, RDSR
Clock Frequency for READ
instructions
fR
Typ.
Max.
Unit
D.C.
50
MHz
D.C.
20
MHz
tCH (1)
tCLH
Clock High Time
9
ns
tCL (1)
tCLL
Clock Low Time
9
ns
0.1
V/ns
S Active Setup Time (relative to C)
9
ns
S Not Active Hold Time (relative to C)
9
ns
Clock Slew Rate 2 (peak to peak)
tSLCH
tCSS
tCHSL
tDVCH
tDSU
Data In Setup Time
2
ns
tCHDX
tDH
Data In Hold Time
5
ns
tCHSH
S Active Hold Time (relative to C)
9
ns
tSHCH
S Not Active Setup Time (relative to C)
9
ns
100
ns
tSHSL
tCSH
S Deselect Time
tSHQZ (2)
tDIS
Output Disable Time
8
ns
tCLQV
tV
Clock Low to Output Valid
8
ns
tCLQX
tHO
Output Hold Time
0
ns
tTHSL
Top Sector Lock Setup Time
50
ns
tSHTL
Top Sector Lock Hold Time
100
ns
tDP (2)
S to Deep Power-down
3
µs
tRDP (2)
S High to Standby Mode
30
µs
25
ms
0.4 +
n * 0.8/256
5
ms
Page Write Cycle Time (256 Bytes)
tPW (3)
Page Write Cycle Time (n Bytes)
Page Program Cycle Time (256 Bytes)
tPP (3)
Page Program Cycle Time (n Bytes)
11
10.2 +
n * 0.8/256
1.2
tPE
Page Erase Cycle Time
10
20
ms
tSE
Sector Erase Cycle Time
1
5
s
tBE
Bulk Erase Cycle Time
16
60
s
Note: 1. tCH + tCL must be greater than or equal to 1/ fC
2. Value guaranteed by characterization, not 100% tested in production.
3. When using PP and PW instructions to update consecutive Bytes, optimized timings are obtained with one sequence including all
the Bytes versus several sequences of only a few Bytes.
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M25PE80
Figure 25. Serial Input Timing
tSHSL
S
tCHSL
tSLCH
tCHSH
tSHCH
C
tDVCH
tCHCL
tCHDX
D
Q
MSB IN
tCLCH
LSB IN
High Impedance
AI01447C
Figure 26. Top Sector Lock Setup and Hold Timing
TSL
tSHTL
tTHSL
S
C
D
High Impedance
Q
AI07439b
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M25PE80
Figure 27. Output Timing
S
tCH
C
tCLQV
tCLQX
tCLQV
tCL
tSHQZ
tCLQX
LSB OUT
Q
tQLQH
tQHQL
D
ADDR.LSB IN
AI01449e
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M25PE80
Table 17. Reset Timings
Test conditions specified in Table 12. and Table 13.
Symbol
Alt.
tRLRH (1)
tRST
tRHSL
tREC
Parameter
Min.
Reset Pulse Width
Reset Recovery Time
Chip Select High to
Reset High
tSHRH
Conditions
Typ.
Max.
10
µs
after any operation except
for PW, PP, PE, SE and BE
30
µs
After PW, PP, PE, SE and
BE operations(1)
300
µs
Chip should have been
deselected before Reset is
de-asserted
10
ns
Note: 1. Value guaranteed by characterization, not 100% tested in production.
Figure 28. Reset AC Waveforms
S
tSHRH
Reset
tRHSL
tRLRH
AI06808
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Unit
M25PE80
PACKAGE MECHANICAL
Figure 29. MLP8, 8-lead Very thin Dual Flat Package No lead, 6x5mm, Package Outline
D
D1
E E1
E2
e
b
θ
A
D2
A2
L
A1 A3
VDFPN-01
Note: Drawing is not to scale.
Table 18. MLP8, 8-lead Very thin Dual Flat Package No lead, 6x5mm,
Package Mechanical Data
millimeters
inches
Symbol
Typ.
A
Min.
0.85
A1
0.00
Max.
Typ.
1.00
0.0335
0.05
A2
0.65
0.0256
A3
0.20
0.0079
b
0.40
D
6.00
0.2362
D1
5.75
0.2264
D2
3.40
E
5.00
0.1969
E1
4.75
0.1870
E2
4.00
e
1.27
L
0.60
θ
0.35
3.20
3.80
0.48
3.60
4.20
0.0157
0.1339
0.1575
Min.
Max.
0.0394
0.0000
0.0020
0.0138
0.0189
0.1260
0.1417
0.1496
0.1654
0.0197
0.0295
0.0500
0.50
0.75
12°
0.0236
12°
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M25PE80
Figure 30. SO8 wide – 8 lead Plastic Small Outline, 208 mils body width, Package Outline
A2
A
C
B
CP
e
D
N
E
H
1
A1
α
L
SO-b
Note: Drawing is not to scale.
Table 19. SO8 wide – 8 lead Plastic Small Outline, 208 mils body width, Mechanical Data
millimeters
inches
Symbol
Typ
Min
A
0.10
A2
Min
0.25
0.20
0.35
0.45
–
–
CP
Max
0.080
0.004
1.78
B
0.010
0.070
0.008
0.014
0.018
–
–
0.10
0.004
D
5.15
5.35
0.203
0.211
E
5.20
5.40
0.205
0.213
–
–
–
–
H
7.70
8.10
0.303
0.319
L
0.50
0.80
0.020
0.031
a
0
10
0
10
e
N
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Typ
2.03
A1
C
Max
1.27
8
0.050
8
M25PE80
PART NUMBERING
Table 20. Ordering Information Scheme
Example:
M25PE80
–
V MP
6
T
P
Device Type
M25PE = Page-Erasable Serial Flash Memory
Device Function
80 = 8Mbit (1Mb x 8)
Operating Voltage
V = VCC = 2.7 to 3.6V
Package
MW = SO8 (208 mils width)
MP = VDFPN8 6x5mm (MLP8)
Device Grade
6 = Industrial: device tested with standard test flow over –40 to 85 °C
Option
blank = Standard Packing
T = Tape and Reel Packing
Plating Technology
blank = Standard SnPb plating
P or G = RoHS compliant
For a list of available options (speed, package, etc.) or for further information on any aspect of this device,
please contact your nearest ST Sales Office.
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M25PE80
REVISION HISTORY
Table 21. Document Revision History
Date
Version
24-Nov-2004
0.1
First Issue.
07-Dec-2004
0.2
4KB Software protection granularity extended to Sector 15.
0.3
SO16W package removed, SO8W package added.
End timing line of tSHQZ modified in Figure 27., Output Timing. Plating Technology
options modified in Table 20., Ordering Information Scheme. Minor text changes.
Tables 3 and 4 and Figure 6. for details on the software protection scheme.
25-Jul-2005
0.4
Lock Register programming sequence detailed in Section Write to Lock Register
(WRLR).
Sections An Easy Way to Modify Data, A Fast Way to Modify Data, Page Write (PW)
and Page Program (PP), updated to explain when using Page Write and Page
Program instructions.
Bulk Erase cycle time (tBE), Page Write cycle time (tPW) and Page Program cycle time
(tPP) updated in Table 16., AC Characteristics.
24-Aug-2005
1.0
Version number updated for internet. No document changes.
25-Aug-2005
2.0
Document status updated to Preliminary Data.
10-May-2005
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Description of Revision
M25PE80
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
ECOPACK is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2005 STMicroelectronics - All rights reserved
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