STMICROELECTRONICS M27V322

M27V322
32 Mbit (2Mb x16) Low Voltage UV EPROM and OTP EPROM
■
3.3V ± 10% SUPPLY VOLTAGE in READ
OPERATION
■
READ ACCESS TIME
– 100ns at VCC = 3.0V to 3.6V
■
PIN COMPATIBLE WITH M27C322
■
WORD-WIDE CONFIGURABLE
■
32 Mbit MASK ROM REPLACEMENT
■
LOW POWER CONSUMPTION
42
42
1
– Active Current 30mA at 5MHz
1
FDIP42W (F)
PDIP42 (P)
– Stand-by Current 60µA
■
PROGRAMMING VOLTAGE: 12V ± 0.25V
■
PROGRAMMING TIME: 50µs/word
■
ELECTRONIC SIGNATURE
Figure 1. Logic Diagram
– Manufacturer Code: 0020h
– Device Code: 0034h
DESCRIPTION
The M27V322 is a 32 Mbit EPROM offered in the
UV range (ultra violet erase) and OTP range. It is
ideally suited for microprocessor systems requiring large data or program storage. It is organised
as 2 MWords of 16 bit. The pin-out is compatible
with a 32 Mbit Mask ROM.
The FDIP42W (window ceramic frit-seal package)
has a transparent lid which allows the user to expose the chip to ultraviolet light to erase the bit pattern. A new pattern can then be written rapidly to
the device by following the programming procedure.
For applications where the content is programmed
only one time and erasure is not required, the
M27V322 is offered in PDIP42 package.
VCC
21
16
A0-A20
E
Q0-Q15
M27V322
GVPP
VSS
AI03050
March 2000
1/13
M27V322
Table 1. Signal Names
Figure 2A. DIP Connections
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
E
VSS
GVPP
Q0
Q8
Q1
Q9
Q2
Q10
Q3
Q11
1
42
2
41
3
40
4
39
5
38
6
37
7
36
35
8
9
34
10
33
M27V322
32
11
31
12
30
13
29
14
28
15
27
16
17
26
18
25
19
24
20
23
22
21
A19
A8
A9
A10
A11
A12
A13
A14
A15
A16
A20
VSS
Q15
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
AI03051
DEVICE OPERATION
The operating modes of the M27V322 are listed in
the Operating Modes Table. A single power supply
is required in the read mode. All inputs are TTL
compatible except for V PP and 12V on A9 for the
Electronic Signature.
Read Mode
The M27V322 has a word-wide organization. Chip
Enable (E) is the power control and should be
used for device selection. Output Enable (G) is the
output control and should be used to gate data to
the output pins independent of device selection.
Assuming that the addresses are stable, the address access time (tAVQV) is equal to the delay
2/13
A0-A20
Address Inputs
Q0-Q15
Data Outputs
E
Chip Enable
GVPP
Output Enable / Program Supply
VCC
Supply Voltage
VSS
Ground
from E to output (tELQV). Data is available at the
output after a delay of t GLQV from the falling edge
of GVPP, assuming that E has been low and the
addresses have been stable for at least tAVQVtGLQV.
Standby Mode
The M27V322 has a standby mode which reduces
the supply current from 30mA to 30µA. The
M27V322 is placed in the standby mode by applying a CMOS high signal to the E input.When in the
standby mode, the outputs are in a high impedance state, independent of the GVPP input.
Two Line Output Control
Because EPROMs are usually used in larger
memory arrays, this product features a 2 line control function which accommodates the use of multiple memory connection. The two line control
function allows:
a. the lowest possible memory power dissipation,
b. complete assurance that output bus contention
will not occur.
For the most efficient use of these two control
lines, E should be decoded and used as the primary device selecting function, while GVPP should be
made a common connection to all devices in the
array and connected to the READ line from the
system control bus. This ensures that all deselected memory devices are in their low power standby
mode and that the output pins are only active
when data is required from a particular memory
device.
M27V322
Table 2. Absolute Maximum Ratings (1)
Symbol
Parameter
Value
Unit
Ambient Operating Temperature (3)
–40 to 125
°C
TBIAS
Temperature Under Bias
–50 to 125
°C
TSTG
Storage Temperature
–65 to 150
°C
VIO (2)
Input or Output Voltage (except A9)
–2 to 7
V
Supply Voltage
–2 to 7
V
–2 to 13.5
V
–2 to 14
V
TA
VCC
VA9 (2)
A9 Voltage
VPP
Program Supply Voltage
Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC
voltage on Output is V CC +0.5V with possible overshoot to VCC +2V for a period less than 20ns.
3. Depends on range.
Table 3. Operating Modes
E
GVPP
A9
Q15-Q0
Read
VIL
VIL
X
Data Out
Output Disable
VIL
VIH
X
Hi-Z
VIL Pulse
VPP
X
Data In
Program Inhibit
VIH
VPP
X
Hi-Z
Standby
VIH
X
X
Hi-Z
Electronic Signature
VIL
VIL
VID
Codes
Mode
Program
Note: X = VIH or VIL, V ID = 12V ± 0.5V.
Table 4. Electronic Signature
Identifier
A0
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
Hex Data
Manufacturer’s Code
VIL
0
0
1
0
0
0
0
0
20h
Device Code
VIH
0
0
1
1
0
1
0
0
34h
Note: Outputs Q15-Q8 are set to '0'.
3/13
M27V322
Table 5. AC Measurement Conditions
High Speed
Standard
Input Rise and Fall Times
≤ 10ns
≤ 20ns
Input Pulse Voltages
0 to 3V
0.4V to 2.4V
1.5V
0.8V and 2V
Input and Output Timing Ref. Voltages
Figure 3. AC Testing Input Output Waveform
Figure 4. AC Testing Load Circuit
1.3V
High Speed
1N914
3V
1.5V
3.3kΩ
0V
DEVICE
UNDER
TEST
Standard
2.4V
OUT
CL
2.0V
0.8V
0.4V
CL = 30pF for High Speed
AI01822
CL = 100pF for Standard
CL includes JIG capacitance
AI01823B
Table 6. Capacitance (1) (TA = 25 °C, f = 1 MHz)
Symbol
CIN
COUT
Parameter
Input Capacitance
Output Capacitance
Test Condition
Min
Max
Unit
VIN = 0V
10
pF
VOUT = 0V
12
pF
Note: 1. Sampled only, not 100% tested.
System Considerations
The power switching characteristics of Advanced
CMOS EPROMs require careful decoupling of the
supplies to the devices. The supply current ICC
has three segments of importance to the system
designer: the standby current, the active current
and the transient peaks that are produced by the
falling and rising edges of E. The magnitude of the
transient current peaks is dependent on the capacitive and inductive loading of the device outputs. The associated transient voltage peaks can
be suppressed by complying with the two line out-
4/13
put control and by properly selected decoupling
capacitors. It is recommended that a 0.1µF ceramic capacitor is used on every device between V CC
and VSS. This should be a high frequency type of
low inherent inductance and should be placed as
close as possible to the device. In addition, a
4.7µF electrolytic capacitor should be used between V CC and VSS for every eight devices. This
capacitor should be mounted near the power supply connection point. The purpose of this capacitor
is to overcome the voltage drop caused by the inductive effects of PCB traces.
M27V322
Table 7. Read Mode DC Characteristics (1)
(TA = –40 to 85 °C or 0 to 70 °C; VCC = 3.3V ± 10%; VPP = V CC)
Symbol
Parameter
Test Condition
ILI
Input Leakage Current
ILO
Output Leakage Current
ICC
Supply Current
ICC1
Supply Current (Standby) TTL
ICC2
Supply Current (Standby) CMOS
Min
Max
Unit
0V ≤ VIN ≤ VCC
±1
µA
0V ≤ VOUT ≤ VCC
±10
µA
E = VIL, GVPP = VIL, IOUT = 0mA,
f = 5MHz
30
mA
E = VIH
1
mA
E > VCC – 0.2V
60
µA
VPP = VCC
10
µA
IPP
Program Current
VIL
Input Low Voltage
–0.6
0.2VCC
V
VIH (2)
Input High Voltage
0.7VCC
VCC + 0.5
V
VOL
Output Low Voltage
0.4
V
VOH
Output High Voltage TTL
IOL = 2.1mA
IOH = –400µA
2.4
V
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V PP.
2. Maximum DC voltage on Output is VCC +0.5V.
Table 8. Read Mode AC Characteristics (1)
(TA = –40 to 85 °C or 0 to 70 °C; VCC = 3.3V ± 10%; VPP = V CC)
M27V322
Symbol
Alt
Parameter
Test Condition
-100 (3)
Min
Max
-150
-120
Min
Max
Min
Unit
Max
E = VIL, G = VIL
100
120
150
ns
Chip Enable Low to Output Valid
G = VIL
100
120
150
ns
tOE
Output Enable Low to Output
Valid
E = VIL
50
60
60
ns
tEHQZ (2)
tDF
Chip Enable High to Output Hi-Z
G = VIL
0
45
0
50
0
50
ns
tGHQZ (2)
tDF
Output Enable High to Output
Hi-Z
E = VIL
0
45
0
50
0
50
ns
tAXQX
tOH
Address Transition to Output
Transition
E = VIL, G = VIL
5
tAVQV
tACC
Address Valid to Output Valid
tELQV
tCE
tGLQV
5
5
ns
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V PP
2. Sampled only, not 100% tested.
3. Speed obtained with High Speed measurement conditions.
5/13
M27V322
Figure 5. Read Mode AC Waveforms
VALID
A0-A20
VALID
tAVQV
tAXQX
E
tEHQZ
tGLQV
GVPP
tGHQZ
tELQV
Hi-Z
Q0-Q15
AI02207
Table 9. Programming Mode DC Characteristics (1)
(TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12V ± 0.25V)
Symbol
Parameter
Test Condition
ILI
Input Leakage Current
VIL ≤ VIN ≤ VIH
ICC
Supply Current
IPP
Program Current
VIL
Input Low Voltage
VIH
Input High Voltage
VOL
Output Low Voltage
VOH
Output High Voltage TTL
VID
A9 Voltage
Min
Max
Unit
±10
µA
50
mA
50
mA
–0.3
0.8
V
2.4
VCC + 0.5
V
0.4
V
E = VIL
IOL = 2.1mA
IOH = –2.5mA
3.5
11.5
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V PP.
6/13
V
12.5
V
M27V322
Table 10. MARGIN MODE AC Characteristics (1)
(TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12V ± 0.25V)
Symbol
Alt
Parameter
Test Condition
Min
Max
Unit
tA9HVPH
tAS9
VA9 High to VPP High
2
µs
tVPHEL
tVPS
VPP High to Chip Enable Low
2
µs
tA10HEH
tAS10
VA10 High to Chip Enable High (Set)
1
µs
tA10LEH
tAS10
VA10 Low to Chip Enable High (Reset)
1
µs
tEXA10X
tAH10
Chip Enable Transition to VA10 Transition
1
µs
tEXVPX
tVPH
Chip Enable Transition to VPP Transition
2
µs
tVPXA9X
tAH9
VPP Transition to VA9 Transition
2
µs
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V PP.
Table 11. Programming Mode AC Characteristics (1)
(TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12V ± 0.25V)
Symbol
Alt
Parameter
Test Condition
Min
Max
tAVEL
tAS
Address Valid to Chip Enable Low
1
µs
tQVEL
tDS
Input Valid to Chip Enable Low
1
µs
tVCHEL
tVCS
VCC High to Chip Enable Low
2
µs
tVPHEL
tOES
VPP High to Chip Enable Low
1
µs
tVPLVPH
tPRT
VPP Rise Time
50
ns
tELEH
tPW
Chip Enable Program Pulse Width (Initial)
45
tEHQX
tDH
Chip Enable High to Input Transition
2
µs
tEHVPX
tOEH
Chip Enable High to VPP Transition
2
µs
tVPLEL
tVR
VPP Low to Chip Enable Low
1
µs
tELQV
tDV
Chip Enable Low to Output Valid
tEHQZ (2)
tDFP
Chip Enable High to Output Hi-Z
0
tEHAX
tAH
Chip Enable High to Address Transition
0
55
Unit
µs
1
µs
130
ns
ns
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V PP.
2. Sampled only, not 100% tested.
Programming
When delivered (and after each erasure for UV
EPROM), all bits of the M27V322 are in the "1"
state. Data is introduced by selectively programming "0"s into the desired bit locations. Although
only "0"s will be programmed, both "1"s and "0"s
can be present in the data word. The only way to
change a "0" to a "1" is by die exposition to ultravi-
olet light (UV EPROM). The M27V322 is in the
programming mode when V PP input is at 12.V,
GVPP is at VIH and E is pulsed to VIL. The data to
be programmed is applied to 16 bits in parallel to
the data output pins. The levels required for the
address and data inputs are TTL. VCC is specified
to be 6.25V ± 0.25V.
7/13
M27V322
Figure 6. MARGIN MODE AC Waveforms
VCC
A8
A9
tA9HVPH
tVPXA9X
GVPP
tVPHEL
tEXVPX
E
tA10HEH
tEXA10X
A10 Set
A10 Reset
tA10LEH
AI00736B
Note: A8 High level = 5V; A9 High level = 12V.
Figure 7. Programming and Verify Modes AC Waveforms
VALID
A0-A20
tAVEL
Q0-Q15
tEHAX
DATA IN
DATA OUT
tQVEL
tEHQX
tEHQZ
VCC
tVCHEL
tEHVPX
tELQV
GVPP
tVPHEL
tVPLEL
E
tELEH
PROGRAM
VERIFY
AI02205
Note: BYTE = V IH.
8/13
M27V322
Figure 8. Programming Flowchart
VCC = 6.25V, VPP = 12V
SET MARGIN MODE
n=0
E = 50µs Pulse
NO
++n
= 25
YES
FAIL
NO
++ Addr
VERIFY
YES
Last
Addr
NO
YES
RESET MARGIN MODE
CHECK ALL WORDS
1st: VCC = 5V
2nd: VCC = 3V
AI03059B
PRESTO III Programming Algorithm
The PRESTO III Programming Algorithm allows
the whole array to be programed with a guaranteed margin in a typical time of 100 seconds. Programming with PRESTO III consists of applying a
sequence of 50µs program pulses to each word
until a correct verify occurs (see Figure 8). During
programing and verify operation a MARGIN
MODE circuit must be activated to guarantee that
each cell is programed with enough margin. No
overprogram pulse is applied since the verify in
MARGIN MODE provides the necessary margin to
each programmed cell.
Program Inhibit
Programming of multiple M27V322s in parallel
with different data is also easily accomplished. Except for E, all like inputs including GVPP of the parallel M27V322 may be common. A TTL low level
pulse applied to a M27V322's E input and VPP at
12V, will program that M27V322. A high level E input inhibits the other M27V322s from being programmed.
Program Verify
A verify (read) should be performed on the programmed bits to determine that they were correctly programmed. The verify is accomplished with
GVPP at V IL. Data should be verified with tELQV after the falling edge of E.
On-Board Programming
The M27V322 can be directly programmed in the
application circuit. See the relevant Application
Note AN620.
Electronic Signature
The Electronic Signature (ES) mode allows the
reading out of a binary code from an EPROM that
will identify its manufacturer and type. This mode
is intended for use by programming equipment to
automatically match the device to be programmed
with its corresponding programming algorithm.
The ES mode is functional in the 25°C ± 5°C ambient temperature range that is required when programming the M27V322. To activate the ES mode,
the programming equipment must force 11.5V to
12.5V on address line A9 of the M27V322, with
VPP = VCC = 5V. Two identifier bytes may then be
sequenced from the device outputs by toggling address line A0 from VIL to VIH. All other address
lines must be held at V IL during Electronic Signature mode.
Byte 0 (A0 = VIL) represents the manufacturer
code and byte 1 (A0 = VIH) the device identifier
code. For the STMicroelectronics M27V322, these
two identifier bytes are given in Table 4 and can be
read-out on outputs Q0 to Q7.
ERASURE OPERATION (applies to UV EPROM)
The erasure characteristics of the M27V322 is
such that erasure begins when the cells are exposed to light with wavelengths shorter than approximately 4000 Å. It should be noted that
sunlight and some type of fluorescent lamps have
wavelengths in the 3000-4000 Å range. Research
shows that constant exposure to room level fluorescent lighting could erase a typical M27V322 in
about 3 years, while it would take approximately 1
week to cause erasure when exposed to direct
sunlight. If the M27V322 is to be exposed to these
types of lighting conditions for extended periods of
time, it is suggested that opaque labels be put over
the M27V322 window to prevent unintentional erasure. The recommended erasure procedure for
M27V322 is exposure to short wave ultraviolet
light which has a wavelength of 2537 Å. The integrated dose (i.e. UV intensity x exposure time) for
erasure should be a minimum of 30 W-sec/cm 2.
The erasure time with this dosage is approximately 30 to 40 minutes using an ultraviolet lamp with
12000 µW/cm2 power rating. The M27V322
should be placed within 2.5cm (1 inch) of the lamp
tubes during the erasure. Some lamps have a filter
on their tubes which should be removed before
erasure.
9/13
M27V322
Table 12. Ordering Information Scheme
Example:
M27V322
-100 X
F
1
Device Type
M27
Supply Voltage
V = 3.3V ±10%
Device Function
322 = 32 Mbit (2Mb x16)
Speed
-100 = 100 ns (1)
-120 = 120 ns
-150 = 150 ns
VCC Tolerance
blank = 3.3V ±10%
X = 3.3V ±5%
Package
F = FDIP42W
P = PDIP42
Temperature Range
1 = 0 to 70 °C
6 = –40 to 85 °C
Note: 1. High Speed, see AC Characteristics section for further information.
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you.
Table 13. Revision History
Date
Revision Details
July 1999
First Issue
02/09/00
Programming Flowchart changed (Figure 8)
PRESTO III Programming Algorithm paragraph changed
FDIP42W Package Dimension, L Max added (Table 14)
10/13
M27V322
Table 14. FDIP42W - 42 pin Ceramic Frit-seal DIP with window, Package Mechanical Data
mm
Symb
Typ
inches
Min
Max
A
Typ
Min
5.72
Max
0.225
A1
0.51
1.40
0.020
0.055
A2
3.91
4.57
0.154
0.180
A3
3.89
4.50
0.153
0.177
B
0.41
0.56
0.016
0.022
–
–
–
–
B1
1.45
0.057
C
0.23
0.30
0.009
0.012
D
54.41
54.86
2.142
2.160
D2
50.80
–
–
2.000
–
–
E
15.24
–
–
0.600
–
–
E1
14.50
14.90
0.571
0.587
e
2.54
–
–
0.100
–
–
eA
14.99
–
–
0.590
–
–
eB
16.18
18.03
0.637
0.710
L
3.18
4.10
0.125
0.161
S
1.52
2.49
0.060
0.098
K
8.00
–
–
0.315
–
–
K1
16.00
–
–
0.630
–
–
α
4°
11°
4°
11°
N
42
42
Figure 9. FDIP42W - 42 pin Ceramic Frit-seal DIP with window, Package Outline
A2
A3
A1
B1
B
A
L
e1
α
eA
D2
C
eB
D
S
N
K
1
E1
E
K1
FDIPW-b
Note: Drawing is not to scale.
11/13
M27V322
Table 15. PDIP42 - 42 pin Plastic DIP, 600 mils width, Package Mechanical Data
Symb
mm
Typ
inches
Min
Max
A
–
A1
Typ
Min
Max
5.08
–
0.200
0.25
–
0.010
–
A2
3.56
4.06
0.140
0.160
B
0.38
0.53
0.015
0.021
B1
1.27
1.65
0.050
0.065
C
0.20
0.36
0.008
0.014
D
52.20
52.71
2.055
2.075
D2
50.80
–
–
2.000
–
–
E
15.24
–
–
0.600
–
–
13.59
13.84
0.535
0.545
E1
e1
2.54
–
–
0.100
–
–
eA
14.99
–
–
0.590
–
–
eB
15.24
17.78
0.600
0.700
L
3.18
3.43
0.125
0.135
S
0.86
1.37
0.034
0.054
α
0°
10°
0°
10°
N
42
42
Figure 10. PDIP42 - 42 pin Plastic DIP, 600 mils width, Package Outline
A2
A1
B1
B
A
L
e1
α
eA
D2
C
eB
D
S
N
E1
E
1
PDIP
Note: Drawing is not to scale.
12/13
M27V322
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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13/13