M36P0R9070E0 512 Mbit (x16, Multiple Bank, Multi-Level, Burst) Flash Memory 128 Mbit (Burst) PSRAM, 1.8V Supply, Multi-Chip Package PRELIMINARY DATA Features summary ■ ■ ■ ■ Multi-chip package – 1die of 512 Mbit (32Mb x 16, Multiple Bank, Multi-Level, Burst) Flash Memory – 1 die of 128Mbit (8Mb x16) PSRAM Supply voltage – VDDF = VCCP = VDDQ = 1.7 to 1.95V – VPPF = 9V for fast program (12V tolerant) Electronic signature – Manufacturer Code: 20h – Device Code: 8819 Package – ECOPACK® Flash memory ■ FBGA TFBGA107 (ZAC) ■ Security – 2112-bit user programmable OTP Cells – 64-bit unique device number ■ 100,000 program/erase cycles per block ■ Block locking – All Blocks locked at power-up – Any combination of Blocks can be locked with zero latency – WPF for Block Lock-Down – Absolute Write Protection with VPPF = VSS ■ Common Flash Interface (CFI) Synchronous / asynchronous read – Synchronous Burst Read mode: 108MHz, 66MHz – Asynchronous Page Read mode – Random Access: 93ns ■ ■ ■ Programming time – 4µs typical Word program time using Buffer Enhanced Factory Program command Memory organization – Multiple Bank Memory Array: 64 Mbit Banks – Four Extended Flash Array (EFA) Blocks of 64 Kbits Dual operations – program/erase in one Bank while read in others – No delay between read and write operations PSRAM ■ Access time: 70ns ■ Asynchronous Page Read – Page Size: 4, 8 or 16 Words – Subsequent read within page: 20ns ■ Low power features – Partial Array Self Refresh (PASR) – Deep Power-Down mode (DPD) ■ Synchronous Burst Read/Write November 2005 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. Rev. 1 1/26 www.st.com 1 M36P0R9070E0 Contents 1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 Address inputs (A0-A24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 Data input/output (DQ0-DQ15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3 Latch Enable (L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4 Clock (K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.5 Wait (WAIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.6 Flash Chip Enable input (EF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.7 Flash Output Enable inputs (GF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.8 Flash Write Enable (WF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.9 Flash Write Protect (WPF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.10 Flash Reset (RPF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.11 PSRAM Chip Enable input (EP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.12 PSRAM Write Enable (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.13 PSRAM Output Enable (GP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.14 PSRAM Upper Byte Enable (UBP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.15 PSRAM Lower Byte Enable (LBP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.16 PSRAM Configuration Register Enable (CRP) . . . . . . . . . . . . . . . . . . . . . . . 11 2.17 Deep Power-Down input (DPDF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.18 VDDF Supply Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.19 VCCP Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.20 VDDQ Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.21 VPPF Program Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.22 VSS Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2/26 M36P0R9070E0 6 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3/26 M36P0R9070E0 List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. 4/26 Logic Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Main Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Flash Memory DC Characteristics - Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Flash Memory DC Characteristics - Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 PSRAM DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Stacked TFBGA107 8x11mm - 9x12 active ball array, 0.8mm pitch, package data. . . . . . 23 Ordering Information Scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 M36P0R9070E0 List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. TFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 AC Measurement I/O Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 TFBGA107 8x11mm - 9x12 active ball array, 0.8mm pitch, package outline . . . . . . . . . . . 22 5/26 M36P0R9070E0 1 Summary description 1 Summary description The M36P0R9070E0 combines two memory devices in one Multi-Chip Package: ● 512-Mbit Multiple Bank Flash memory (the M58PR512J). ● 128 Mbit PSRAM (the M69KB128AA). This datasheet should be read in conjunction with the M58PR512J and M69KB128AA datasheets, which are available from www.st.com. Recommended operating conditions do not allow more than one memory to be active at the same time. The memory is offered in a Stacked TFBGA107 package. It is supplied with all the bits erased (set to ‘1’). Table 1. Logic Diagram VDDF VDDQ VCCP VPPF 25 16 DQ0-DQ15 A0-A24 EF WAIT GF WF RPF WPF L M36P0R9070E0 K DPDF EP GP WP CRP UBP LBP VSS 6/26 AI10845 M36P0R9070E0 Table 2. 1 Summary description Signal Names A0-A24(1) Address Inputs DQ0-DQ15 Common Data Input/Output VDDQ Common Flash and PSRAM Power Supply for I/O Buffers VPPF Flash Memory Optional Supply Voltage for Fast Program & Erase VDDF Flash Memory Power Supply VCCP PSRAM Power Supply VSS Ground L Latch Enable input K Burst Clock WAIT Wait Output NC Not Connected Internally DU Do Not Use as Internally Connected Flash Memory EF Chip Enable input GF Output Enable Input WF Write Enable input RPF Reset input WPF Write Protect input DPDF Deep Power-Down PSRAM EP Chip Enable Input GP Output Enable Input WP Write Enable Input CRP Configuration Register Enable Input UBP Upper Byte Enable Input LBP Lower Byte Enable Input Note: 1 A23-A24 are Address Inputs for the Flash memory component only. 7/26 M36P0R9070E0 1 Summary description Figure 1. TFBGA Connections (Top view through package) 1 A 2 3 4 5 6 7 DU NC NC NC VCCP DPDF 8 9 VSS DU B DU A4 A18 A19 VSS VDDF NC A21 A11 C NC A5 LBP A23 VSS NC K A22 A12 D VSS A3 A17 A24 VPP WP EP A9 A13 E VSS A2 A7 NC WPF L A20 A10 A15 F NC A1 A6 UBP RPF WF A8 A14 A16 G VDDQ A0 DQ8 DQ2 DQ10 DQ5 DQ13 WAIT NC H VSS GP DQ0 DQ1 DQ3 DQ12 DQ14 DQ7 NC J DU NC GF DQ9 DQ11 DQ4 DQ6 DQ15 VDDQ K NC EF NC NC NC VCCP NC VDDQ CRP L DU VSS VSS VDDQ VDDF VSS VSS VSS VSS M DU NC DU DU DU DU DU DU DU AI11098 8/26 M36P0R9070E0 2 2 Signal descriptions Signal descriptions See Table 1., Logic Diagram and Table 2., Signal Names, for a brief overview of the signals connected to this device. 2.1 Address inputs (A0-A24) Addresses A0-A22 are common inputs for the Flash memory and PSRAM components. Addresses A23 and A24 are inputs for Flash memory components only. The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the internal state machine. The Flash memory is accessed through the Chip Enable signal (EF) and through the Write Enable signal (WF), while the PSRAM is accessed through the Chip Enable signal (EP) and the Write Enable signal (WP). EF Low, and EP must not be Low at the same time. 2.2 Data input/output (DQ0-DQ15) The Data I/O output the data stored at the selected address during a Bus Read operation or input a command or the data to be programmed during a Bus Write operation. For the PSRAM component, the upper Byte Data Inputs/Outputs (DQ8-DQ15) carry the data to or from the upper part of the selected address when Upper Byte Enable (UBP) is driven Low. The lower Byte Data Inputs/Outputs (DQ0-DQ7) carry the data to or from the lower part of the selected address when Lower Byte Enable (LBP) is driven Low. When both UBP and LBP are disabled, the Data Inputs/ Outputs are high impedance. 2.3 Latch Enable (L) The Latch Enable pin is common to the Flash memory and PSRAM components. For details of how the Latch Enable signal behaves, please refer to the datasheets of the respective memory components: M69KB128AA for the PSRAM and M58PR512J for the Flash memory. 2.4 Clock (K) The Clock input pin is common to the Flash memory and PSRAM components. For details of how the Clock signal behaves, please refer to the datasheets of the respective memory components: M69KB128AA for the PSRAM and M58PR512J for the Flash memory. 9/26 2 Signal descriptions 2.5 M36P0R9070E0 Wait (WAIT) WAIT is an output pin common to the Flash memory and PSRAM components. However the WAIT signal does not behave in the same way for the PSRAM and the Flash memory. For details of how it behaves, please refer to the M69KB128AA datasheet for the PSRAM and to the M58PR512J datasheet for the Flash memory. 2.6 Flash Chip Enable input (EF) The Flash Chip Enable input activates the control logic, input buffers, decoders and sense amplifiers of the Flash memory component selected. When Chip Enable is Low, VIL, and Reset is High, VIH, the device is in active mode. When Chip Enable is at VIH the corresponding Flash memory are deselected, the outputs are high impedance and the power consumption is reduced to the standby level. It is not allowed to have EF at VIL and EP at VIL at the same time. Only one memory component can be enabled at a time. 2.7 Flash Output Enable inputs (GF) The Output Enable pins control the data outputs during Flash memory Bus Read operations. 2.8 Flash Write Enable (WF) The Write Enable controls the Bus Write operation of the Flash memory Command Interface. The data and address inputs are latched on the rising edge of Chip Enable or Write Enable whichever occurs first. 2.9 Flash Write Protect (WPF) Write Protect is an input that gives an additional hardware protection for each block. When Write Protect is Low, VIL, Lock-Down is enabled and the protection status of the Locked-Down blocks cannot be changed. When Write Protect is at High, VIH, Lock-Down is disabled and the Locked-Down blocks can be locked or unlocked. (See the Lock Status Table in the M58PR512J datasheet). 2.10 Flash Reset (RPF) The Reset input provides a hardware reset of the Flash memories. When Reset is at VIL, the memory is in Reset mode: the outputs are high impedance and the current consumption is reduced to the Reset Supply Current IDD2. Refer to Table 7., Flash Memory DC Characteristics - Currents, for the value of IDD2. After Reset all blocks are in the Locked state and the Configuration Register is reset. When Reset is at VIH, the device is in normal operation. Exiting Reset mode the device enters Asynchronous Read mode, but a negative transition of Chip Enable or Latch Enable is required to ensure valid data outputs. 10/26 M36P0R9070E0 2 Signal descriptions The Reset pin can be interfaced with 3V logic without any additional circuitry. It can be tied to VRPH (refer to Table 8., Flash Memory DC Characteristics - Voltages). 2.11 PSRAM Chip Enable input (EP) The Chip Enable input activates the PSRAM when driven Low (asserted). When deasserted (VIH), the device is disabled, and goes automatically in low-power Standby mode or Deep Power-down mode. 2.12 PSRAM Write Enable (WP) Write Enable, WP, controls the Bus Write operation of the PSRAM. When asserted (VIL), the device is in Write mode and Write operations can be performed either to the configuration registers or to the memory array. 2.13 PSRAM Output Enable (GP) Output Enable, GP, provides a high speed tri-state control, allowing fast read/write cycles to be achieved with the common I/O data bus. 2.14 PSRAM Upper Byte Enable (UBP) The Upper Byte En-able, UBP, gates the data on the Upper Byte Data Inputs/Outputs (DQ8DQ15) to or from the upper part of the selected address during a Write or Read operation. 2.15 PSRAM Lower Byte Enable (LBP) The Lower Byte Enable, LBP, gates the data on the Lower Byte Data Inputs/Outputs (DQ0DQ7) to or from the lower part of the selected address during a Write or Read operation. If both LBP and UBP are disabled (High) during an operation, the device will disable the data bus from receiving or transmitting data. Although the device will seem to be deselected, it remains in an active mode as long as EP remains Low. 2.16 PSRAM Configuration Register Enable (CRP) When this signal is driven High, VIH, Write operations load either the value of the Refresh Configuration Register (RCR) or the Bus configuration register (BCR). 11/26 2 Signal descriptions 2.17 M36P0R9070E0 Deep Power-Down input (DPDF) The Deep Power-Down input is used to place the device in a Deep Power-Down mode.When the device is in Deep Power-Down mode, the memory cannot be modified and data is protected. For further details on how the Deep Power-Down input signal works, please refer to the M58PR512J datasheet. 2.18 VDDF Supply Voltages VDDF provides the power supply to the internal cores of the Flash memory. It is the main power supply for all Flash memory operations (Read, Program and Erase). 2.19 VCCP Supply Voltage VCCP provides the power supply to the internal core of the PSRAM device. It is the main power supply for all PSRAM operations. 2.20 VDDQ Supply Voltage VDDQ provides the power supply for the Flash memory and PSRAM I/O pins. This allows all Outputs to be powered independently of the Flash memory and SRAM core power supplies, VDDF and VCCP. 2.21 VPPF Program Supply Voltage VPPF is both a control input and a power supply pin for the Flash memory. The two functions are selected by the voltage range applied to the pin. If VPPF is kept in a low voltage range (0V to VDDQ) VPPF is seen as a control input. In this case a voltage lower than VPPLK gives an absolute protection against Program or Erase, while VPPF > VPP1 enables these functions (see Tables 7 and 8, Flash Memory DC Characteristics for the relevant values). VPPF is only sampled at the beginning of a Program or Erase; a change in its value after the operation has started does not have any effect and Program or Erase operations continue. If VPPF is in the range of VPPH it acts as a power supply pin. In this condition VPPF must be stable until the Program/Erase algorithm is completed. 12/26 M36P0R9070E0 2.22 2 Signal descriptions VSS Ground VSS is the common ground reference for all voltage measurements in the Flash (core and I/O Buffers) and PSRAM chips. It must be connected to the system ground. Note: Each Flash memory device in a system should have their supply voltage (VDDF) and the program supply voltage VPPF decoupled with a 0.1µF ceramic capacitor close to the pin (high frequency, inherently low inductance capacitors should be as close as possible to the package). See Figure 4., AC Measurement Load Circuit. The PCB track widths should be sufficient to carry the required VPPF program and erase currents. 13/26 M36P0R9070E0 3 Functional description 3 Functional description The PSRAM and Flash memory components have separate power supplies but share the same grounds. They are distinguished by two Chip Enable inputs: EF for Flash and EP for the PSRAM. Recommended operating conditions do not allow more than one device to be active at a time. The most common example is a simultaneous read operations on the Flash memory and the PSRAM which would result in a data bus contention. Therefore it is recommended to put the other devices in the high impedance state when reading the selected device. Figure 2. Functional Block Diagram VDDF VPPF EF GF A23-A24 DPDF WF RPF WPF 512 Mbit Flash Memory A0-A22 DQ0-DQ15 WAIT L K VCCP EP GP VSS V DDQ 128Mbit PSRAM WP CRP UBP LBP Ai11731 14/26 M36P0R9070E0 Table 3. 3 Functional description Main Operating Modes Operation Flash Read EF GF WF LF VIL VIL VIH VIL(2) RPF WAITF(4) WP LBP,UBP DQ15-DQ0 Flash Data Out VIH VIL VIL(2) VIH Flash Address Latch VIL X VIH VIL VIH Flash Output Disable VIL VIH VIH X VIH Flash Standby VIH X X X VIH Hi-Z Flash Reset X X X X VIL Hi-Z Flash Deep Power-Down VIH X X X VIH Hi-Z Flash Data In Flash Data Out or Hi-Z (3) Hi-Z PSRAM Read Flash memories must be disabled PSRAM Read Configuration Register PSRAM Deep Power-Down GP PSRAM must be disabled. Only one Flash memory can be enabled at a time. VIL PSRAM Standby CRP VIH Flash Write PSRAM Write EP Any Flash memory mode is allowed. Only one Flash memory can be enabled at a time Any PSRAM mode is allowed. Flash memories must be disabled. Hi-Z Hi-Z Hi-Z VIL VIL VIL VIH VIL PSRAM data out VIL VIL X VIL VIL PSRAM data in VIL VIH VIL VIH VIL PSRAM data out VIH VIL X X X Hi-Z VIH X X X X Hi-Z Note: 1 X = Don't care 2 LF can be tied to VIH if the valid address has been previously latched 3 Depends on GF 4 WAITF signal polarity is configured using the Set Configuration Register command. See the M58PR512J datasheet for details. 15/26 M36P0R9070E0 4 Maximum rating 4 Maximum rating Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 4. Absolute Maximum Ratings Value Symbol Unit Min Max Ambient Operating Temperature –30 85 °C TBIAS Temperature Under Bias –30 85 °C TSTG Storage Temperature –65 125 °C VIO Input or Output Voltage –0.2 2.45 V VDD Supply Voltage –0.2 2.45 V Input/Output Supply Voltage –0.2 2.45 V Program Voltage –1.0 12.6 V Output Short Circuit Current 100 mA Time for VPP at VPPH 100 hours TA VDDQ VPP IO tVPPH 16/26 Parameter M36P0R9070E0 5 5 DC and AC parameters DC and AC parameters This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measurement Conditions summarized in Table 5., Operating and AC Measurement Conditions. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. Table 5. Operating and AC Measurement Conditions Flash Memory PSRAM Parameter Unit Min Max Min Max VCCP Supply Voltage 1.7 1.95 1.7 1.95 V VDDF Supply Voltage 1.7 1.95 1.7 1.95 V VDDQ Supply Voltage 1.7 1.95 1.7 1.95 V VPPF Supply Voltage (Factory environment) 8.5 9.5 – – V VPPF Supply Voltage (Application environment) –0.4 VDDQ +0.4 – – V Ambient Operating Temperature –30 85 –30 85 °C Load Capacitance (CL) 30 30 pF Impedance Output (Z0) 50 Ω Output Circuit Protection Resistance (R) 50 Ω Input Rise and Fall Times 3 Input Pulse Voltages Input and Output Timing Ref. Voltages Figure 3. ns 0 to VDDQ 0 to VDDQ V VDDQ/2 VDDQ/2 V AC Measurement I/O Waveform VDDQ VDDQ/2 0V AI06161 17/26 M36P0R9070E0 5 DC and AC parameters Figure 4. AC Measurement Load Circuit VCCQ/2 R DEVICE UNDER TEST OUT Z0 CL AI06162a Table 6. Capacitance Symbol Parameter Test Condition CIN Input Capacitance COUT Output Capacitance 1. Sampled only, not 100% tested. 18/26 Min Max Unit VIN = 0V 14 pF VOUT = 0V 14 pF M36P0R9070E0 Table 7. Symbol ILI ILO 5 DC and AC parameters Flash Memory DC Characteristics - Currents Parameter Input Leakage Current Output Leakage Current Supply Current Asynchronous Read (f=5MHz) Supply Current Page Read (f=13MHz) Test Condition Typ Max Unit 0V ≤VIN ≤VDDQ ±1 µA 0V ≤VOUT ≤VDDQ ±1 µA 25 30 mA 11 15 mA EF = VIL, GF = VIH IDD2 Supply Current (Reset) 8 Word 16 Word Continuous 8 Word 16 Word Continuous RPF = VSS ± 0.2V 512 Mbit IDD3 Supply Current (Standby) EF = VDDF ± 0.2V 512 Mbit 50 120 µA IDD4 Supply Current (Automatic Standby) EF = VIL, GF = VIH 512 Mbit 50 120 µA IDD5(1) Supply Current (Deep Power Down) 2 30 µA IDD1 Supply Current Synchronous Read (f=66MHz) Supply Current Synchronous Read (f = 108MHz) Supply Current (Program) IDD6 (2) Supply Current (Erase) Supply Current (Blank Check) IDD7 (2)(3) IDD8(2) Supply Current (Dual Operations) Supply Current Program/ Erase Suspended (Standby) VPPF Supply Current (Program) IPP1(2) IPP3(2) IPP4 32 26 34 36 30 42 mA mA mA mA mA mA 50 120 µA VPPF = VPPH 35 50 mA VPPF = VDDF 35 50 mA VPPF = VPPH 35 50 mA VPPF = VDDF 35 50 mA VPPF = VPPH 35 50 mA VPPF = VDDF 35 50 mA 60 80 mA 65 92 mA 50 120 µA VPPF = VPPH 8 22 mA VPPF = VDDF 0.05 0.1 µA Program/Erase in one Bank, Asynchronous Read in another Bank Program/Erase in one Bank, Synchronous Read (Continuous f=66MHz) in another Bank EF = VDDF ± 0.2V 512 Mbit VPPF = VPPH 8 22 mA VPPF = VDDF 0.05 0.1 µA VPPF Supply Current (Read) VPP F≤VDDF 2 15 µA VPPF Supply Current (Standby, Program/Erase Suspend) VPPF ≤VDDF 0.2 5 µA VPPF = VPPH 0.05 0.1 mA VPPF = VPP1 0.05 0.1 mA VPPF Supply Current (Erase) IPP2 22 19 25 26 23 30 VPPF Supply Current (Blank Check) 1. The DPD current is measured 40µs after entering the Deep Power Down mode. 2. Sampled only, not 100% tested. 3. VDDF Dual Operation current is the sum of read and program or erase currents. 19/26 M36P0R9070E0 5 DC and AC parameters Table 8. Symbol Flash Memory DC Characteristics - Voltages Parameter Test Condition Min Typ Max Unit VIL Input Low Voltage 0 0.4 V VIH Input High Voltage VDDQ –0.4 VDDQ + 0.4 V VOL Output Low Voltage IOL = 100µA 0.1 V VOH Output High Voltage IOH = –100µA VDDQ –0.1 VPP1 VPPF Program Voltage-Logic Program, Erase 1.1 1.8 3.3 V VPPH VPPF Program Voltage Factory Program, Erase 8.5 9.0 9.5 V VPPLK Program or Erase Lockout 0.4 V VLKO VDDF Lock Voltage VRPH RPF pin Extended High Voltage VLKOQ VDDQ Lock Voltage 20/26 V 1 V 3.3 0.9 V V M36P0R9070E0 Table 9. Symbol 5 DC and AC parameters PSRAM DC Characteristics Parameter Refreshed Array Test Conditions Min. 0.8VDDQ VOH(3) Output High Voltage IOH = –0.2mA VOL(3) Output Low Voltage IOL = 0.2mA VIH(1) Input High Voltage VIL(2) Input Low Voltage ILI Input Leakage Current ILO Output Leakage Current ICC1(4) Asynchronous Read/Write Random at tRC min ICC2(4) Asynchronous Page Read ICC3(4) Burst, Initial Read/Write Access ICC4R(4) Continuous Burst Read ICC4W(4 Continuous Burst Write ) Typ. 1/2 Array 1/4 Array 1/8 Array 0.2VDDQ V VDDQ −0.4 VDDQ + 0.2 V −0.2 0.4 V VIN = 0 to VDDQ 1 µA GP = VIH or EP = VIH 1 µA VIN = 0V or VDDQ, 70ns 25 mA IOUT = 0mA, EP = VIL 85ns 22 mA VIN = 0V or VDDQ 70ns 15 mA IOUT = 0mA, EP = VIL 85ns 12 mA 104MHz 35 mA 80MHz 30 mA 66MHz 25 mA 104MHz 30 mA 80MHz 25 mA 66MHz 20 mA 104MHz 35 mA 80MHz 30 mA 66MHz 25 mA 200 µA 170 µA 155 µA 150 µA 140 µA 200 µA 10 µA VIN = 0V or VDDQ IOUT = 0mA, EP = VIL VIN = 0V or VDDQ IOUT = 0mA, EP = VIL VIN = 0V or VDDQ IOUT = 0mA, EP = VIL VIN = 0V or VDDQ EP = VDDQ None ISB(5) Standby Current ICCPD Deep-Power Down Current Unit V Full Array Partial Array Refresh IPASR(4) Standby Current Max. VIN = 0V or VDDQ EP = VDDQ VIN = 0V or VDDQ, VCCP, VDDQ = 1.95V; TA= +85°C 3 1. Input signals may overshoot to VDDQ+ 1.0V for periods of less than 2ns during transitions. 2. Output signals may undershoot to VSS – 1.0V for periods of less than 2ns during transitions. 3. BCR5-BCR4 = 01 (default settings). 4. This parameter is specified with all outputs disabled to avoid external loading effects. The user must add the current required to drive output capacitance expected for the actual system. 5. ISB maximum value is measured at +85°C with PAR set to Full Array. In order to achieve low standby current, all inputs must be driven either to VDDQ or VSSQ. ISB might be slightly higher for up to 500ms after Power-up, or when entering Standby mode. 21/26 M36P0R9070E0 6 Package mechanical 6 Package mechanical In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second-level interconnect. The category of Second-Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 5. TFBGA107 8x11mm - 9x12 active ball array, 0.8mm pitch, package outline D D1 FD e ddd SE E E1 BALL "B1" FE A e b A2 A1 BGA-Z85 1. Drawing is not to scale. 22/26 M36P0R9070E0 Table 10. 6 Package mechanical Stacked TFBGA107 8x11mm - 9x12 active ball array, 0.8mm pitch, package data millimeters inches Symbol Typ Min A Max Typ Min 1.20 A1 Max 0.047 0.20 0.008 A2 0.85 0.033 b 0.35 0.30 0.40 0.014 0.012 0.016 D 8.00 7.90 8.10 0.315 0.311 0.319 D1 6.40 0.252 ddd 0.10 10.90 11.10 0.004 E 11.00 0.433 E1 8.80 0.346 e 0.80 0.031 FD 0.80 0.031 FE 1.10 0.043 SE 0.40 0.016 0.429 0.437 23/26 M36P0R9070E0 7 Part numbering 7 Table 11. Part numbering Ordering Information Scheme M36 P 0 R 9 0 7 0 E 0 ZAC E Example: Device Type M36 = Multi-Chip Package (Multiple Flash + PSRAM) Flash 1 Architecture P = Multi-Level, Multiple Bank, Large Buffer Flash 2 Architecture 0 = No Die Operating Voltage R = VDDF = VCCP = VDDQ = 1.7 to 1.95V Flash 1 Density 9 = 512 Mbits Flash 2 Density 0 = No Die RAM 1 Density 7 = 128 Mbits RAM 0 Density 0 = No Die Parameter Blocks Location E = Even Block Flash Memory Configuration Product Version 0 = 90nm Flash technology, 93ns speed; PSRAM Package ZAC= stacked TFBGA107 C stacked footprint. Option Blank = Standard Packing E = ECOPACK® Package, Standard packing F = ECOPACK® Package, Tape & Reel packing Note: 24/26 Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you. M36P0R9070E0 8 8 Revision history Revision history Table 12. Document revision history Date Revision 28-Nov-2005 1 Changes Initial release. 25/26 M36P0R9070E0 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. 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