STMICROELECTRONICS M40Z300

M40Z300
M40Z300W
NVRAM CONTROLLER for up to EIGHT LPSRAM
■
■
■
■
■
■
■
■
■
■
CONVERT LOW POWER SRAMs into
NVRAMs
PRECISION POWER MONITORING and
POWER SWITCHING CIRCUITRY
AUTOMATIC WRITE-PROTECTION when VCC
is OUT-OF-TOLERANCE
TWO INPUT DECODER ALLOWS CONTROL
for up to 8 SRAMs (with 2 devices active in
parallel)
CHOICE of SUPPLY VOLTAGES and
POWER-FAIL DESELECT VOLTAGES:
– M40Z300:
VCC = 4.5V to 5.5V
THS = VSS 4.5V ≤ VPFD ≤ 4.75V
THS = VOUT 4.2V ≤ V PFD ≤ 4.5V
– M40Z300W:
VCC = 3.0V to 3.6V
THS = VSS 2.8V ≤ VPFD ≤ 3.0V
VCC = 2.7V to 3.3V
THS = VOUT 2.5 ≤ VPFD ≤ 2.7V
RESET OUTPUT (RST) for POWER ON
RESET
LESS THAN 12ns CHIP ENABLE ACCESS
PROPAGATION DELAY (for 5.0V device)
PACKAGING INCLUDES a 28-LEAD SOIC
and SNAPHAT® TOP, or a 16-LEAD SOIC
(to be Ordered Separately)
SOIC PACKAGE PROVIDES DIRECT
CONNECTION for a SNAPHAT TOP which
CONTAINS the BATTERY
BATTERY LOW PIN (BL)
DESCRIPTION
The M40Z300/W NVRAM Controller is a self-contained device which converts a standard low-power SRAM into a non-volatile memory. A precision
voltage reference and comparator monitors the
VCC input for an out-of-tolerance condition.
SNAPHAT (SH)
Battery
16
1
28
1
SO16 (MQ)
SOH28 (MH)
Figure 1. Logic Diagram
VCC
B+(1)
THS
VOUT
E
BL
B
A
E1CON
M40Z300
M40Z300W
E2CON
E3CON
E4CON
RST
VSS B–(1)
NOTE: 1. For 16-pin SOIC package only.
AI02242
March 2000
1/16
M40Z300, M40Z300W
Figure 2B. SOIC16 Connections
Figure 2A. SOIC28 Connections
VOUT
NC
NC
RST
NC
A
NC
B
NC
BL
NC
NC
THS
VSS
1
28
27
2
26
3
25
4
24
5
23
6
7 M40Z300 22
8 M40Z300W 21
20
9
19
10
18
11
17
12
16
13
15
14
VCC
E
NC
NC
NC
E1CON
E2CON
NC
E3CON
NC
NC
NC
E4CON
NC
VOUT
NC
RST
A
B
BL
THS
VSS
1
16
15
2
14
3
4 M40Z300 13
5 M40Z300W 12
11
6
7
10
8
9
VCC
B+ (B–)
E
E1CON
E2CON
E3CON
E4CON
B– (B+)
( ) = M40Z300W
AI03624
AI02243
Table 1. Signal Names
THS
Threshold Select Input
E
Chip Enable Input
E1CON-E4CON
Conditioned Chip Enable Output
A, B
Decoder Inputs
RST
Reset Output (Open Drain)
BL
Battery Low Output (Open Drain)
VOUT
Supply Voltage Output
VCC
Supply Voltage
VSS
Ground
B+
Positive Battery Pin
B–
Negative Battery Pin
NC
Not Connected Internally
2/16
When an invalid V CC condition occurs, the conditioned chip enable outputs (E1 CON to E4CON ) are
forced inactive to write-protect the stored data in
the SRAM. During a power failure, the SRAM is
switched from the VCC pin to the lithium cell within
the SNAPHAT to provide the energy required for
data retention. On a subsequent power-up, the
SRAM remains write protected until a valid power
condition returns.
The 28 pin, 330 mil SOIC provides sockets with
gold plated contacts for direct connection to a separate SNAPHAT housing containing the battery.
The SNAPHAT housing has gold plated pins
which mate with the sockets, ensuring reliable
connection. The housing is keyed to prevent improper insertion. This unique design allows the
SNAPHAT battery package to be mounted on top
of the SOIC package after the completion of the
surface mount process which greatly reduces the
board manufacturing process complexity of either
directly soldering or inserting a battery into a soldered holder. Providing non-volatility becomes a
"SNAP".
The 16 pin SOIC provides battery pins for an external user supplied battery.
M40Z300, M40Z300W
Table 2. Absolute Maximum Ratings (1)
Symbol
TA
TSTG
VIO
VCC
Parameter
Ambient Operating Temperature
Storage Temperature (VCC Off)
SNAPHAT
SOIC
Input or Output Voltages
Supply Voltage
M40Z300
M40Z300W
Value
Unit
0 to 70
°C
–40 to 85
–55 to 125
°C
–0.3 to VCC +0.3
V
–0.3 to 7
–0.3 to 4.6
V
IO
Output Current
20
mA
PD
Power Dissipation
1
W
Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational section
of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect
reliability.
CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.
CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
OPERATION
The M40Z300/W, as shown in Figure 4, can control up to four (eight, if placed in parallel) standard
low-power SRAMs. These SRAMs must be configured to have the chip enable input disable all other
input signals. Most slow, low-power SRAMs are
configured like this, however many fast SRAMs
are not. During normal operating conditions, the
conditioned chip enable (E1CON to E4CON ) output
pins follow the chip enable (E) input pin with timing
shown in Table 7. An internal switch connects V CC
to
V OUT.
This switch has a voltage drop of less than 0.3V
(IOUT1).
When V CC degrades during a power failure,
E1CON to E4CON are forced inactive independent
of E. In this situation, the SRAM is unconditionally
write protected as VCC falls below an out-of-tolerance threshold (VPFD). For the M40Z300 the power fail detection value associated with VPFD is
selected by the Threshold Select (THS) pin and is
shown in Table 6A. For the M40Z300W, the THS
pin selects both the supply voltage and VPFD as
shown in Table 6B.
Note: In either case, THS pin must be connected
to either VSS or VOUT.
If chip enable access is in progress during a power
fail detection, that memory cycle continues to completion before the memory is write protected. If the
memory cycle is not terminated within time tWPT,
E1CON to E4CON are unconditionally driven high,
write protecting the SRAM. A power failure during
a write cycle may corrupt data at the currently addressed location, but does not jeopardize the rest
of the SRAM’s contents. At voltages below VPFD
(min), the user can be assured the memory will be
write protected within the Write Protect Time
(tWPT) provided the VCC fall time exceeds t F (See
Table 7).
As VCC continues to degrade, the internal switch
disconnects VCC and connects the internal battery
to V OUT. This occurs at the switchover voltage
(VSO). Below the VSO, the battery provides a voltage V OHB to the SRAM and can supply current
IOUT2 (see Table 6A/6B).
When V CC rises above VSO, VOUT is switched
back to the supply voltage. Outputs E1CON to
E4CON are held inactive for tCER (120ms maximum) after the power supply has reached V PFD,
independent of the E input, to allow for processor
stabilization (see Figure 6).
3/16
M40Z300, M40Z300W
Table 3. Truth Table
Inputs
Outputs
E
B
A
E1CON
E2CON
E3CON
E4CON
H
X
X
H
H
H
H
L
L
L
L
H
H
H
L
L
H
H
L
H
H
L
H
L
H
H
L
H
L
H
H
H
H
H
L
Table 4. AC Measurement Conditions
Input Rise and Fall Times
Input Pulse Voltages
Input and Output Timing Ref. Voltages
Figure 3. AC Testing Load Circuit
≤ 5ns
0 to 3V
1.5V
DATA RETENTION LIFETIME CALCULATION
Most low power SRAMs on the market today can
be used with the M40Z300/W NVRAM Controller.
There are, however some criteria which should be
used in making the final choice of which SRAM to
use. The SRAM must be designed in a way where
the chip enable input disables all other inputs to
the SRAM. This allows inputs to the M40Z300/W
and SRAMs to be Don’t Care once VCC falls below
VPFD (min). The SRAM should also guarantee
data retention down to VCC = 2.0V. The chip enable access time must be sufficient to meet the
system needs with the chip enable propagation
delays included. If the SRAM includes a second
Chip Enable pin (E2), this pin should be tied to
VOUT.
If data retention lifetime is a critical parameter for
the system, it is important to review the data retention current specifications for the particular
SRAMs being evaluated. Most SRAMs specify a
data retention current at 3.0V. Manufacturers generally specify a typical condition for room temperature along with a worst case condition (generally
at elevated temperatures). The system level requirements will determine the choice of which value to use. The data retention current value of the
SRAMs can then be added to the I CCDR value of
4/16
333Ω
DEVICE
UNDER
TEST
CL = 50pF
CL includes JIG capacitance
1.73V
AI02393
the M40Z300/W to determine the total current requirements for data retention. The available battery capacity for the SNAPHAT of your choice can
then be divided by this current to determine the
amount of data retention available (see Table 8).
CAUTION: Take care to avoid inadvertent discharge through V OUT and E1CON-E4CON after battery has been attached.
For a further more detailed review of lifetime calculations, please see Application Note AN1012.
M40Z300, M40Z300W
Figure 4. Hardware Hookup
3.0V, 3.3V or 5V
VCC
VOUT
VCC
0.1µF
VCC
CMOS
SRAM
M40Z300
M40Z300W
0.1µF
CMOS
SRAM
0.1µF
E
A
B
E
Threshold
VCC
CMOS
SRAM
0.1µF
E
VCC
CMOS
SRAM
0.1µF
E
E
E1CON
E2CON
E3CON
E4CON
THS
RST
VSS
BL
To Microprocessor
To Battery Monitor Circuit
AI02395
POWER-ON RESET OUTPUT
All microprocessors have a reset input which forces them to a known state when starting. The
M40Z300/W has a reset output (RST) pin which is
guaranteed to be low within tWPT of V PFD (See Table 7). This signal is an open drain configuration.
An appropriate pull-up resistor should be chosen
to control the rise time. This signal will be valid for
all voltage conditions, even when V CC equals VSS.
Once VCC exceeds the power failure detect voltage VPFD, an internal timer keeps RST low for
tREC to allow the power supply to stabilize.
TWO TO FOUR DECODE
The M40Z300/W includes a 2 input (A, B) decoder
which allows the control of up to 4 independent
SRAMs. The Truth Table for these inputs is shown
in Table 3.
5/16
M40Z300, M40Z300W
Table 5. Capacitance (1)
(TA = 25 °C, f = 1 MHz)
Symbol
CIN
COUT
Parameter
Test Condition
Input Capacitance
Output Capacitance
Min
Max
Unit
VIN = 0V
8
pF
VOUT = 0V
10
pF
Note: 1. Sampled only, not 100% tested.
2. Outputs deselected.
Table 6A. DC Characteristics for M40Z300
(TA = 0 to 70°C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
Symbol
ILI (1)
Parameter
Input Leakage Current
Test Condition
Min
Typ
0V ≤ VIN ≤ VCC
Unit
±1
µA
6
mA
ICC
Supply Current
VIL
Input Low Voltage
–0.3
0.8
V
VIH
Input High Voltage
2.2
VCC + 0.3
V
VOL
Outputs open
3
Output Low Voltage
IOL = 4.0mA
0.4
V
Output Low Voltage (open drain) (2)
IOL = 10mA
0.4
V
VOH
Output High Voltage
VOHB
VOH Battery Back-up (3)
IOUT1
VOUT Current (Active)
IOH = –2.0mA
2.4
IOUT2 = –1.0µA
2.0
V
VOUT > VCC –0.3
250
mA
VOUT > VCC –0.2
150
mA
VOUT Current (Battery Back-up)
ICCDR
Data Retention Mode Current (4)
THS
Threshold Select Voltage
VSS
Power-fail Deselect Voltage (THS = VSS)
4.5
Power-fail Deselect Voltage (THS = VOUT)
4.2
VPFD
VSO
Battery Back-up Switchover Voltage
V
3.6
IOUT2
VOUT > VBAT –0.3
2.9
100
µA
100
nA
VOUT
V
4.6
4.75
V
4.35
4.5
V
3.0
Note: 1. Outputs deselected.
2. For RST & BL pins (Open Drain).
3. Chip Enable outputs (E1CON - E4CON) can only sustain CMOS leakage currents in the battery back-up mode.
Higher leakage currents will reduce battery life.
4. Measured with V OUT and E1CON - E4CON open.
6/16
Max
V
M40Z300, M40Z300W
Table 6B. DC Characteristics for M40Z300W
(TA = 0 to 70°C; VCC = 3V to 3.6V or 2.7V to 3.3V)
Symbol
ILI (1)
Parameter
Input Leakage Current
Test Condition
Min
Typ
0V ≤ VIN ≤ VCC
Max
Unit
±1
µA
4
mA
ICC
Supply Current
VIL
Input Low Voltage
–0.3
0.8
V
VIH
Input High Voltage
2.0
VCC + 0.3
V
VOL
Outputs open
2
Output Low Voltage
IOL = 4.0mA
0.4
V
Output Low Voltage (open drain) (2)
IOL = 10mA
0.4
V
VOH
Output High Voltage
VOHB
VOH Battery Back-up (3)
IOUT1
VOUT Current (Active)
IOH = –2.0mA
2.4
IOUT2 = –1.0µA
2.0
3.6
V
VOUT > VCC –0.3
150
mA
VOUT > VCC –0.2
100
mA
IOUT2
VOUT Current (Battery Back-up)
ICCDR
Data Retention Mode Current (4)
THS
Threshold Select Voltage
VSS
Power-fail Deselect Voltage (THS = VSS)
2.8
Power-fail Deselect Voltage (THS = VOUT)
2.5
VPFD
VSO
Battery Back-up Switchover Voltage
V
VOUT > VBAT –0.3
2.9
100
µA
100
nA
VOUT
V
2.9
3.0
V
2.6
2.7
V
2.5
V
Note: 1. Outputs deselected.
2. For RST & BL pins (Open Drain).
3. Chip Enable outputs (E1CON - E4CON) can only sustain CMOS leakage currents in the battery back-up mode.
Higher leakage currents will reduce battery life.
4. Measured with V OUT and E1CON - E4CON open.
7/16
M40Z300, M40Z300W
Table 7. Power Down/Up AC Characteristics
(TA = 0 to 70°C)
Symbol
Parameter
Min
Max
Unit
tF (1)
VPFD (max) to VPFD (min) VCC Fall Time
300
µs
tFB (2)
VPFD (min) to VSS VCC Fall Time
150
µs
VPFD(min) to VPFD (max) VCC Rise Time
10
µs
tR
tEDL
Chip Enable Propagation Delay Low
tEDH
Chip Enable Propagation Delay High
tAS
M40Z300
12
ns
M40Z300W
20
ns
M40Z300
10
ns
M40Z300W
20
ns
A, B set up to E
0
tCER
Chip Enable Recovery
40
120
ms
tREC
VPFD (max) to RST High
40
120
ms
M40Z300
40
150
µs
tWPT
Write Protect Time
M40Z300W
40
250
µs
tRB
VSS to VPFD (min) VCC Rise Time
ns
1
µs
Note: 1. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200 µs after
VCC passes VPFD (min)..
2. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
BATTERY LOW PIN
The M40Z300/W automatically performs battery
voltage monitoring upon power-up, and at factoryprogrammed time intervals of at least 24 hours.
The Battery Low (BL) pin will be asserted if the
battery voltage is found to be less than approximately 2.5V. The BL pin will remain asserted until
completion of battery replacement and subsequent battery low monitoring tests, either during
the next power-up sequence or the next scheduled
24-hour interval.
If a battery low is generated during a power-up sequence, this indicates that the battery is below
2.5V and may not be able to maintain data integrity
in the SRAM. Data should be considered suspect,
and verified as correct. A fresh battery should be
installed.
8/16
If a battery low indication is generated during the
24-hour interval check, this indicates that the battery is near end of life. However, data is not compromised due to the fact that a nominal V CC is
supplied. In order to insure data integrity during
subsequent periods of battery back-up mode, the
battery should be replaced. SNAPHAT top should
be replaced with valid VCC applied to the device.
The M40Z300/W only monitors the battery when a
nominal V CC is applied to the device. Thus applications which require extensive durations in the
battery back-up mode should be powered-up periodically (at least once every few months) in order
for this technique to be beneficial. Additionally, if a
battery low is indicated, data integrity should be
verified upon power-up via a checksum or other
technique. The BL pin is an open drain output and
an appropriate pull-up resistor to VCC should be
chosen to control the rise time.
M40Z300, M40Z300W
Figure 5. Power Down Timing
VCC
VPFD (max)
VPFD
VPFD (min)
VSO
tF
tFB
E
tWPT
VOHB
E1CON-E4CON
RST
AI02398B
Figure 6. Power Up Timing
VCC
VPFD (max)
VPFD
VPFD (min)
VSO
tR
tRB
tCER
E
tEDH
E1CON-E4CON
tEDL
VOHB
tREC
RST
AI02399B
9/16
M40Z300, M40Z300W
Figure 7. Address-Decode Time
A, B
tAS
E
tEDL
tEDH or tEDL
E1CON-E4CON
AI02551
Note: During system design, compliance with the SRAM timing parameters must comprehend the propagation delay
between E and EXCON
Table 8. Battery Table
Part Number
Description
Package
M4Z28-BR00SH
Lithium Battery (48mAh) SNAPHAT
SH
M4Z32-BR00SH
Lithium Battery (120mAh) SNAPHAT
SH
VCC NOISE AND NEGATIVE GOING TRANSIENTS
ICC transients, including those produced by output
switching, can produce voltage fluctuations, resulting in spikes on the VCC bus. These transients
can be reduced if capacitors are used to store energy, which stabilizes the V CC bus. The energy
stored in the bypass capacitors will be released as
low going spikes are generated or energy will be
absorbed when overshoots occur.
A ceramic bypass capacitor value of 0.1µF (as
shown in figure 8) is recommended in order to provide the needed filtering.
In addition to transients that are caused by normal
SRAM operation, power cycling can generate negative voltage spikes on V CC that drive it to values
below V SS by as much as one volt. These negative
spikes can cause data corruption in the SRAM
while in battery backup mode. To protect from
these voltage spikes, STMicroelectronics recommends connecting a schottky diode from VCC to
VSS (cathode connected to VCC, anode to VSS).
Schottky diode 1N5817 is recommended for
through hole and MBRS120T3 is recommended
for surface mount.
10/16
Figure 8. Supply Voltage Protection
VCC
VCC
0.1µF
DEVICE
VSS
AI00622
M40Z300, M40Z300W
Table 9. Ordering Information Scheme
Example:
M40Z300W
MH
1
TR
Supply Voltage and Write Protect Voltage
300 = VCC = 4.5V to 5.5V
THS = VSS 4.5V ≤ VPFD ≤ 4.75V
THS = VOUT 4.2V ≤ VPFD ≤ 4.5V
300W = VCC = 3.0V to 3.6V
THS = VSS 2.8V ≤ VPFD ≤ 3.0V
VCC = 2.7V to 3.3V
THS = VOUT 2.5V ≤ VPFD ≤ 2.7V
Package
MH(1,2) = SOH28
MQ = SO16
Temperature Range
1 = 0 to 70 °C
Shipping Method for SOIC
blank = Tubes
TR = Tape & Reel
Note: 1. The SOIC package (SOH28) requires the battery package (SNAPHAT) which is ordered separately under the part number
“M4Zxx-BR00SH1" in plastic tube or "M4Zxx-BR00SH1TR" in Tape & Reel form.
2. Delivery may include either the 2-pin version of the SOIC/SNAPHAT or the 4-pin version of the SOIC/SNAPHAT. Both are functionally equivalent (see package drawing section for details).
Caution: Do not place the SNAPHAT battery package "M4Zxx-BR00SH1" in conductive foam since will drain the lithium button-cell battery.
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you.
Table 10. Revision History
Date
Revision Details
March 1999
First Issue
03/08/00
Document Layout changed
SO16 package added
Battery Capacity changed (Table 8)
11/16
M40Z300, M40Z300W
Table 11. SOH28 - 28 lead Plastic Small Outline, battery SNAPHAT, Package Mechanical Data
mm
inches
Symb
Typ
Min
Max
A
Typ
Min
3.05
Max
0.120
A1
0.05
0.36
0.002
0.014
A2
2.34
2.69
0.092
0.106
B
0.36
0.51
0.014
0.020
C
0.15
0.32
0.006
0.012
D
17.71
18.49
0.697
0.728
E
8.23
8.89
0.324
0.350
–
–
–
–
eB
3.20
3.61
0.126
0.142
H
11.51
12.70
0.453
0.500
L
0.41
1.27
0.016
0.050
α
0°
8°
0°
8°
N
28
e
1.27
0.050
28
CP
0.10
0.004
Figure 9. SOH28 - 28 lead Plastic Small Outline, 4-socket battery SNAPHAT, Package Outline
A2
A
C
B
eB
e
CP
D
N
E
H
A1
1
SOH-A
Drawing is not to scale.
12/16
α
L
M40Z300, M40Z300W
Table 12. M4Z28-BR00SH SNAPHAT Housing for 48 mAh Battery, Package Mechanical Data
mm
inches
Symb
Typ
Min
A
Max
Typ
Min
Max
9.78
0.385
A1
6.73
7.24
0.265
0.285
A2
6.48
6.99
0.255
0.275
A3
0.38
0.015
B
0.46
0.56
0.018
0.022
D
21.21
21.84
0.835
0.860
E
14.22
14.99
0.560
0.590
eA
15.55
15.95
0.612
0.628
eB
3.20
3.61
0.126
0.142
L
2.03
2.29
0.080
0.090
Figure 10. M4Z28-BR00SH SNAPHAT Housing for 48 mAh Battery, Package Outline
A1
eA
A2
A
A3
B
L
eB
D
E
SHZP-A
Drawing is not to scale.
13/16
M40Z300, M40Z300W
Table 13. M4Z32-BR00SH SNAPHAT Housing for 120 mAh Battery, Package Mechanical Data
mm
inches
Symb
Typ
Min
A
Max
Typ
Min
Max
10.54
0.415
A1
8.00
8.51
0.315
.0335
A2
7.24
8.00
0.285
0.315
A3
0.38
0.015
B
0.46
0.56
0.018
0.022
D
21.21
21.84
0.835
0.860
E
17.27
18.03
0.680
.0710
eA
15.55
15.95
0.612
0.628
eB
3.20
3.61
0.126
0.142
L
2.03
2.29
0.080
0.090
Figure 11. M4Z32-BR00SH SNAPHAT Housing for 120 mAh Battery, Package Outline
A1
eA
A2
A
A3
B
L
eB
D
E
SHZP-A
Drawing is not to scale.
14/16
M40Z300, M40Z300W
Table 14. SO16 - 16 lead Plastic Small Outline, 300 mils body width
mm
inches
Symb.
Typ.
Min.
A
Max.
Typ.
Min.
2.59
Max.
0.102
A1
0.10
0.30
0.004
0.012
B
0.38
0.51
0.015
0.020
C
0.23
0.25
0.009
0.010
D
10.11
10.49
0.398
0.413
E
7.44
7.54
0.293
0.297
–
–
–
–
10.16
10.41
0.400
0.410
e
1.27
H
h
0.38
0.050
0.015
L
0.41
1027
0.016
0.050
α
0°
8°
0°
8°
N
16
CP
16
0.10
0.004
Figure 12. SO16 - 16 lead Plastic Small Outline, 300 mils body width, Package Outline
h x 45˚
A
C
B
CP
e
D
N
E
H
1
A1
α
L
SO-a
Drawing is not to scale.
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M40Z300, M40Z300W
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