STMICROELECTRONICS M48Z129V

M48Z129Y
M48Z129V
3.3V/5V 1 Mbit (128Kb x8) ZEROPOWER® SRAM
■
INTEGRATED ULTRA LOW POWER SRAM,
POWER-FAIL CONTROL CIRCUIT, and
BATTERY
■
AUTOMATIC POWER-FAIL CHIP DESELECT
AND WRITE PROTECTION
■
MICROPROCESSOR POWER-ON RESET
(RESET VALID EVEN DURING BATTERY
BACK-UP MODE)
■
BATTERY LOW PIN - PROVIDES WARNING
OF BATTERY END-OF-LIFE
■
WRITE PROTECT VOLTAGES
(VPFD = Power-fail Deselect Voltage):
– M48Z129Y: 4.2V ≤ VPFD ≤ 4.5V
– M48Z129V: 2.7V ≤ VPFD ≤ 3.0V
■
CONVENTIONAL SRAM OPERATION;
UNLIMITED WRITE CYCLES
■
10 YEARS OF DATA RETENTION IN THE
ABSENCE OF POWER
■
PIN AND FUNCTION COMPATIBLE WITH
JEDEC STANDARD 128Kb x 8 SRAMS
■
SELF CONTAINED BATTERY IN DIP
PACKAGE
32
1
PMDIP32 (PM)
Module
Figure 1. Logic Diagram
VCC
17
Table 1. Signal Names
A0-A16
Address Inputs
DQ0-DQ7
Data Inputs / Outputs
E
Chip Enable
G
Output Enable
W
Write Enable
RST
Reset Output (Open Drain)
BL
Battery Low Output (Open
Drain)
VCC
Supply Voltage
VSS
Ground
8
A0-A16
W
DQ0-DQ7
M48Z129Y
M48Z129V
E
RST
BL
G
June 2000
VSS
AI02309
1/13
M48Z129Y, M48Z129V
Table 2. Absolute Maximum Ratings (1)
Symbol
Parameter
Value
Unit
TA
Ambient Operating Temperature
0 to 70
°C
TSTG
Storage Temperature (VCC Off)
–40 to 70
°C
TBIAS
Temperature Under Bias
–10 to 70
°C
TSLD (2)
Lead Solder Temperature for 10 seconds
260
°C
–0.3 to VCC+0.3
V
–0.3 to 7.0
–0.3 to 4.6
V
VIO
Input or Output Voltages
Supply Voltage
VCC
M48Z129Y
M48Z129V
Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational section
of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect
reliability.
2. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).
CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.
Figure 2A. DIP Pin Connections
RST
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
32
1
31
2
30
3
29
4
28
5
27
6
26
7
8 M48Z129Y 25
9 M48Z129V 24
23
10
22
11
21
12
20
13
19
14
18
15
17
16
VCC
A15
BL
W
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
AI02310
DESCRIPTION
The M48Z129Y/V ZEROPOWER SRAM is a
1,048,576 bit non-volatile static RAM organized as
131,072 words by 8 bits. The device combines an
internal lithium battery, a CMOS SRAM and a control circuit in a plastic 32 pin DIP Module. The
M48Z129Y/V directly replaces industry standard
2/13
128K x 8 SRAM. It also provides the non-volatility
of FLASH without any requirement for special
write timing or limitations on the number of writes
that can be performed.
The M48Z129Y/V also has its own Power-Fail Detect circuit. This control circuitry constantly monitors the supply voltage for an out of tolerance
condition. When V CC is out of tolerance, the circuit
write protects the SRAM, providing data security in
the midst of unpredictable system operation. As
VCC falls, the control circuitry automatically switches to the battery, maintaining data until valid power
is restored.
READ MODE
The M48Z129Y/V is in the Read Mode whenever
W (Write Enable) is high and E (Chip Enable) is
low. The unique address specified by the 17 Address Inputs defines which one of the 131,072
bytes of data is to be accessed. Valid data will be
available at the Data I/O pins within tAVQV (Address Access Time) after the last address input
signal is stable, providing the E and G access
times are also satisfied. If the E and G access
times are not met, valid data will be available after
the latter of the Chip Enable Access Times (tELQV)
or Output Enable Access Time (tGLQV).
The state of the eight three-state Data I/O signals
is controlled by E and G. If the outputs are activated before t AVQV, the data lines will be driven to an
indeterminate state until t AVQV. If the Address Inputs are changed while E and G remain active,
output data will remain valid for tAXQX (Output
Data Hold Time) but will go indeterminate until the
next Address Access.
M48Z129Y, M48Z129V
Table 3. Operating Modes (1)
VCC
Mode
Deselect
4.5V to 5.5V
(M48Z129Y)
or
3.0V to 3.6V
(M48Z129V)
Write
Read
Read
E
G
W
DQ0-DQ7
Power
VIH
X
X
High Z
Standby
VIL
X
VIL
DIN
Active
VIL
VIL
VIH
DOUT
Active
VIL
VIH
VIH
High Z
Active
Deselect
VSO to VPFD (min) (2)
X
X
X
High Z
CMOS Standby
Deselect
≤ VSO (2)
X
X
X
High Z
Battery Back-up Mode
Note: 1. X = VIH or VIL; VSO = Battery Back-up Switchover Voltage.
2. See Table 7 for details.
Figure 3. Block Diagram
VCC
A0-A16
POWER
E
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
131,072 x 8
SRAM ARRAY
E
DQ0-DQ7
W
G
INTERNAL
BATTERY
RST
BL
WRITE MODE
The M48Z129Y/V is in the Write Mode whenever
W (Write Enable) and E (Chip Enable) are active.
The start of a write is referenced from the latter occurring falling edge of W or E. A write is terminated by the earlier rising edge of W or E. The
addresses must be held valid throughout the cycle.
E or W must return high for a minimum of tEHAX
from Chip Enable or tWHAX from Write Enable prior
to the initiation of another read or write cycle.
Data-in must be valid tDVWH prior to the end of
write and remain valid for tWHDX afterward. G
should be kept high during write cycles to avoid
VSS
AI03608
bus contention; although, if the output bus has
been activated by a low on E and G a low on W
will disable the outputs t WLQZ after W falls.
DATA RETENTION MODE
With valid V CC applied, the M48Z129Y/V operates
as a conventional BYTEWIDE static RAM. Should
the supply voltage decay, the RAM will automatically deselect, write protecting itself when V CC
falls between VPFD (max), VPFD (min) window. All
outputs become high impedance and all inputs are
treated as “don’t care”.
3/13
M48Z129Y, M48Z129V
Figure 4. AC Testing Load Circuit
Table 4. AC Measurement Conditions
Input Rise and Fall Times
Input Pulse Voltages
Input and Output Timing Ref. Voltages
≤ 5ns
0 to 3V
1.5V
Note that Output Hi-Z is defined as the point where data is no longer
driven.
Note: A power failure during a write cycle may
corrupt data at the current addressed location, but
does not jeopardize the rest of the RAM’s content.
At voltages below V PFD(min), the memory will be
in a write protected state, provided the V CC fall
time is not less than t F. The M48Z129Y/V may respond to transient noise spikes on VCC that cross
into the deselect window during the time the device is sampling VCC. Therefore, decoupling of the
power supply lines is recommended.
When V CC drops below VSO, the control circuit
switches power to the internal battery, preserving
data. The internal energy source will maintain
data in the M48Z129Y/V for an accumulated period of at least 10 years at room temperature. As
system power rises above V SO, the battery is disconnected, and the power supply is switched to
external VCC. Deselect continues for tREC after
VCC reaches V PFD(max).
For more information on Battery Storage Life refer
to the Application Note AN1012.
POWER-ON RESET OUTPUT
All microprocessors have a reset input which forces them to a known state when starting. The
M48Z129Y/V has a reset output (RST) pin which
is guaranteed to be low below VPFD(min). This signal is an open drain configuration. An appropriate
pull-up resistor should be chosen to control the
rise time. This signal will be valid for all voltage
conditions, even when VCC equals VSS. Once VCC
exceeds the power failure detect voltage VPFD, an
internal timer keeps RST low for tREC to allow the
power supply to stabilize.
BATTERY LOW PIN
The M48Z129Y/V automatically performs battery
voltage monitoring upon power-up, and at factory-
4/13
650Ω
DEVICE
UNDER
TEST
CL = 100pF
or 50pF(1)
CL includes JIG capacitance
1.75V
AI03630
Note: 1. 50pF for M48Z129V (3.3V).
programmed time intervals of 24 hours. The Battery Low (BL) pin will be asserted if the battery voltage is found to be less than approximately 2.5V. If
a battery low is generated during a power-up sequence, this indicates that the battery is below 2.5
volts and may not be able to maintain data integrity
in the SRAM. Data should be considered suspect,
and verified as correct.
If a battery low indication is generated during the
24-hour interval check, this indicates that the battery is near end of life. However, data is not compromised due to the fact that a nominal V CC is
supplied.
The M48Z129Y/V only monitors the battery when
a nominal V CC is applied to the device. Thus applications which require extensive durations in the
battery back-up mode should be powered-up periodically (at least once every few months) in order
for this technique to be beneficial. Additionally, if
a battery low is indicated, data integrity should be
verified upon power-up via a checksum or other
technique. The BL pin is an open drain output and
an appropriate pull-up resistor should be chosen
to control the rise time.
M48Z129Y, M48Z129V
Table 5. Capacitance (1)
(TA = 25 °C, f = 1 MHz)
Symbol
CIN
CIO (2)
Parameter
Test Condition
Input Capacitance
Input / Output Capacitance
Min
Max
Unit
VIN = 0V
10
pF
VOUT = 0V
10
pF
Note: 1. Effective capacitance measured with power supply at 5V.
2. Outputs deselected.
Table 6A. DC Characteristics
(TA = 0 to 70 °C; VCC = 4.5V to 5.5V)
Symbol
Parameter
ILI (1)
Input Leakage Current
ILO (1)
Output Leakage Current
Test Condition
Min
Max
Unit
0V ≤ VIN ≤ VCC
±1
µA
0V ≤ VOUT ≤ VCC
±1
µA
Outputs open
95
mA
E = VIH
7
mA
E = VCC – 0.2V
4
mA
ICC
Supply Current
ICC1
Supply Current (Standby) TTL
ICC2
Supply Current (Standby) CMOS
VIL
Input Low Voltage
–0.3
0.8
V
VIH
Input High Voltage
2.2
VCC + 0.3
V
VOL
Output Low Voltage
IOL = 2.1mA
0.4
V
VOH
Output High Voltage
IOH = –1mA
2.4
Test Condition
Min
V
Note: 1. Outputs deselected.
Table 6B. DC Characteristics
(TA = 0 to 70 °C; VCC = 3.0V to 3.6V)
Symbol
Parameter
ILI (1)
Input Leakage Current
ILO (1)
Output Leakage Current
Max
Unit
0V ≤ VIN ≤ VCC
±1
µA
0V ≤ VOUT ≤ VCC
±1
µA
Outputs open
50
mA
E = VIH
4
mA
E = VCC – 0.2V
3
mA
ICC
Supply Current
ICC1
Supply Current (Standby) TTL
ICC2
Supply Current (Standby) CMOS
VIL
Input Low Voltage
–0.3
0.6
V
VIH
Input High Voltage
2.2
VCC + 0.3
V
VOL
Output Low Voltage
IOL = 2.1mA
0.4
V
VOH
Output High Voltage
IOH = –1mA
2.2
V
Note: 1. Outputs deselected.
5/13
M48Z129Y, M48Z129V
Table 7. Power Down/Up Trip Points DC Characteristics (1)
(TA = 0 to 70 °C)
Symbol
VPFD
VSO
tDR (2)
Parameter
Min
Typ
Max
Power-fail Deselect Voltage (M48Z129Y)
4.2
4.35
4.5
Power-fail Deselect Voltage (M48Z129V)
2.7
2.9
3.0
Unit
V
Battery Back-up Switchover Voltage (M48Z129Y)
3.0
Battery Back-up Switchover Voltage (M48Z129V)
2.45
V
Expected Data Retention Time
10
YEARS
Note: 1. All voltages referenced to VSS.
2. At 25 °C.
Table 8. Power Down/Up AC Characteristics
(TA = 0 to 70 °C)
Symbol
tF (1)
Parameter
Min
Max
Unit
VPFD (max) to VPFD (min) VCC Fall Time
300
VPFD (min) to VSS VCC Fall Time (M48Z129Y)
10
VPFD (min) to VSS VCC Fall Time (M48Z129V)
150
tR
VPFD (min) to VPFD (max) VCC Rise Time
10
µs
tRB
VSS to VPFD (min) VCC Rise Time
1
µs
Write Protect Time (M48Z129Y)
40
150
Write Protect Time (M48Z129V)
40
250
VPFD (max) to RST High
40
200
tFB (2)
tWPT
tREC
µs
µs
µs
ms
Note: 1. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200µs after VCC passes V PFD (min).
2. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
6/13
M48Z129Y, M48Z129V
Figure 5. Power Down/Up Mode AC Waveforms
VCC
VPFD (max)
VPFD (min)
VSO
tF
tR
tFB
tREC
tRB
tWPT
E
RECOGNIZED
DON'T CARE
RECOGNIZED
HIGH-Z
OUTPUTS
VALID
VALID
(PER CONTROL INPUT)
(PER CONTROL INPUT)
RST
AI03610
Table 9. Read Mode AC Characteristics
(TA = 0 to 70 °C; VCC = 4.5V to 5.5V or 3.0V to 3.6V)
Symbol
M48Z129Y
M48Z129V
-70
-85
Parameter
Min
tAVAV
Read Cycle Time
Max
70
Min
Unit
Max
85
ns
tAVQV (1)
Address Valid to Output Valid
70
85
ns
tELQV (1)
Chip Enable Low to Output Valid
70
85
ns
tGLQV (1)
Output Enable Low to Output Valid
35
45
ns
tELQX (2)
Chip Enable Low to Output Transition
5
5
ns
tGLQX (2)
Output Enable Low to Output Transition
3
5
ns
tEHQZ (2)
Chip Enable High to Output Hi-Z
30
40
ns
tGHQZ (2)
Output Enable High to Output Hi-Z
20
25
ns
tAXQX (1)
Address Transition to Output Transition
5
5
ns
Note: 1. CL = 100pF or 50pF (see Figure 4).
2. CL = 5pF (see Figure 4).
7/13
M48Z129Y, M48Z129V
Figure 6. Address Controlled, Read Mode AC Waveforms.
tAVAV
VALID
A0-A16
tAVQV
tAXQX
DQ0-DQ7
DATA VALID
DATA VALID
AI02324
Note: Chip Enable (E) and Output Enable (G) = Low, Write Enable (W) = High.
Figure 7. Chip Enable or Output Enable Controlled, Read Mode AC Waveform
tAVAV
VALID
A0-A16
tAVQV
tAXQX
tELQV
tEHQZ
E
tELQX
tGLQV
tGHQZ
G
tGLQX
DQ0-DQ7
DATA OUT
AI01197
8/13
M48Z129Y, M48Z129V
Table 10. Write Mode AC Characteristics
(TA = 0 to 70 °C; VCC = 4.5V to 5.5V or 3.0V to 3.6V)
Symbol
M48Z129Y
M48Z129V
-70
-85
Parameter
Min
Max
Min
Unit
Max
tAVAV
Write Cycle Time
70
85
ns
tAVWL
Address Valid to Write Enable Low
0
0
ns
tAVEL
Address Valid to Chip Enable Low
0
0
ns
tWLWH
Write Enable Pulse Width
55
65
ns
tELEH
Chip Enable Low to Chip Enable High
55
75
ns
tWHAX
Write Enable High to Address Transition
5
5
ns
tEHAX
Chip Enable High to Address Transition
15
15
ns
tDVWH
Input Valid to Write Enable High
30
35
ns
tDVEH
Input Valid to Chip Enable High
30
35
ns
tWHDX
Write Enable High to Input Transition
0
0
ns
tEHDX
Chip Enable High to Input Transition
10
15
ns
tWLQZ (1, 2)
Write Enable Low to Output Hi-Z
25
30
ns
tAVWH
Address Valid to Write Enable High
65
75
ns
tAVEH
Address Valid to Chip Enable High
65
75
ns
Write Enable High to Output Transition
5
5
ns
tWHQX (1, 2)
Note: 1. CL = 5pF (see Figure 4).
2. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
Figure 8. Write Enable Controlled, Write AC Waveforms
tAVAV
VALID
A0-A16
tAVWH
tWHAX
tAVEL
E
tWLWH
tAVWL
W
tWLQZ
tWHQX
tWHDX
DQ0-DQ7
DATA INPUT
tDVWH
AI02382
9/13
M48Z129Y, M48Z129V
Figure 9. Chip Enable Controlled, Write AC Waveforms
tAVAV
VALID
A0-A16
tAVWH
tAVEL
tELEH
tEHAX
E
tWLWH
tAVWL
W
tDVWH
DQ0-DQ7
tWHDX
DATA INPUT
AI03611
Figure 10. Supply Voltage Protection
VCC
VCC
0.1µF
DEVICE
VSS
AI02169
10/13
POWER SUPPLY DECOUPLING AND
UNDERSHOOT PROTECTION
Icc transients, including those produced by output
switching, can produce voltage fluctuations, resulting in spikes on the V CC bus. These transients
can be reduced if capacitors are used to store energy, which stabilizes the VCC bus. The energy
stored in the bypass capacitors will be released as
low going spikes are generated or energy will be
absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1 microfarad is recommended in order to provide the needed filtering.
In addition to transients that are caused by normal
SRAM operation, power cycling can generate negative voltage spikes on V CC that drive it to values
below Vss by as much as one volt. These negative spikes can cause data corruption in the SRAM
while in battery backup mode. To protect from
these voltage spikes, it is recommended to connect a schottky diode from VCC to Vss (cathode
connected to VCC, anode to Vss). (Schottky diode
1N5817 is recommended for through hole and
MBRS120T3 is recommended for surface mount).
M48Z129Y, M48Z129V
Table 11. Ordering Information Scheme
Example:
M48Z129Y
-70 PM
1
Supply Voltage and Write Protect Voltage
129Y = VCC = 4.5V to 5.5V; VPFD = 4.2V to 4.5V
129V = VCC = 3.0V to 3.6V; VPFD = 2.7V to 3.0V
Speed
-70 = 70ns (M48Z129Y)
-85 = 85ns (M48Z129V)
Package
PM = PMDIP32
Temperature Range
1 = 0 to 70 °C
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you.
Table 12. Revision History
Date
Revision Details
December 1999
First Issue
03/30/00
From Preliminary Data to Data Sheet
06/20/00
tGLQX changed for M48Z129Y (Table 9)
11/13
M48Z129Y, M48Z129V
Table 13. PMDIP32 - 32 pin Plastic Module DIP, Package Mechanical Data
mm
inches
Symb
Typ
Min
Max
A
9.27
A1
Typ
Min
Max
9.52
0.365
0.375
0.38
–
0.015
–
B
0.43
0.59
0.017
0.023
C
0.20
0.33
0.008
0.013
D
42.42
43.18
1.670
1.700
E
18.03
18.80
0.710
0.740
e1
2.29
2.79
0.090
0.110
e3
34.29
41.91
1.350
1.650
eA
14.99
16.00
0.590
0.630
L
3.05
3.81
0.120
0.150
S
1.91
2.79
0.075
0.110
N
32
32
Figure 11. PMDIP32 - 32 pin Plastic Module DIP, Package Outline
A
A1
B
S
L
C
eA
e1
e3
D
N
E
1
Drawing is not to scale.
12/13
PMDIP
M48Z129Y, M48Z129V
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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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13/13