M40Z111 M40Z111W 5V OR 3V NVRAM SUPERVISOR FOR UP TO TWO LPSRAMs FEATURES SUMMARY ■ CONVERT LOW POWER SRAMs INTO NVRAMs ■ PRECISION POWER MONITORING and POWER SWITCHING CIRCUITRY ■ AUTOMATIC WRITE-PROTECTION WHEN VCC IS OUT-OF-TOLERANCE ■ CHOICE OF SUPPLY VOLTAGES and POWER-FAIL DESELECT VOLTAGES: – M40Z111: VCC = 4.5 to 5.5V THS = VSS; 4.5 ≤ VPFD ≤ 4.75V THS = VOUT; 4.2 ≤ VPFD ≤ 4.5V – M40Z111W: VCC = 3.0 to 3.6V THS = VSS; 2.8 ≤ VPFD ≤ 3.0V VCC = 2.7 to 3.3V THS = VOUT; 2.5 ≤ VPFD ≤ 2.7V LESS THAN 15ns CHIP ENABLE ACCESS PROPAGATION DELAY (for 5.0V device) ■ ■ PACKAGING INCLUDES A 28-LEAD SOIC and SNAPHAT® TOP (to be ordered separately) ■ SOIC PACKAGE PROVIDES DIRECT CONNECTION FOR A SNAPHAT TOP WHICH CONTAINS THE BATTERY May 2002 Figure 1. 28-pin SOIC Package SNAPHAT (SH) Battery 28 1 SOH28 (MH) 1/15 M40Z111, M40Z111W TABLE OF CONTENTS SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Logic Diagram (Figure 2.) . . . . . . . Signal Names (Table 1.) . . . . . . . . SOIC28 Connections (Figure 3.) . . Hardware Hookup (Figure 4.) . . . . ....... ....... ....... ....... ...... ...... ...... ...... ....... ....... ....... ....... ...... ...... ...... ...... ....... ....... ....... ....... ...... ...... ...... ...... ...... ...... ...... ...... .....3 .....3 .....3 .....4 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Absolute Maximum Ratings (Table 2.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 DC and AC Measurement Conditions (Table 3.) . . . AC Testing Load Circuit (Figure 5.) . . . . . . . . . . . . . Capacitance (Table 4.) . . . . . . . . . . . . . . . . . . . . . . DC Characteristics (Table 5.) . . . . . . . . . . . . . . . . . ....... ....... ....... ....... ...... ...... ...... ...... ....... ....... ....... ....... ...... ...... ...... ...... ...... ...... ...... ...... .....5 .....5 .....5 .....6 OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Data Retention Lifetime Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Power Down Timing (Figure 6.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Power Up Timing (Figure 7.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Power Down/Up AC Characteristics (Table 6.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 VCC Noise And Negative Going Transients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Supply Voltage Protection (Figure 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Battery Table (Table 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2/15 M40Z111, M40Z111W SUMMARY DESCRIPTION The M40Z111/W NVRAM SUPERVISOR is a selfcontained device which converts a standard lowpower SRAM into a non-volatile memory. A precision voltage reference and comparator monitors the VCC input for an out-of-tolerance condition. When an invalid VCC condition occurs, the conditioned chip enable (ECON) output is forced inactive to write-protect the stored data in the SRAM. During a power failure, the SRAM is switched from the VCC pin to the lithium cell within the SNAPHAT® to provide the energy required for data retention. On a subsequent power-up, the SRAM remains write protected until a valid power condition returns. The 28-pin, 330mil SOIC provides sockets with gold plated contacts at both ends for direct con- nection to a separate SNAPHAT housing containing the battery. The unique design allows the SNAPHAT battery package to be mounted on top of the SOIC package after the completion of the surface mount process. Insertion of the SNAPHAT housing after reflow prevents potential battery damage due to the high temperatures required for device surface-mounting. The SNAPHAT housing is keyed to prevent reverse insertion. The SOIC and battery packages are shipped separately in plastic anti-static tubes or in Tape & Reel form. For the 28-lead SOIC, the battery package (e.g., SNAPHAT) part number is “M4Z28BR00SH” or “M4Z32-BR00SH” (See Table 8, page 10). Figure 2. Logic Diagram Table 1. Signal Names THS VCC E THS VOUT M40Z111 M40Z111W E ECON Threshold Select Input Chip Enable Input ECON Conditioned Chip Enable Output VOUT Supply Voltage Output VCC Supply Voltage VSS Ground NC Not Connected Internally Figure 3. SOIC28 Connections VSS AI02238B VOUT NC NC NC NC VCC NC VCC NC NC NC NC THS VSS 1 28 27 2 26 3 25 4 24 5 23 6 7 M40Z111 22 8 M40Z111W 21 20 9 19 10 18 11 17 12 16 13 15 14 VCC E NC NC NC NC NC NC NC NC NC NC ECON NC AI02239B 3/15 M40Z111, M40Z111W Figure 4. Hardware Hookup 3.0, 3.3, or 5V VCC VOUT VCC E2 1N5817 or MBR5120T3 0.1µF CMOS SRAM 0.1µF M40Z111/W ECON E E Thereshold x8 or x16 THS VSS AI02394 MAXIMUM RATING Stressing the device above the rating listed in the “Absolute Maximum Ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 2. Absolute Maximum Ratings Symbol Parameter TA Ambient Operating Temperature TSTG Storage Temperature (VCC Off) TSLD(1) VIO Value Unit Grade 6 –40 to 85 °C SNAPHAT® –40 to 85 °C SOIC –55 to 125 °C 260 °C –0.3 to VCC +0.3 V M40Z111 –0.3 to 7.0 V M40Z111W –0.3 to 4.6 V Lead Solder Temperature for 10 seconds Input or Output Voltages Supply Voltage VCC IO Output Current 20 mA PD Power Dissipation 1 W Note: 1. Reflow at peak temperature of 215°C to 225°C for < 60 seconds (total thermal budget not to exceed 180°C for between 90 to 120 seconds). CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode. CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets. 4/15 M40Z111, M40Z111W DC AND AC PARAMETERS This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the Measure- ment Conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. Table 3. DC and AC Measurement Conditions Parameter M40Z111 M40Z111W VCC Supply Voltage 4.5 to 5.5V 2.7 to 3.6V Ambient Operating Temperature –40 to 85°C –40 to 85°C Load Capacitance (CL) 100pF 50pF Input Rise and Fall Times ≤ 5ns ≤ 5ns 0 to 3V 0 to 3V 1.5V 1.5V Input Pulse Voltages Input and Output Timing Ref. Voltages Note: Note that Output Hi-Z is defined as the point where data is no longer driven. Figure 5. AC Testing Load Circuit 645Ω DEVICE UNDER TEST (1) CL = 100pF or 5pF CL includes JIG capacitance 1.75V AI02326 Note: 1. 50pF for M40Z111W. Table 4. Capacitance Parameter(1,2) Symbol CIN COUT(3) Min Max Unit Input Capacitance 8 pF Output Capacitance 10 pF Note: 1. Effective capacitance measured with power supply at 5V (M40Z111) or 3.3V (M40Z111W); sampled only, not 100% tested. 2. At 25°C, f = 1MHz. 3. Outputs deselected 5/15 M40Z111, M40Z111W Table 5. DC Characteristics Sym ICC Parameter Supply Current ICCDR Data Retention Mode Current ILI Input Leakage Current ILO(2) Output Leakage Current IOUT1 VOUT Current (Active) Test Condition(1) M40Z111 Min Max 2 4 mA 150 150 nA 0V ≤ VIN ≤ VCC ±1 ±1 µA 0V ≤ VOUT ≤ VCC ±1 ±1 µA VOUT > VCC –0.3 160 100 mA VOUT > VCC –0.2 100 65 mA Outputs open VOUT Current (Battery Back-up) VBAT Battery Voltage 2.0 VIH Input High Voltage VIL Input Low Voltage VOH Output High Voltage IOH = –2.0mA 2.4 VOHB VOH Battery Back-up IOUT2 = –1.0µA 2.0 VOL Output Low Voltage IOL = 4.0mA THS Threshold Select Voltage VSS Power-fail Deselect Voltage (THS = VSS) 4.50 Power-fail Deselect Voltage (THS = VOUT) 4.20 VSO Battery Back-up Switchover Voltage VOUT > VBAT –0.3 Typ Max 3 6 Min 100 3.0 100 3.5 2.0 2.2 VCC + 0.3 –0.3 0.8 3.0 µA 3.5 V 2.0 VCC + 0.3 V –0.3 0.8 V 2.4 2.9 3.6 2.0 V 2.9 0.4 3.6 V 0.4 V VOUT V VOUT VSS 4.60 4.75 2.80 2.90 3.00 V 4.35 4.50 2.50 2.60 2.70 V 3.0 VPFD – 100mV Note: 1. Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 4.5 to 5.5V or 2.7 to 3.6V (except where noted). 2. Outputs deselected. 6/15 Unit Typ IOUT2 VPFD M40Z111W V M40Z111, M40Z111W OPERATION The M40Z111/W, as shown in Figure 4, page 4, can control up to two standard low-power SRAMs. These SRAMs must be configured to have the chip enable input disable all other input signals. Most slow, low-power SRAMs are configured like this, however many fast SRAMs are not. During normal operating conditions, the conditioned chip enable (ECON) output pin follows the chip enable (E) input pin with timing shown in Table 6, page 9. An internal switch connects VCC to VOUT. This switch has a voltage drop of less than 0.3V (IOUT1). When VCC degrades during a power failure, ECON is forced inactive independent of E. In this situation, the SRAM is unconditionally write protected as VCC falls below an out-of-tolerance threshold (VPFD). The power fail detection value associated with VPFD is selected by the THS pin and is shown in Table 5, page 6. Note: The THS pin must be connected to either VSS or VOUT. If chip enable access is in progress during a power fail detection, that memory cycle continues to completion before the memory is write protected. If the memory cycle is not terminated within time tWP, ECON is unconditionally driven high, write protecting the SRAM. A power failure during a write cycle may corrupt data at the currently addressed location, but does not jeopardize the rest of the SRAM's contents. At voltages below VPFD (min), the user can be assured the memory will be write protected provided the VCC fall time exceeds tF. As VCC continues to degrade, the internal switch disconnects VCC and connects the internal battery to VOUT. This occurs at the switchover voltage (VSO ). Below the VSO, the battery provides a voltage VOHB to the SRAM and can supply current IOUT2 (see Table 5, page 6). When VCC rises above VSO, VOUT is switched back to the supply voltage. Output ECON is held inactive for tER (200ms maximum) after the power supply has reached VPFD, independent of the E input, to allow for processor stabilization (see Figure 7, page 8). Data Retention Lifetime Calculation Most low power SRAMs on the market today can be used with the M40Z111/W NVRAM SUPERVISOR. There are, however some criteria which should be used in making the final choice of which SRAM to use. The SRAM must be designed in a way where the chip enable input disables all other inputs to the SRAM. This allows inputs to the M40Z111/W and SRAMs to be “Don't Care” once VCC falls below VPFD (min). The SRAM should also guarantee data retention down to VCC = 2.0V. The chip enable access time must be sufficient to meet the system needs with the chip enable propagation delays included. If the SRAM includes a second chip enable pin (E2), this pin should be tied to VOUT. If data retention lifetime is a critical parameter for the system, it is important to review the data retention current specifications for the particular SRAMs being evaluated. Most SRAMs specify a data retention current at 3.0V. Manufacturers generally specify a typical condition for room temperature along with a worst case condition (generally at elevated temperatures). The system level requirements will determine the choice of which value to use. The data retention current value of the SRAMs can then be added to the ICCDR value of the M40Z111/W to determine the total current requirements for data retention. The available battery capacity for the SNAPHAT® of your choice can then be divided by this current to determine the amount of data retention available (see Table 8, page 10). For more information on Battery Storage Life refer to the Application Note AN1012. 7/15 M40Z111, M40Z111W Figure 6. Power Down Timing VCC VPFD (max) VPFD VPFD (min) VSO tF tFB E tWPT VOHB ECON AI02396 Figure 7. Power Up Timing VCC VPFD (max) VPFD VPFD (min) VSO tR tRB tER E tEDH ECON tEDL VOHB AI02397 8/15 M40Z111, M40Z111W Table 6. Power Down/Up AC Characteristics Parameter(1) Symbol Min Max Unit tF(2) VPFD (max) to VPFD (min) VCC Fall Time 300 µs tFB(3) VPFD (min) to VSS VCC Fall Time 10 µs tR VPFD (min) to VPFD (max) VCC Rise Time 10 µs tRB VSS to VPFD (min) VCC Rise Time 1 µs tEDL Chip Enable Propagation Delay tEDH Chip Enable Propagation Delay tER(4) Chip Enable Recovery tWPT Write Protect Time M40Z111 15 ns M40Z111W 20 ns M40Z111 10 ns M40Z111W 20 ns 40 200 ms M40Z111 40 150 µs M40Z111W 40 250 µs Note: 1. Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 4.5 to 5.5V or 2.7 to 3.6V (except where noted). 2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200 µs after VCC passes VPFD (min). 3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data. 4. tER (min) = 20ms for Industrial Temperature Range - Grade 6 device. VCC Noise And Negative Going Transients ICC transients, including those produced by output switching, can produce voltage fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if capacitors are used to store energy which stabilizes the VCC bus. The energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1µF (as shown in Figure 8) is recommended in order to provide the needed filtering. In addition to transients that are caused by normal SRAM operation, power cycling can generate negative voltage spikes on VCC that drive it to values below VSS by as much as one volt. These negative spikes can cause data corruption in the SRAM while in battery backup mode. To protect from these voltage spikes, STMicroelectronics recommends connecting a schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS). Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is recommended for surface mount. Figure 8. Supply Voltage Protection VCC VCC 0.1µF DEVICE VSS AI00622 9/15 M40Z111, M40Z111W PART NUMBERING Table 7. Ordering Information Scheme Example: M40Z 111W MH 6 TR Device Type M40Z Supply Voltage and Write Protect Voltage 111 = VCC = 4.5 to 5.5V; VPFD = 4.3 to 4.5V THS = VSS = 4.5 ≤ VPFD ≤ 4.75V THS = VOUT = 4.2 ≤ VPFD ≤ 4.5V 111W = VCC = 2.7 to 3.6V; VPFD = 2.6 to 2.7V THS = VSS = 2.8 ≤ VPFD ≤ 3.0V VCC = 2.7 to 3.3V THS = VOUT = 2.5 ≤ VPFD ≤ 2.7V Package MH(1) = SOH28 Temperature Range 6 = –40 to 85°C Shipping Method for SOIC blank = Tubes TR = Tape & Reel Note: 1. The SOIC package (SOH28) requires the battery package (SNAPHAT ®) which is ordered separately under the part number “M4ZXX-BR00SHX” in plastic tube or “M4ZXX-BR00SHXTR” in Tape & Reel form. Caution: Do not place the SNAPHAT battery package “M4ZXX-BR00SH” in conductive foam as this will drain the lithium button-cell battery. For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you. Table 8. Battery Table Part Number Description Package M4Z28-BR00SH SNAPHAT Housing for 48mAh Battery SH M4Z32-BR00SH SNAPHAT Housing for 120mAh Battery SH 10/15 M40Z111, M40Z111W PACKAGE MECHANICAL INFORMATION Figure 9. SOH28 – 28-lead Plastic Small Outline, 4-socket battery SNAPHAT, Package Outline A2 A C B eB e CP D N E H A1 α L 1 SOH-A Note: Drawing is not to scale. Table 9. SOH28 – 28-lead Plastic Small Outline, battery SNAPHAT, Package Mechanical Data mm inches Symbol Typ Min A Max Typ Min 3.05 Max 0.120 A1 0.05 0.36 0.002 0.014 A2 2.34 2.69 0.092 0.106 B 0.36 0.51 0.014 0.020 C 0.15 0.32 0.006 0.012 D 17.71 18.49 0.697 0.728 E 8.23 8.89 0.324 0.350 – – – – eB 3.20 3.61 0.126 0.142 H 11.51 12.70 0.453 0.500 L 0.41 1.27 0.016 0.050 α 0° 8° 0° 8° N 28 e CP 1.27 0.050 28 0.10 0.004 11/15 M40Z111, M40Z111W Figure 10. 4-pin SNAPHAT Housing for 48mAh Battery, Package Outline A1 A2 A eA A3 B L eB D E SHZP-A Note: Drawing is not to scale. Table 10. 4-pin SNAPHAT Housing for 48mAh Battery, Package Mechanical Data mm inches Symbol Typ Min A Typ Min 9.78 Max 0.385 A1 6.73 7.24 0.265 0.285 A2 6.48 6.99 0.255 0.275 A3 12/15 Max 0.38 0.015 B 0.46 0.56 0.018 0.022 D 21.21 21.84 0.835 0.860 E 14.22 14.99 0.560 0.590 eA 15.55 15.95 0.612 0.628 eB 3.20 3.61 0.126 0.142 L 2.03 2.29 0.080 0.090 M40Z111, M40Z111W Figure 11. 4-pin SNAPHAT Housing for 120mAh Battery, Package Outline A1 A2 A eA A3 B L eB D E SHZP-A Note: Drawing is not to scale. Table 11. 4-pin SNAPHAT Housing for 120mAh Battery, Package Mechanical Data mm inches Symbol Typ Min A Max Typ Min 10.54 Max 0.415 A1 8.00 8.51 0.315 0.335 A2 7.24 8.00 0.285 0.315 A3 0.38 0.015 B 0.46 0.56 0.018 0.022 D 21.21 21.84 0.835 0.860 E 17.27 18.03 0.680 0.710 eA 15.55 15.95 0.612 0.628 eB 3.20 3.61 0.126 0.142 L 2.03 2.29 0.080 0.090 13/15 M40Z111, M40Z111W REVISION HISTORY Table 12. Document Revision History Date September 2000 Revision Details First Draft Issue 09/14/01 Reformatted, TOC added, changed DC Characteristics (Table 5); changed battery, ind. temperature information (Tables 2, 6, 7, 8, Figures 10, 11); Corrected SOIC label (Figure 3); added E2 to Hookup (Figure 4) 05/13/02 Modify reflow time and temperature footnote (Table 2) 14/15 M40Z111, M40Z111W Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners. © 2002 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. www.st.com 15/15