STMICROELECTRONICS M48Z32V

M48Z32V
3.3V, 256 Kbit (32 Kbit x 8) ZEROPOWER® SRAM
FEATURES SUMMARY
■ INTEGRATED, ULTRA LOW POWER SRAM,
and POWER-FAIL CONTROL CIRCUIT
■
READ CYCLE TIME EQUALS WRITE CYCLE
TIME
■
AUTOMATIC POWER-FAIL CHIP DESELECT
and WRITE PROTECTION
■
WRITE PROTECT VOLTAGES:
(VPFD = Power-fail Deselect Voltage)
– M48Z32V: 2.7V ≤ VPFD ≤ 3.0V
■
Figure 2. 44-pin, Hatless SOIC Package
44
1
SOH44 (MT)
ULTRA-LOW STANDBY CURRENT
Figure 1. Logic Diagram
VCC
Table 1. Signal Names
B+
A0-A14
15
A0-A14
W
DQ0-DQ7
8
DQ0-DQ7
M48Z32V
Address Inputs
Data Inputs / Outputs
E
Chip Enable Input
G
Output Enable Input
W
WRITE Enable Input
E
G
VSS
November 2002
VCC
Supply Voltage
VSS
Ground
B+
Positive Battery Pin
NC
Not Connected
AI04787
1/16
M48Z32V
TABLE OF CONTENTS
DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
SOIC Connections (Figure 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Block Diagram (Figure 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Absolute Maximum Ratings (Table 2.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Operating and AC Measurement Conditions (Table 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
AC Measurement Load Circuit (Figure 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Capacitance (Table 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
DC Characteristics (Table 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Operating Modes (Table 6.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
READ Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
READ Mode AC Waveforms (Figure 6.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
READ Mode AC Characteristics (Table 7.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
WRITE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
WRITE Enable Controlled, WRITE Mode AC Waveforms (Figure 7.) . . . . . . . . . . . . . . . . . . . . . . . . 9
Chip Enable Controlled, WRITE Mode AC Waveforms (Figure 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . 9
WRITE Mode AC Characteristics (Table 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Data Retention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Power Down/Up Mode AC Waveforms (Figure 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Power Down/Up AC Characteristics (Table 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Power Down/Up Trip Points DC Characteristics (Table 10.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
VCC Noise And Negative Going Transients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Supply Voltage Protection (Figure 10.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2/16
M48Z32V
DESCRIPTION
The M48Z32V ZEROPOWER® RAM is a 32 Kbit x
8, non-volatile static RAM that integrates powerfail deselect circuitry and battery control logic on a
single die.
The 44-pin, 330mil SOIC provides a battery pin for
an external, user-supplied battery. This is all that
is required to fully non-volatize the SRAM.
Figure 3. SOIC Connections
A14
A12
A7
A6
A5
A4
NF
NC
NC
NC
NC
NC
NC
NC
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
44
2
43
42
3
4
41
40
5
39
6
38
7
37
8
36
9
35
10
34
11
M48Z32V
33
12
32
13
31
14
30
15
29
16
17
28
18
27
19
26
20
25
24
21
23
22
VCC
W
A13
A8
A9
A11
G
NC
NC
NC
NC
NC
NC
NC
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
B+
AI04786
Note: NF, Pin 7 must be tied to VSS.
3/16
M48Z32V
Figure 4. Block Diagram
A0-A14
LITHIUM
CELL
POWER
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
DQ0-DQ7
32K x 8
SRAM ARRAY
E
VPFD
W
G
USER
SUPPLIED
VCC
VSS
MAXIMUM RATING
Stressing the device above the rating listed in the
“Absolute Maximum Ratings” table may cause
permanent damage to the device. These are
stress ratings only and operation of the device at
these or any other conditions above those indicated in the Operating sections of this specification is
AI04788
not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device
reliability.
Refer
also
to
the
STMicroelectronics SURE Program and other relevant quality documents.
Table 2. Absolute Maximum Ratings
Symbol
TA
TSTG
TSLD(1)
Parameter
Value
Unit
Grade 1
0 to 70
°C
Grade 6
–40 to 85
°C
SOIC
–55 to 125
°C
260
°C
–0.3 to VCC + 0.3
V
Ambient Operating Temperature
Storage Temperature (VCC Off, Oscillator Off)
Lead Solder Temperature for 10 seconds
VIO
Input or Output Voltages
VCC
Supply Voltage
–0.3 to 4.6
V
IO
Output Current
20
mA
PD
Power Dissipation
1
W
Note: 1. Reflow at peak temperature of 215°C to 225°C for < 60 seconds (total thermal budget not to exceed 180°C for between 90 and 120
seconds).
CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.
4/16
M48Z32V
DC AND AC PARAMETERS
This section summarizes the operating and measurement conditions, as well as the DC and AC
characteristics of the device. The parameters in
the following DC and AC Characteristic tables are
derived from tests performed under the Measure-
ment Conditions listed in the relevant tables. Designers should check that the operating conditions
in their projects match the measurement conditions when using the quoted parameters.
Table 3. Operating and AC Measurement Conditions
Parameter(1)
M48Z32V
Unit
3.0 to 3.6
V
Grade 1
0 to 70
°C
Grade 6
–40 to 85
°C
Load Capacitance (CL)
50
pF
Input Rise and Fall Times
≤5
ns
0 to 3
V
1.5
V
Supply Voltage (VCC)
Ambient Operating Temperature (TA)
Input Pulse Voltages
Input and Output Timing Ref. Voltages
Note: 1. Output Hi-Z is defined as the point where data is no longer driven.
Figure 5. AC Measurement Load Circuit
645Ω
DEVICE
UNDER
TEST
CL = 50pF or
5pF
CL includes JIG capacitance
1.75V
AI04789
Table 4. Capacitance
Symbol
CIN
CIO(3)
Parameter(1,2)
Min
Max
Unit
Input Capacitance
10
pF
Input / Output Capacitance
10
pF
Note: 1. Effective capacitance measured with power supply at 3.3V; sampled only, not 100% tested.
2. At 25°C, f = 1MHz.
3. Outputs deselected.
5/16
M48Z32V
Table 5. DC Characteristics
Sym
ILI
Parameter
Input Leakage Current
Test Condition(1)
Min
Typ
Max
Unit
0V ≤ VIN ≤ VCC
±1
µA
0V ≤ VOUT ≤ VCC
±1
µA
1.2
µA
ILO(2)
Output Leakage Current
IBAT
Battery Current
TA = 40°C; VCC = 0V
VBAT = 3V
ICC1
Supply Current
IO = 0mA; Cycle Time = Min
E = 0.2V, other input =
VCC – 2V or 0.2V
45
mA
ICC2
Supply Current (TTL
Standby)
E = VIH
800
µA
ICC3
Supply Current (CMOS
Standby)
E = VCC – 0.2V
500
µA
VIL(3)
Input Low Voltage
–0.3
0.8
V
VIH
Input High Voltage
2.2
VCC + 0.3
V
VOL
Output Low Voltage
IOL = 2.1mA
0.4
V
VOH
Output High Voltage
IOH = –1mA
0.2
0.8VCC
V
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C or –40 to 85°C; VCC = 3.0 to 3.6V (except where noted).
2. Outputs deselected.
3. Negative spikes of –1V allowed for up to 10ns once per cycle.
OPERATING MODES
The M48Z32V also has its own Power-fail Detect
circuit. The control circuitry constantly monitors
the single power supply for an out of tolerance
condition. When VCC is out of tolerance, the circuit
write protects the SRAM, providing a high degree
of data security in the midst of unpredictable system operation brought on by low VCC. As VCC falls
below approximately VSO, the control circuitry connects the battery which maintains data until valid
power returns.
Table 6. Operating Modes
Mode
VCC
E
G
W
DQ0-DQ7
Power
VIH
X
X
High Z
Standby
VIL
X
VIL
DIN
Active
READ
VIL
VIL
VIH
DOUT
Active
READ
VIL
VIH
VIH
High Z
Active
Deselect
WRITE
3.0 to 3.6V
Deselect
VSO to VPFD (min)(1)
X
X
X
High Z
CMOS Standby
Deselect
≤ VSO(1)
X
X
X
High Z
Battery Back-up Mode
Note: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage.
1. See Table 10, page 12 for details.
6/16
M48Z32V
READ Mode
The M48Z32V is in the READ Mode whenever W
(WRITE Enable) is high, E (Chip Enable) is low.
The device architecture allows ripple-through access of data from eight of 262,144 locations in the
static storage array. Thus, the unique address
specified by the 15 Address Inputs defines which
one of the 32,768 bytes of data is to be accessed.
Valid data will be available at the Data I/O pins
within Address Access time (tAVQV) after the last
address input signal is stable, providing that the E
and G access times are also satisfied. If the E and
G access times are not met, valid data will be
available after the latter of the Chip Enable Access
time (tELQV) or Output Enable Access time
(tGLQV).
The state of the eight three-state Data I/O signals
is controlled by E and G. If the outputs are activated before tAVQV, the data lines will be driven to an
indeterminate state until tAVQV. If the Address Inputs are changed while E and G remain active,
output data will remain valid for Output Data Hold
time (tAXQX) but will go indeterminate until the next
Address Access.
Figure 6. READ Mode AC Waveforms
tAVAV
VALID
A0-A14
tAVQV
tAXQX
tELQV
tEHQZ
E
tELQX
tGLQV
tGHQZ
G
tGLQX
DQ0-DQ7
VALID
AI00925
Note: WRITE Enable (W) = High.
7/16
M48Z32V
Table 7. READ Mode AC Characteristics
M48Z32V
(1)
Symbol
–35
Parameter
Min
Unit
Max
tAVAV
READ Cycle Time
tAVQV
Address Valid to Output Valid
35
ns
tELQV
Chip Enable Low to Output Valid
35
ns
tGLQV
Output Enable Low to Output Valid
15
ns
35
ns
tELQX(2)
Chip Enable Low to Output Transition
5
ns
tGLQX(2)
Output Enable Low to Output Transition
0
ns
tEHQZ(2)
Chip Enable High to Output Hi-Z
13
ns
tGHQZ(2)
Output Enable High to Output Hi-Z
13
ns
0
ns
tAXQX
Address Transition to Output Transition
5
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C or –40 to 85°C; VCC = 3.0 to 3.6V (except where noted).
2. CL = 5pF (see Figure 5, page 5).
8/16
M48Z32V
WRITE Mode
The M48Z32V is in the WRITE Mode whenever W
and E are low. The start of a WRITE is referenced
from the latter occurring falling edge of W or E. A
WRITE is terminated by the earlier rising edge of
W or E. The addresses must be held valid throughout the cycle. E or W must return high for a minimum of tEHAX from Chip Enable or tWHAX from
WRITE Enable prior to the initiation of another
READ or WRITE cycle. Data-in must be valid tDVWH prior to the end of WRITE and remain valid for
tWHDX afterward. G should be kept high during
WRITE cycles to avoid bus contention; although, if
the output bus has been activated by a low on E
and G, a low on W will disable the outputs tWLQZ
after W falls.
Figure 7. WRITE Enable Controlled, WRITE Mode AC Waveforms
tAVAV
VALID
A0-A14
tAVWH
tWHAX
E
tWLWH
tAVWL
W
tWLQZ
tWHQX
tWHDX
DQ0-DQ7
DATA INPUT
tDVWH
AI05662
Figure 8. Chip Enable Controlled, WRITE Mode AC Waveforms
tAVAV
VALID
A0-A14
tAVEH
tAVEL
tELEH
tEHAX
E
tAVWL
W
tEHDX
DQ0-DQ7
DATA INPUT
tDVEH
AI00927
9/16
M48Z32V
Table 8. WRITE Mode AC Characteristics
M48Z32V
(1)
Symbol
–35
Parameter
Min
Unit
Max
tAVAV
WRITE Cycle Time
35
ns
tAVWL
Address Valid to WRITE Enable Low
0
ns
tAVEL
Address Valid to Chip Enable Low
0
ns
tWLWH
WRITE Enable Pulse Width
25
ns
tELEH
Chip Enable Low to Chip Enable High
25
ns
tWHAX
WRITE Enable High to Address Transition
0
ns
tEHAX
Chip Enable High to Address Transition
0
ns
tDVWH
Input Valid to WRITE Enable High
12
ns
tDVEH
Input Valid to Chip Enable High
12
ns
tWHDX
WRITE Enable High to Input Transition
0
ns
tEHDX
Chip Enable High to Input Transition
0
ns
tWLQZ
(2,3)
WRITE Enable Low to Output Hi-Z
13
tAVWH
Address Valid to WRITE Enable High
25
ns
tAVEH
Address Valid to Chip Enable High
25
ns
WRITE Enable High to Output Transition
5
ns
tWHQX(2,3)
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C or –40 to 85°C; VCC = 3.0 to 3.6V (except where noted).
2. CL = 5pF (see Figure 5, page 5).
3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
10/16
ns
M48Z32V
Data Retention Mode
With valid VCC applied, the M48Z32V operates as
a conventional BYTEWIDE™ static RAM. Should
the supply voltage decay, the RAM will automatically power-fail deselect, write protecting itself
when VCC falls within the VPFD (max), VPFD (min)
window. All outputs become high impedance, and
all inputs are treated as “Don't care.”
Note: A power failure during a WRITE cycle may
corrupt data at the currently addressed location,
but does not jeopardize the rest of the RAM's content. At voltages below VPFD(min), the user can be
assured the memory will be in a write protected
state, provided the VCC fall time is not less than tF.
The M48Z32V may respond to transient noise
spikes on VCC that reach into the deselect window
during the time the device is sampling VCC. Therefore, decoupling of the power supply lines is recommended.
When VCC drops below VSO, the control circuit
switches power to the external battery which preserves data.
As system power returns and VCC rises above
VSO, the battery is disconnected, and the power
supply is switched to external VCC. Write protection continues until VCC reaches VPFD(min) plus
tREC(min). Normal RAM operation can resume
tREC after VCC exceeds VPFD(max).
For more information on Battery Storage Life refer
to the Application Note AN1012.
Figure 9. Power Down/Up Mode AC Waveforms
VCC
VPFD (max)
VPFD (min)
VSO
tF
tR
tFB
tDR
tPD
INPUTS
tRB
RECOGNIZED
tREC
DON'T CARE
RECOGNIZED
HIGH-Z
OUTPUTS
VALID
VALID
(PER CONTROL INPUT)
(PER CONTROL INPUT)
AI01168C
Table 9. Power Down/Up AC Characteristics
Symbol
Parameter(1)
tPD
E or W at VIH before Power Down
tF(2)
VPFD (max) to VPFD (min) VCC Fall Time
tFB(3)
Min
Max
Unit
0
µs
300
µs
VPFD (min) to VSS VCC Fall Time
10
µs
tR
VPFD (min) to VPFD (max) VCC Rise Time
10
µs
tRB
VSS to VPFD (min) VCC Rise Time
1
µs
tREC(4)
VPFD (max) to Inputs Recognized
40
200
ms
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C or –40 to 85°C; VCC = 3.0 to 3.6V (except where noted).
2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200µs after VCC passes VPFD (min).
3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
4. tREC (min) = 20ms for industrial temperature Grade (6) device.
11/16
M48Z32V
Table 10. Power Down/Up Trip Points DC Characteristics
Symbol
Parameter(1,2)
VPFD
Power-fail Deselect Voltage
VSO
Battery Back-up Switchover Voltage
Min
Typ
Max
Unit
2.7
2.85
3.0
V
VPFD – 100mV
V
Note: 1. All voltages referenced to VSS.
2. Valid for Ambient Operating Temperature: TA = 0 to 70°C or –40 to 85°C; VCC = 3.0 to 3.6V (except where noted).
VCC Noise And Negative Going Transients
ICC transients, including those produced by output
switching, can produce voltage fluctuations, resulting in spikes on the VCC bus. These transients
can be reduced if capacitors are used to store energy which stabilizes the VCC bus. The energy
stored in the bypass capacitors will be released as
low going spikes are generated or energy will be
absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1µF (see Figure 10) is
recommended in order to provide the needed filtering.
In addition to transients that are caused by normal
SRAM operation, power cycling can generate negative voltage spikes on VCC that drive it to values
below VSS by as much as one volt. These negative
spikes can cause data corruption in the SRAM
while in battery backup mode. To protect from
these voltage spikes, ST recommends connecting
a schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS). (Schottky diode
1N5817 is recommended for through hole and
MBRS120T3 is recommended for surface mount).
12/16
Figure 10. Supply Voltage Protection
VCC
VCC
0.1µF
DEVICE
VSS
AI02169
M48Z32V
PART NUMBERING
Table 11. Ordering Information Scheme
Example:
M48Z
32V
–35
MT
1
TR
Device Type
M48Z
Supply Voltage and Write Protect Voltage
32V = VCC = 3.0 to 3.6V; VPFD = 2.7 to 3.0V
Speed
–35 = 35ns
Package
MT = 44-lead, Hatless SOIC
Temperature Range
1 = 0 to 70°C
6 = –40 to 85°C
Shipping Method for SOIC
blank = Tubes
TR = Tape & Reel
For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device,
please contact the ST Sales Office nearest to you.
13/16
M48Z32V
PACKAGE MECHANICAL INFORMATION
Figure 11. SOH44 – 44-lead Plastic, Hatless, Small Package Outline
A2
A
C
B
e
CP
D
N
E
H
A1
α
L
1
SOH-C
Note: Drawing is not to scale.
Table 12. SOH44 – 44-lead Plastic, Hatless, Small Package Mechanical Data
mm
inch
Symbol
Typ
Min
A
Typ
Min
3.05
Max
0.120
A1
0.05
0.36
0.002
0.014
A2
2.34
2.69
0.092
0.106
B
0.36
0.46
0.014
0.018
C
0.15
0.32
0.006
0.012
D
17.71
18.49
0.697
0.728
E
8.23
8.89
0.324
0.350
–
–
–
–
H
11.51
12.70
0.453
0.500
L
0.41
1.27
0.016
0.050
α
0°
8°
0°
8°
N
44
e
CP
14/16
Max
0.81
0.032
44
0.10
0.004
M48Z32V
REVISION HISTORY
Table 13. Revision History
Date
Rev. #
Revision Details
October 2002
1.0
First Issue
11/07/02
1.1
Update Absolute Maximum Ratings, DC Characteristics (Table 2, 5)
15/16
M48Z32V
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is registered trademark of STMicroelectronics
All other names are the property of their respective owners.
© 2002 STMicroelectronics - All Rights Reserved
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