STMICROELECTRONICS M48Z08

M48Z08
M48Z18
5 V, 64 Kbit (8 Kb x 8) ZEROPOWER® SRAM
Features
■
Integrated, ultra low power SRAM and powerfail control circuit
■
Unlimited WRITE cycles
■
READ cycle time equals WRITE cycle time
■
Automatic power-fail chip deselect and WRITE
protection
■
WRITE protect voltages
(VPFD = power-fail deselect voltage):
– M48Z08: VCC = 4.75 to 5.5 V
4.5 V ≤ VPFD ≤ 4.75 V
– M48Z18: VCC = 4.5 to 5.5 V
4.2 V ≤ VPFD ≤ 4.5 V
■
Self-contained battery in the CAPHAT™ DIP
package
■
Pin and function compatible with JEDEC
standard 8 K x 8 SRAMs
■
RoHS compliant
– Lead-free second level interconnect
May 2010
28
1
PCDIP28 (PC)
Battery CAPHAT™
Doc ID 2424 Rev 7
1/20
www.st.com
1
Contents
M48Z08, M48Z18
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1
READ mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2
WRITE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3
Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.4
VCC noise and negative going transients . . . . . . . . . . . . . . . . . . . . . . . . . 11
3
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7
Environmental information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
8
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2/20
Doc ID 2424 Rev 7
M48Z08, M48Z18
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
READ mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
WRITE mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Power down/up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Power down/up trip points DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
PCDIP28 – 28-pin plastic DIP, battery CAPHAT™, package mech. data . . . . . . . . . . . . . 16
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Doc ID 2424 Rev 7
3/20
List of figures
M48Z08, M48Z18
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
4/20
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
DIP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
READ mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
WRITE enable controlled, WRITE mode AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Chip enable controlled, WRITE mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
AC testing load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
PCDIP28 – 28-pin plastic DIP, battery CAPHAT™, package outline . . . . . . . . . . . . . . . . . 16
Recycling symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Doc ID 2424 Rev 7
M48Z08, M48Z18
1
Description
Description
The M48Z08/18 ZEROPOWER® RAM is an 8 K x 8 non-volatile static RAM which is pin and
function compatible with the DS1225.
The monolithic chip provides a highly integrated battery-backed memory solution.
The M48Z08/18 is a non-volatile pin and function equivalent to any JEDEC standard 8 K x 8
SRAM. It also easily fits into many ROM, EPROM, and EEPROM sockets, providing the
non-volatility of PROMs without any requirement for special write timing or limitations on the
number of writes that can be performed.
The 28-pin, 600 mil DIP CAPHAT™ houses the M48Z08/18 silicon with a long-life lithium
button cell in a single package.
Figure 1.
Logic diagram
VCC
13
8
A0-A12
W
DQ0-DQ7
M48Z08
M48Z18
E
G
VSS
Table 1.
AI01022
Signal names
A0-A12
DQ0-DQ7
Address inputs
Data inputs / outputs
E
Chip enable
G
Output enable
W
WRITE enable
VCC
Supply voltage
VSS
Ground
NC
Not connected internally
Doc ID 2424 Rev 7
5/20
Description
Figure 2.
M48Z08, M48Z18
DIP connections
NC
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
Figure 3.
28
1
27
2
26
3
4
25
5
24
6
23
7
M48Z08 22
M48Z18 21
8
9
20
10
19
11
18
12
17
13
16
14
15
VCC
W
NC
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
AI01183
Block diagram
A0-A12
LITHIUM
CELL
POWER
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
8K x 8
SRAM ARRAY
DQ0-DQ7
E
VPFD
W
G
VSS
VCC
6/20
Doc ID 2424 Rev 7
AI01394
M48Z08, M48Z18
2
Operation modes
Operation modes
The M48Z08/18 also has its own power-fail detect circuit. The control circuitry constantly
monitors the single 5 V supply for an out of tolerance condition. When VCC is out of
tolerance, the circuit write protects the SRAM, providing a high degree of data security in the
midst of unpredictable system operation brought on by low VCC. As VCC falls below
approximately 3 V, the control circuitry connects the battery which maintains data until valid
power returns.
Table 2.
Operating modes
Mode
VCC
Deselect
WRITE
READ
4.75 to 5.5 V
or
4.5 to 5.5 V
READ
Deselect
Deselect
VSO to VPFD
≤ VSO
(min)(1)
(1)
E
G
W
DQ0-DQ7
Power
VIH
X
X
High Z
Standby
VIL
X
VIL
DIN
Active
VIL
VIL
VIH
DOUT
Active
VIL
VIH
VIH
High Z
Active
X
X
X
High Z
CMOS standby
X
X
X
High Z
Battery backup mode
1. See Table 10 on page 15 for details.
Note:
X = VIH or VIL; VSO = Battery backup switchover voltage.
2.1
READ mode
The M48Z08/18 is in the READ mode whenever W (WRITE enable) is high and E (chip
enable) is low. The device architecture allows ripple-through access of data from eight of
65,536 locations in the static storage array. Thus, the unique address specified by the 13
address inputs defines which one of the 8,192 bytes of data is to be accessed. Valid data
will be available at the data I/O pins within address access time (tAVQV) after the last
address input signal is stable, providing that the E and G access times are also satisfied. If
the E and G access times are not met, valid data will be available after the latter of the chip
enable access time (tELQV) or output enable access time (tGLQV).
The state of the eight three-state data I/O signals is controlled by E and G. If the outputs are
activated before tAVQV, the data lines will be driven to an indeterminate state until tAVQV. If
the address inputs are changed while E and G remain active, output data will remain valid
for output data hold time (tAXQX) but will go indeterminate until the next address access.
Doc ID 2424 Rev 7
7/20
Operation modes
Figure 4.
M48Z08, M48Z18
READ mode AC waveforms
tAVAV
VALID
A0-A12
tAVQV
tAXQX
tELQV
tEHQZ
E
tELQX
tGLQV
tGHQZ
G
tGLQX
DQ0-DQ7
VALID
AI01385
Note:
WRITE enable (W) = high.
Table 3.
READ mode AC characteristics
Symbol
M48Z08/M48Z18
Parameter(1)
Unit
Min
Max
tAVAV
READ cycle time
tAVQV
Address valid to output valid
100
tELQV
Chip enable low to output valid
100
ns
tGLQV
Output enable low to output valid
50
ns
100
ns
ns
tELQX(2)
Chip enable low to output transition
10
ns
tGLQX(2)
tEHQZ(2)
tGHQZ(2)
Output enable low to output transition
5
ns
tAXQX
Address transition to output transition
Chip enable high to output Hi-Z
Output enable high to output Hi-Z
50
ns
40
ns
5
ns
1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.75 to 5.5 V or 4.5 to 5.5 V (except where noted).
2. CL = 30 pF.
2.2
WRITE mode
The M48Z08/18 is in the WRITE mode whenever W and E are active. The start of a WRITE
is referenced from the latter occurring falling edge of W or E.
A WRITE is terminated by the earlier rising edge of W or E. The addresses must be held
valid throughout the cycle. E or W must return high for a minimum of tEHAX from chip enable
or tWHAX from WRITE Enable prior to the initiation of another READ or WRITE cycle. Datain must be valid tDVWH prior to the end of WRITE and remain valid for tWHDX afterward. G
should be kept high during WRITE cycles to avoid bus contention; although, if the output bus
has been activated by a low on E and G, a low on W will disable the outputs tWLQZ after W
falls.
8/20
Doc ID 2424 Rev 7
M48Z08, M48Z18
Figure 5.
Operation modes
WRITE enable controlled, WRITE mode AC waveform
tAVAV
A0-A12
VALID
tAVWH
tWHAX
tAVEL
E
tWLWH
tAVWL
W
tWLQZ
tWHQX
tWHDX
DQ0-DQ7
DATA INPUT
tDVWH
AI01386
Figure 6.
Chip enable controlled, WRITE mode AC waveforms
tAVAV
A0-A12
VALID
tAVEH
tAVEL
tELEH
tEHAX
E
tAVWL
W
tEHDX
DQ0-DQ7
DATA INPUT
tDVEH
Doc ID 2424 Rev 7
AI01387B
9/20
Operation modes
Table 4.
Symbol
M48Z08, M48Z18
WRITE mode AC characteristics
Parameter(1)
M48Z08/M48Z18
Unit
Min
Max
tAVAV
WRITE cycle time
100
ns
tAVWL
Address valid to WRITE enable low
0
ns
tAVEL
Address valid to chip enable 1 low
0
ns
tWLWH
WRITE enable pulse width
80
ns
tELEH
Chip enable low to chip enable 1 high
80
ns
tWHAX
WRITE enable high to address transition
10
ns
tEHAX
Chip enable high to address transition
10
ns
tDVWH
Input valid to WRITE enable high
50
ns
tDVEH
Input valid to chip enable 1 high
30
ns
tWHDX
WRITE enable high to input transition
5
ns
tEHDX
Chip enable high to input transition
5
ns
tWLQZ(2)(3)
WRITE enable low to output Hi-Z
50
ns
tAVWH
Address valid to WRITE enable high
80
ns
tAVEH
Address valid to chip enable high
80
ns
WRITE enable high to output transition
10
ns
tWHQX(2)(3)
1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.75 to 5.5 V or 4.5 to 5.5 V (except where
noted).
2. CL = 30 pF.
3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
2.3
Data retention mode
With valid VCC applied, the M48Z08/18 operates as a conventional BYTEWIDE™ static
RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write
protecting itself when VCC falls within the VPFD (max), VPFD (min) window. All outputs
become high impedance, and all inputs are treated as “Don't care.”
Note:
A power failure during a WRITE cycle may corrupt data at the currently addressed location,
but does not jeopardize the rest of the RAM's content. At voltages below VPFD (min), the
user can be assured the memory will be in a write protected state, provided the VCC fall time
is not less than tF. The M48Z08/18 may respond to transient noise spikes on VCC that reach
into the deselect window during the time the device is sampling VCC. Therefore, decoupling
of the power supply lines is recommended.
When VCC drops below VSO, the control circuit switches power to the internal battery which
preserves data. The internal button cell will maintain data in the M48Z08/18 for an
accumulated period of at least 11 years when VCC is less than VSO.
As system power returns and VCC rises above VSO, the battery is disconnected, and the
power supply is switched to external VCC. Write protection continues until VCC reaches VPFD
(min) plus trec (min). E should be kept high as VCC rises past VPFD (min) to prevent
inadvertent write cycles prior to system stabilization. Normal RAM operation can resume trec
after VCC exceeds VPFD (max). For more information on battery storage life refer to the
application note AN1012.
10/20
Doc ID 2424 Rev 7
M48Z08, M48Z18
2.4
Operation modes
VCC noise and negative going transients
ICC transients, including those produced by output switching, can produce voltage
fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if
capacitors are used to store energy which stabilizes the VCC bus. The energy stored in the
bypass capacitors will be released as low going spikes are generated or energy will be
absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1 µF (as shown in
Figure 7) is recommended in order to provide the needed filtering.
In addition to transients that are caused by normal SRAM operation, power cycling can
generate negative voltage spikes on VCC that drive it to values below VSS by as much as
one volt. These negative spikes can cause data corruption in the SRAM while in battery
backup mode. To protect from these voltage spikes, STMicroelectronics recommends
connecting a Schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS).
Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is
recommended for surface mount.
Figure 7.
Supply voltage protection
VCC
VCC
0.1µF
DEVICE
VSS
AI02169
Doc ID 2424 Rev 7
11/20
Maximum ratings
3
M48Z08, M48Z18
Maximum ratings
Stressing the device above the rating listed in the absolute maximum ratings table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Table 5.
Absolute maximum ratings
Symbol
TA
TSTG
TSLD(1)
Parameter
Ambient operating temperature
Storage temperature (VCC off, oscillator off)
Lead solder temperature for 10 seconds
Value
Unit
0 to 70
°C
–40 to 85
°C
260
°C
VIO
Input or output voltages
–0.3 to 7
V
VCC
Supply voltage
–0.3 to 7
V
IO
Output current
20
mA
PD
Power dissipation
1
W
1. Soldering temperature of the IC leads is to not exceed 260 °C for 10 seconds. In order to protect the lithium
battery, preheat temperatures must be limited such that the battery temperature does not exceed +85 °C.
Furthermore, the devices shall not be exposed to IR reflow.
Caution:
12/20
Negative undershoots below –0.3 V are not allowed on any pin while in the battery backup
mode.
Doc ID 2424 Rev 7
M48Z08, M48Z18
4
DC and AC parameters
DC and AC parameters
This section summarizes the operating and measurement conditions, as well as the DC and
AC characteristics of the device. The parameters in the following DC and AC characteristic
tables are derived from tests performed under the measurement conditions listed in the
relevant tables. Designers should check that the operating conditions in their projects match
the measurement conditions when using the quoted parameters.
Table 6.
Operating and AC measurement conditions
Parameter
Supply voltage (VCC)
Ambient operating temperature (TA)
M48Z18
Unit
4.75 to 5.5
4.5 to 5.5
V
0 to 70
0 to 70
°C
Load capacitance (CL)
100
100
pF
Input rise and fall times
≤5
≤5
ns
0 to 3
0 to 3
V
1.5
1.5
V
Input pulse voltages
Input and output timing ref. voltages
Note:
M48Z08
Output Hi-Z is defined as the point where data is no longer driven.
Figure 8.
AC testing load circuit
5V
1.8kΩ
DEVICE
UNDER
TEST
OUT
1kΩ
CL = 100pF or 30pF
CL includes JIG capacitance
Table 7.
Capacitance
Parameter(1)(2)
Symbol
CIN
CIO(3)
AI01398
Min
Max
Unit
Input capacitance
-
10
pF
Input / output capacitance
-
10
pF
1. Effective capacitance measured with power supply at 5 V; sampled only, not 100% tested.
2. At 25 °C, f = 1 MHz.
3. Outputs deselected.
Doc ID 2424 Rev 7
13/20
DC and AC parameters
Table 8.
DC characteristics
Symbol
ILI
ILO(2)
M48Z08, M48Z18
Test condition(1)
Parameter
Input leakage current
Output leakage current
Min
Max
Unit
0 V ≤ VIN ≤ VCC
±1
µA
0 V ≤ VOUT ≤ VCC
±1
µA
Outputs open
80
mA
E = VIH
3
mA
E = VCC – 0.2 V
3
mA
ICC
Supply current
ICC1
Supply current (standby) TTL
ICC2
Supply current (standby) CMOS
VIL
Input low voltage
–0.3
0.8
V
VIH
Input high voltage
2.2
VCC + 0.3
V
VOL
Output low voltage
IOL = 2.1 mA
0.4
V
VOH
Output high voltage
IOH = –1 mA
2.4
V
1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.75 to 5.5 V or 4.5 to 5.5 V (except where noted
2. Outputs deselected.
Figure 9.
Power down/up mode AC waveforms
VCC
VPFD (max)
VPFD (min)
VSO
tF
tPD
INPUTS
tDR
tR
tFB
RECOGNIZED
tRB
DON'T CARE
tREC
NOTE
RECOGNIZED
HIGH-Z
OUTPUTS
VALID
VALID
(PER CONTROL INPUT)
(PER CONTROL INPUT)
AI00606
Note:
14/20
Inputs may or may not be recognized at this time. Caution should be taken to keep E high as
VCC rises past VPFD (min). Some systems may perform inadvertent WRITE cycles after VCC
rises above VPFD (min) but before normal system operations begin. Even though a power on
reset is being applied to the processor, a reset condition may not occur until after the system
is running.
Doc ID 2424 Rev 7
M48Z08, M48Z18
DC and AC parameters
Table 9.
Power down/up AC characteristics
Parameter(1)
Symbol
Min
Max
Unit
tPD
E or W at VIH before power down
0
-
µs
tF(2)
VPFD (max) to VPFD (min) VCC fall time
300
-
µs
tFB(3)
VPFD (min) to VSS VCC fall time
10
-
µs
tR
VPFD (min) to VPFD (max) VCC rise time
0
-
µs
tRB
VSS to VPFD (min) VCC rise time
1
-
µs
trec
E or W at VIH before power-up
2
-
ms
1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.75 to 5.5 V or 4.5 to 5.5 V (except where
noted).
2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring
until 200 µs after VCC passes VPFD (min).
3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
Table 10.
Power down/up trip points DC characteristics
Parameter(1)(2)
Symbol
VPFD
Power-fail deselect voltage
VSO
Battery backup switchover voltage
tDR
(3)
Min
Typ
Max
Unit
M48Z08
4.5
4.6
4.75
V
M48Z18
4.2
4.3
4.5
V
Expected data retention time
3.0
11
V
Years
1. All voltages referenced to VSS.
2. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.75 to 5.5 V or 4.5 to 5.5 V (except where
noted).
3. At 25 °C, VCC = 0 V.
Doc ID 2424 Rev 7
15/20
Package mechanical data
5
M48Z08, M48Z18
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark
Figure 10. PCDIP28 – 28-pin plastic DIP, battery CAPHAT™, package outline
A2
A1
B1
B
A
L
C
e1
eA
e3
D
N
E
1
PCDIP
Note:
Drawing is not to scale.
Table 11.
PCDIP28 – 28-pin plastic DIP, battery CAPHAT™, package mech. data
mm
inches
Symb
Typ
Min
Max
A
8.89
A1
A2
Min
Max
9.65
0.350
0.380
0.38
0.76
0.015
0.030
8.38
8.89
0.330
0.350
B
0.38
0.53
0.015
0.021
B1
1.14
1.78
0.045
0.070
C
0.20
0.31
0.008
0.012
D
39.37
39.88
1.550
1.570
E
17.83
18.34
0.702
0.722
e1
2.29
2.79
0.090
0.110
eA
15.24
16.00
0.600
0.630
L
3.05
3.81
0.120
0.150
N
28
e3
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33.02
Typ
1.3
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M48Z08, M48Z18
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Part numbering
Part numbering
Table 12.
Ordering information scheme
Example:
M48Z
08
–100
PC
1
TR
Device Type
M48Z
Supply voltage and write protect voltage
08 = VCC = 4.75 to 5.5 V; VPFD = 4.5 to 4.75 V
18 = VCC = 4.5 to 5.5 V; VPFD = 4.2 to 4.5 V
Speed
–100 = 100 ns
Package
PC = PCDIP28
Temperature range
1 = 0 to 70 °C
Shipping method
blank = ECOPACK® package, tubes
TR = ECOPACK® package, tape & reel
For other options, or for more information on any aspect of this device, please contact the
ST sales office nearest you.
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Environmental information
7
M48Z08, M48Z18
Environmental information
Figure 11. Recycling symbols
This product contains a non-rechargeable lithium (lithium carbon monofluoride chemistry)
button cell battery fully encapsulated in the final product.
Recycle or dispose of batteries in accordance with the battery manufacturer's instructions
and local/national disposal and recycling regulations.
Please refer to the following web site address for additional information regarding
compliance statements and waste recycling.
Go to www.st.com/nvram, then select "Lithium Battery Recycling" from "Related Topics".
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M48Z08, M48Z18
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Revision history
Revision history
Table 13.
Document revision history
Date
Revision
Changes
Mar-1999
1
First issue
19-Jul-2001
2
2-socket SOH and 2-pin SH packages removed; reformatted;
temperature information added to tables (Table 7, 8, 3, 4, 9, 10)
19-Dec-2001
2.1
Remove all references to “clock”
21-Dec-2001
2.2
Changes to text to reflect addition of M48Z08Y option
20-May-2002
2.3
Modify reflow time and temperature footnotes (Table 5)
10-Sep-2002
2.4
Remove all references to “SNAPHAT” and M48Z08Y part (Figure 1;
Table 5, 6, 3, 4, 10, 12)
01-Apr-2003
3
v2.2 template applied; updated test condition (Table 10)
28-Aug-2004
4
Reformatted; removed references to ‘crystal’ (Figure 1)
14-Dec-2005
5
Updated template, Lead-free text, removed footnote (Table 8, 12)
24-Mar-2009
6
Reformatted document; added text to Section 5: Package mechanical
data; added Section 7: Environmental information.
27-May-2010
7
Updated Section 3: Maximum ratings, Table 11; reformatted document;
minor textual changes.
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M48Z08, M48Z18
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