M54HC165 RAD-HARD 8 BIT PISO SHIFT REGISTER ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 15ns (TYP.) at VCC = 6V LOW POWER DISSIPATION: ICC =4µA(MAX.) at TA=25°C HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 54 SERIES 165 SPACE GRADE-1: ESA SCC QUALIFIED 50 krad QUALIFIED, 100 krad AVAILABLE ON REQUEST NO SEL UNDER HIGH LET HEAVY IONS IRRADIATION DEVICE FULLY COMPLIANT WITH SCC-9306-042 DESCRIPTION The M54HC165 is an high speed CMOS 8 BIT PISO SHIFT REGISTER fabricated with silicon gate C2MOS technology. This device contains eight clocked master slave RS flip-flops connected as a shift register, with auxiliary gating to provide over-riding asynchronous parallel entry. Parallel data enters DILC-16 FPC-16 ORDER CODES PACKAGE FM EM DILC FPC M54HC165D M54HC165K M54HC165D1 M54HC165K1 when the shift/load input is low. The parallel data can change while shift/load is low, provided that the recommended set-up and hold times are observed. For clocked operation, shift/load must be high. The two clock input perform identically; one can be used as a clock inhibit by applying a high signal; to permit this operation clocking is accomplished through a 2 input nor gate. To avoid double clocking, however, the inhibit signal should only go high while the clock is high. Otherwise the rising inhibit signal will cause the same response as rising clock edge. All inputs are equipped with protection circuits against static discharge and transient excess voltage. PIN CONNECTION March 2004 1/12 M54HC165 IEC LOGIC SYMBOLS INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN N° 1 2 7 9 10 11, 12, 13, 14, 3, 4, 5, 6 15 8 16 SYMBOL NAME AND FUNCTION SHIFT/LOAD Data Inputs QH Complementary Output QH Serial Output Clock Input (LOW to CLOCK HIGH, Edge Triggered SI Serial Data Inputs A to H Parallel Data Inputs CLOCK INH Clock Inhibit GND Ground (0V) VCC Positive Supply Voltage TRUTH TABLE INPUTS INTERNAL OUTPUTS OUTPUTS SHIFT / LOAD CLOCK INH CLOCK SI A..........H QA QB QH L X X X a..........h a b h H L H X H QAn QGn H L L X L QAn QGn H L H X H QAn QGn H L L X L QAn QGn H X X X X X H H X H a........h : The level of steady input voltage at inputs a through respectively QAn - QGn : The level of QA - QG, respectively. before the most-recent transition of the clock 2/12 NO CHANGE NO CHANGE M54HC165 LOGIC DIAGRAM TIMING CHART 3/12 M54HC165 ABSOLUTE MAXIMUM RATINGS Symbol VCC Parameter Supply Voltage Value Unit -0.5 to +7 V -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 V DC Input Diode Current ± 20 mA IOK DC Output Diode Current ± 20 mA IO DC Output Current ± 25 mA ± 50 mA VI DC Input Voltage VO DC Output Voltage IIK ICC or IGND DC VCC or Ground Current PD Power Dissipation Tstg Storage Temperature TL Lead Temperature (10 sec) V 300 mW -65 to +150 °C 265 °C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied RECOMMENDED OPERATING CONDITIONS Symbol VCC Parameter Supply Voltage VI Input Voltage VO Output Voltage Top Operating Temperature Input Rise and Fall Time tr, tf 4/12 Value Unit 2 to 6 V 0 to VCC V 0 to VCC V -55 to 125 °C VCC = 2.0V 0 to 1000 ns VCC = 4.5V 0 to 500 ns VCC = 6.0V 0 to 400 ns M54HC165 DC SPECIFICATIONS Test Condition Symbol VIH VIL VOH VOL II ICC Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Input Leakage Current Quiescent Supply Current Value TA = 25°C VCC (V) Min. 2.0 4.5 6.0 2.0 4.5 6.0 Typ. Max. 1.5 3.15 4.2 -40 to 85°C -55 to 125°C Min. Min. Max. 1.5 3.15 4.2 0.5 1.35 1.8 Max. 1.5 3.15 4.2 0.5 1.35 1.8 V 0.5 1.35 1.8 2.0 IO=-20 µA 1.9 2.0 1.9 1.9 4.5 IO=-20 µA 4.4 4.5 4.4 4.4 Unit V 6.0 IO=-20 µA 5.9 6.0 5.9 5.9 4.5 IO=-4.0 mA 4.18 4.31 4.13 4.10 6.0 IO=-5.2 mA 5.68 2.0 IO=20 µA 0.0 0.1 0.1 0.1 4.5 IO=20 µA 0.0 0.1 0.1 0.1 6.0 IO=20 µA 0.0 0.1 0.1 0.1 4.5 IO=4.0 mA 0.17 0.26 0.33 0.40 6.0 IO=5.2 mA 0.18 0.26 0.33 0.40 6.0 VI = VCC or GND ± 0.1 ±1 ±1 µA 6.0 VI = VCC or GND 4 40 80 µA 5.8 5.63 V 5.60 V 5/12 M54HC165 AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6ns) Test Condition Symbol Parameter tTLH tTHL Output Transition Time tPLH tPHL Propagation Delay Time (CLOCK - QH, QH) tPLH tPHL Propagation Delay Time (SHIFT/LOAD QH, QH) tPLH tPHL Propagation Delay Time (H - QH, QH) fMAX Maximum Clock Frequency tW(H) tW(L) Minimum Pulse Width (CLOCK) tW(L) Minimum Pulse Width (SHIFT/LOAD) ts th tREM Minimum Set-up Time (PI - SHIFT/LOAD) (SI - CLOCK) (SHIFT/LOAD - CK) Minimum Hold Time (PI - SHIFT/LOAD) (SI - CLOCK) (SHIFT/LOAD - CK) Minimum Removal Time (CLOCK - CK INH) Value TA = 25°C VCC (V) Min. -40 to 85°C -55 to 125°C Min. Min. Typ. Max. 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 30 8 7 55 18 15 65 21 75 15 13 150 30 26 165 33 95 19 16 190 38 33 205 41 6.0 18 28 35 43 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 52 17 14 15 60 71 24 6 5 32 8 7 24 6 135 27 23 170 34 29 205 41 35 75 15 13 75 15 13 75 15 95 19 16 95 19 16 95 19 110 22 19 110 22 19 110 22 5 13 16 19 2.0 4.5 0 0 0 0 0 0 6.0 0 0 0 75 15 13 95 19 16 110 22 19 7.4 37 44 6.0 2.0 4.5 6.0 Max. 6.0 30 35 20 5 4 Unit Max. 110 22 19 225 45 38 ns ns 250 50 4.8 24 28 ns ns MHz ns ns ns ns ns CAPACITIVE CHARACTERISTICS Test Condition Symbol Parameter VCC (V) Value TA = 25°C Min. Typ. Max. 10 CIN Input Capacitance 5.0 5 CPD Power Dissipation Capacitance (note 1) 5.0 55 -40 to 85°C -55 to 125°C Min. Min. Max. 10 Unit Max. 10 pF pF 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC 6/12 M54HC165 TEST CIRCUIT CL = 50pF or equivalent (includes jig and probe capacitance) RT = ZOUT of pulse generator (typically 50Ω) WAVEFORM 1: SERIAL MODE PROPAGATION DELAY (f=1MHz; 50% duty cycle) 7/12 M54HC165 WAVEFORM 2: PARALLEL MODE PROPAGATION DELAY (f=1MHz; 50% duty cycle) WAVEFORM 3: MINIMUM PULSE WIDTH (S/L), PROPAGATION DELAY TIMES (f=1MHz; 50% duty cycle) 8/12 M54HC165 WAVEFORM 4: SETUP AND HOLD TIME (PI TO S/L) (f=1MHz; 50% duty cycle) WAVEFORM 5: MINIMUM REMOVAL TIME (CK INH TO CK) (f=1MHz; 50% duty cycle) 9/12 M54HC165 DILC-16 MECHANICAL DATA mm. inch DIM. MIN. TYP MAX. MIN. TYP. MAX. A 2.1 2.71 0.083 0.107 a1 3.00 3.70 0.118 0.146 a2 0.63 1.14 0.025 B 1.82 2.39 0.072 b 0.40 0.45 0.50 0.016 0.018 0.020 b1 0.20 0.254 0.30 0.008 0.010 0.012 D 20.06 20.32 20.58 0.790 0.800 0.810 e 7.36 7.62 7.87 0.290 0.300 0.310 e1 0.88 2.54 0.035 0.045 0.094 0.100 e2 17.65 17.78 17.90 0.695 0.700 0.705 e3 7.62 7.87 8.12 0.300 0.310 0.320 F 7.29 7.49 7.70 0.287 0.295 0.303 I 3.83 0.151 K 10.90 12.1 0.429 0.476 L 1.14 1.5 0.045 0.059 0056437F 10/12 M54HC165 FPC-16 MECHANICAL DATA mm. inch DIM. MIN. TYP MAX. MIN. TYP. MAX. A 6.75 6.91 7.06 0.266 0.272 0.278 B 9.76 9.94 10.14 0.384 0.392 0.399 C 1.49 1.95 0.059 D 0.102 0.127 0.152 0.004 0.005 0.006 E 8.76 8.89 9.01 0.345 0.350 0.355 F 0.077 1.27 G 0.38 H 6.0 L 18.75 M 0.33 0.050 0.43 0.48 0.015 0.017 0.019 0.237 0.38 N 22.0 0.738 0.43 0.013 0.867 0.015 4.31 0.017 0.170 G F D H 9 16 A N L 8 1 H E B M C 0016030E 11/12 M54HC165 Information furnished is believed to be accurate and reliable. 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