FAIRCHILD FSB127H

FSB117H / FSB127H / FSB147H
mWSaver™ Fairchild Power Switch (FPS™)
Features
Description
mWSaver™ Technology
The FSB-series is a next-generation, green-mode
Fairchild Power Switch (FPS™) incorporating Fairchild’s
innovative mWSaver™ technology, which dramatically
reduces standby and no-load power consumption,
enabling conformance to all worldwide Standby Mode
efficiency guidelines. It integrates an advanced currentmode pulse width modulator (PWM) and an avalancherugged 700 V SenseFET in a single package, allowing
auxiliary power designs with higher standby energy
efficiency, reduced size, improved reliability, and lower
system cost than previous solutions.

Achieve Low No-Load Power Consumption Less
than 40 mW at 230 VAC (EMI Filter Loss Included)

Meets 2013 ErP Standby Power Regulation (Less
than 0.5 W Consumption with 0.25 W Load) for
ATX Power and LCD TV Power

Eliminate X-Cap Discharge Resistor Loss with
AX-CAP™ Technology

Linearly Decreased Switching Frequency at LightLoad Condition and Advanced Burst Mode
Operation at No-Load Condition

700 V High-Voltage JFET Startup Circuit to
Eliminate the Startup Resistor Loss
Highly Integrated with Rich Features







Internal Avalanche-Rugged 700 V SenseFET
Built-in 5 ms Soft-Start
Peak-Current-Mode Control
Cycle-by-Cycle Current Limiting
Leading-Edge Blanking (LEB)
Synchronized Slope Compensation
Proprietary Asynchronous Jitter to Reduce EMI
Advanced Protection







Internal Overload / Open-Loop Protection (OLP)
VDD Under-Voltage Lockout (UVLO)
VDD Over-Voltage Protection (OVP)
Constant Power Limit (Full AC Input Range)
Internal Auto Restart Circuit (OLP, VDD OVP, OTP)
Internal OTP Sensor with Hysteresis
Adjustable Peak Current Limit
Related Resources


Evaluation Board: FEBFSB127H_T001
Fairchild Semiconductor’s mWSaver™ technology
offers best-in-class minimum no-load and light-load
power consumption. An innovative AX-CAP™ method,
one of the five proprietary mWSaver™ technologies,
minimizes losses in the EMI filter stage by eliminating
the X-cap discharge resistors while still meeting
IEC61010-1 safety requirement. mWSaver™ Green
Mode gradually decreases switching frequency as load
decreases to minimize switching losses.
A new proprietary asynchronous jitter decreases EMI
emission and built-in synchronized slope compensation
allows stable peak-current-mode control over a wide
range of input voltage. The proprietary internal line
compensation ensures constant output power limit over
entire universal line voltage range.
Requiring a minimum number of external components,
the FSB-series provides a basic platform that is well
suited for the cost-effective flyback converter design
with low standby power consumption.
Applications
General-purpose switched-mode power supplies and
flyback power converters, including:

Auxiliary Power Supply for PC, Server, LCD TV,
and Game Console

SMPS for VCR, SVR, STB, DVD, and DVCD
Player, Printer, Facsimile, and Scanner


General Adapter
LCD Monitor Power / Open-Frame SMPS
Fairchild Power Supply WebDesigner — Flyback
Design & Simulation - In Minutes at No Expense
© 2011 Fairchild Semiconductor Corporation
FSB117H / FSB127H / FSB147H • Rev. 1.0.7
www.fairchildsemi.com
FSB117H / FSB127H / FSBH147H — mWSaver™ Fairchild Power Switch (FPS™)
June 2013
Part Number
SenseFET
FSB117HNY
1 A, 700 V
FSB127HNY
2 A, 700 V
FSB147HNY
4 A, 700 V
Operating
Temperature Range
Package
Packing Method
-40°C to +105°C
8-Pin, Dual In-Line Package (DIP)
Tube
Application Diagram
Figure 1.
Table 1.
Typical Flyback Application
Output Power Table(1)
Product
230 VAC ±15%(2)
Adapter
(3)
85-265 VAC
Open Frame
(4)
Adapter
(3)
Open Frame(4)
FSB117H
10 W
15 W
9W
13 W
FSB127H
14 W
20 W
11 W
16 W
FSB147H
23 W
35 W
17 W
26 W
Notes:
1. The maximum output power can be limited by junction temperature.
2. 230 VAC or 100/115 VAC with voltage doubler.
3. Typical continuous power in a non-ventilated enclosed adapter with sufficient drain pattern of printed circuit
board (PCB) as a heat sink, at 50C ambient.
4. Maximum practical continuous power in an open-frame design with sufficient drain pattern of printed circuit board
(PCB) as a heat sink, at 50C ambient.
© 2011 Fairchild Semiconductor Corporation
FSB117H / FSB127H / FSB147H • Rev. 1.0.7
www.fairchildsemi.com
2
FSB117H / FSB127H / FSB147H — mWSaver™ Fairchild Power Switch (FPS™)
Ordering Information
HV
Drain
5
6,7,8
Line Voltage
Sample Circuit
Auto-Re-start
Protection
OVP
OLP
OTP
Brownout Protection
HV
Startup
VDD
PWM
Soft
Driver
OSC1
Internal
BIAS
2
S
Q
…
R
UVLO
Clock
Generator
12V/6V
Soft-Start
Comparator
Soft-Start
Green
Mode
Current-Limit
Comparator
VLimit
Debounce
OVP
VDD-OVP
IPK
4
Slope
Compensation
Maximum Duty
CycleLimit
PWM
3R
3
FB
ZFB
R
VMAX
50µA
OLP
IPK
GND
5.4V
OSC2
3.5V
1
PWM
Comparator
S/H
Current Limit
Compensation
OLP
Delay
VLimit
OLP
Comparator
4.6V
Figure 2. Block Diagram
© 2011 Fairchild Semiconductor Corporation
FSB117H / FSB127H / FSB147H • Rev. 1.0.7
www.fairchildsemi.com
3
FSB117H / FSB127H / FSB147H — mWSaver™ Fairchild Power Switch (FPS™)
Internal Block Diagram
F – Fairchild Logo
Z – Plant Code
X – 1-Digit Year Code
Y – 1-Digit Week Code
TT – 2-Digit Die Run Code
T – Package Type (N: DIP)
P – Y: Green Package
M – Manufacture Flow Code
Figure 3.
Pin Configuration
Pin Definitions
Pin #
Name
Description
1
GND
Ground. This pin internally connects to the SenseFET source and signal ground of the PWM
controller.
2
VDD
Supply voltage of the IC. Typically the holdup capacitor connects from this pin to ground.
Rectifier diode in series with the transformer auxiliary winding connects to this pin to supply bias
during normal operation.
3
FB
Feedback. The signal from the external compensation circuit connects to this pin. The PWM duty
cycle is determined by comparing the signal on this pin and the internal current-sense signal.
4
IPK
Adjust peak current. Typically a resistor connects from this pin to the GND pin to program the
current-limit level. The internal current source (50 µA) introduces voltage drop across the
resistor, which determines the current limit level of pulse-by-pulse current limit.
HV
Startup. Typically, resistors in series with diodes from the AC line connect to this pin to supply
internal bias and to charge the external capacitor connected between the VDD pin and the GND
pin during startup. This pin is also used to sense the line voltage for brownout protection and AC
line disconnection detection.
5
6
7
Drain
SenseFET drain. This pin is designed to directly drive the transformer.
8
© 2011 Fairchild Semiconductor Corporation
FSB117H / FSB127H / FSB147H • Rev. 1.0.7
www.fairchildsemi.com
4
FSB117H / FSB127H / FSB147H — mWSaver™ Fairchild Power Switch (FPS™)
Pin Configuration
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
VDRAIN
Parameter
Min.
(5,6)
Drain Pin Voltage
FSB117H
FSB127H
FSB147H(9)
FSB117H
FSB127H
FSB147H
IDM
Drain Current Pulsed(7)
EAS
Single Pulsed Avalanche Energy(8)
VDD
VFB
VIPK
VHV
PD
DC Supply Voltage
FB Pin Input Voltage
IPK Pin Input Voltage
HV Pin Input Voltage
Power Dissipation (TA＜50°C)
TJ
Operating Junction Temperature
-40
Storage Temperature Range
Lead Soldering Temperature (Wave Soldering or IR, 10 Seconds)
Human Body Model:
JESD22-A114
Electrostatic Discharge Capability,
All Pins Except HV Pin
Charged Device Model:
JESD22-C101
Human Body Model:
JESD22-A114
Electrostatic Discharge Capability,
All Pins Including HV Pin
Charged Device Model:
JESD22-C101
-55
TSTG
TL
ESD
-0.3
-0.3
Max.
Unit
700
4.0
8.0
9.6
50
140
120
30
7.0
7.0
700
V
mJ
1.5
W
A
V
V
V
V
Internally
Limited(10)
+150
+260
C
C
C
5.50
2.00
kV
3.00
1.25
Notes:
5. All voltage values, except differential voltages, are given with respect to the network ground terminal.
6. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
7. Non-repetitive rating: pulse width is limited by maximum junction temperature.
8. L=51 mH, starting TJ=25°C.
9. L=14 mH, starting TJ=25°C.
10. Internally limited by Over-Temperature Protection (OTP). Refer to TOTP.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
RHV
Parameter
Resistor Connect to HV Pin for Full Range Input Detection
Min.
Max.
Unit
150
250
kΩ
Thermal Resistance Table
Symbol
θJA
ψJT
Parameter
Junction-to-Air Thermal Resistance
Junction-to-Package Thermal Resistance(11)
Typ.
Unit
86
20
C/W
C/W
Note:
11. Measured on the package top surface.
© 2011 Fairchild Semiconductor Corporation
FSB117H / FSB127H / FSB147H • Rev. 1.0.7
www.fairchildsemi.com
5
FSB117H / FSB127H / FSB147H — mWSaver™ Fairchild Power Switch (FPS™)
Absolute Maximum Ratings
VDD=15 V, TA=25C unless otherwise specified.
Symbol
Parameter
Condition
Min.
ID=250µA, VGS=0 V
700
Typ.
Max.
Unit
(12)
SenseFET Section
BVDSS
IDSS
RDS(ON)
Drain-Source Breakdown Voltage
Zero-Gate-Voltage Drain Current
Drain-Source On-State
Resistance(13)
FSB117H
FSB127H
FSB147H
FSB117H
CISS
Input Capacitance
FSB127H
FSB147H
FSB117H
COSS
Output Capacitance
FSB127H
FSB147H
FSB117H
CRSS
Reverse Transfer Capacitance FSB127H
FSB147H
FSB117H
td(on)
Turn-On Delay
FSB127H
FSB147H
FSB117H
tr
Rise Time
FSB127H
FSB147H
FSB117H
td(off)
Turn-Off Delay
FSB127H
FSB147H
FSB117H
tf
Fall Time
FSB127H
FSB147H
V
VDS=700 V,
VGS=0 V
50
VDS=560 V,
VGS=0 V, TC=125C
200
μA
8.8
11.0
6.0
7.2
VGS=10 V, ID=2.5 A
2.3
2.7
VGS=0 V, VDS=25 V,
f=1 MHz
250
325
550
715
450
500
VGS=0 V, VDS=25 V,
f=1 MHz
25
33
38
50
60
72
10
15
17
26
7
21
12
34
20
50
12
35
4
18
15
40
20
50
30
70
55
120
30
70
10
30
25
60
16
42
VGS=10 V, ID=0.5 A
VGS=0 V, VDS=25 V,
f=1 MHz
VDS=350 V,
ID=1.0 A
VDS=350 V,
ID=1.0 A
VDS=350 V,
ID=1.0 A
VDS=350 V,
ID=1.0 A
Ω
pF
pF
pF
ns
ns
ns
ns
Continued on the following page…
© 2011 Fairchild Semiconductor Corporation
FSB117H / FSB127H / FSB147H • Rev. 1.0.7
www.fairchildsemi.com
6
FSB117H / FSB127H / FSB147H — mWSaver™ Fairchild Power Switch (FPS™)
Electrical Characteristics
VDD=15 V, TA=25C unless otherwise specified.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
Control Section
VDD Section
VDD-ON
UVLO Start Threshold Voltage
11
12
13
V
VDD-OFF1
UVLO Stop Threshold Voltage
5
6
7
V
VDD-OFF2
IDD-OLP Enable Threshold Voltage
8
9
10
V
VDD-OLP
VDD Voltage Threshold for HV Startup TurnOn at Protection Mode
5
6
7
V
IDD-ST
Startup Supply Current
VDD-ON – 0.16 V
30
µA
IDD-OP1
Operating Supply Current with Normal
Switching Operation
VDD=15 V, VFB=3 V
3.8
mA
IDD-OP2
Operating Supply Current without Switching
Operation
VDD=15 V, VFB=1 V
1.8
mA
IDD-OLP
Internal Sinking Current
VDD-OLP + 0.1 V
VDD-OVP
tD-VDDOVP
30
60
90
µA
VDD Over-Voltage Protection
27
28
29
V
VDD Over-Voltage Protection Debounce
Time
70
140
210
µs
5.0
mA
10
µA
115
V
HV Section
Supply Current Drawn from HV Pin
HV=120 VDC,
VDD=0 V with 10 µF
IHV-LC
Leakage Current after Startup
HV=700 V,
VDD=VDD-OFF1+1 V
VAC-ON
Brown-in Threshold Level (VDC)
VAC-OFF
Brownout Threshold Level (VDC)
IHV
tUVP
DC Voltage Applied
to HV Pin through
200 kΩ Resistor
Brownout Protection Time
1.5
105
110
VAC-ON-10
V
0.8
1.2
1.6
94
100
106
±4.0
±6.0
±8.0
20
23
s
Oscillator Section
fOSC
Frequency in Nominal Mode
tHOP
Hopping Period(12)
fOSC-G
Center Frequency
Hopping Range
20
Green-Mode Frequency
kHz
ms
26
kHz
fDV
Frequency Variation vs. VDD Deviation
VDD=11 V to 22 V
5
%
fDT
Frequency Variation vs. Temperature
Deviation(12)
TA=-40 to 105°C
5
%
Continued on the following page…
© 2011 Fairchild Semiconductor Corporation
FSB117H / FSB127H / FSB147H • Rev. 1.0.7
www.fairchildsemi.com
7
FSB117H / FSB127H / FSB147H — mWSaver™ Fairchild Power Switch (FPS™)
Electrical Characteristics (Continued)
VDD=15 V, TA=25C unless otherwise specified.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
1/4.5
1/4.0
1/3.5
V/V
15
21
27
kΩ
5.2
5.4
5.6
V
4.3
4.6
4.9
V
Feedback Input Section
AV
Internal Voltage Dividing Factor of FB Pin(12)
ZFB
Pull-Up Impedance of FB Pin
VFB-OPEN
FB Pin Pull-Up Voltage
VFB-OLP
FB Voltage Threshold to Trigger Open-Loop
Protection
FB Pin Open
tD-OLP
Delay of FB Pin Open-Loop Protection
VFB-N
FB Voltage Threshold to Exit Green Mode
VFB is Rising
VFB-G
FB Voltage Threshold to enter Green Mode
VFB is Falling
VFB-ZDC
FB Voltage Threshold to Enter Zero-Duty
State
VFB is Falling
VFB-ZDCR
FB Voltage Threshold to Exit Zero-Duty State VFB is Rising
46
56
66
ms
2.4
2.6
2.8
V
VFB-N-0.2
1.95
2.05
V
2.15
VFB-ZDC
+0.1
V
V
IPK Pin Section
VIPK-OPEN
VIPK-H
VIPK-L
IPK
ILMT-FL-H
IPK Pin Open Voltage
3.0
Internal Upper Clamping Voltage of IPK Pin
Internal Lower Clamping Voltage of IPK Pin
Internal Current Source of IPK Pin
TA=-40 to 105°C,
VIPK=2.25 V
Current Limit Plateau when IPK FSB117H
Pin Voltage is Internally Clamped FSB127H
to Upper Limit
FSB147H
VIPK=3 V,
Duty>40%
V
45
50
55
0.72
0.80
0.88
0.90
1.00
1.10
1.35
1.50
1.65
µA
A
ILMT-FL-H
-0.20
Initial Current Limit when IPK Pin
Voltage is Internally Clamped to FSB127H
Upper Limit
VIPK=3 V,
Duty=0%
Current Limit Plateau when IPK FSB117H
Pin Voltage is Internally Clamped FSB127H
to Lower Limit
FSB147H
VIPK=1.5 V,
Duty>40%
ILMT-FL-H
-0.25
A
0.36
ILMT-FL-H 0.37
0.40
0.44
0.45
0.50
0.55
0.67
0.75
0.83
A
ILMT-FL-L
-0.10
Initial Current Limit when IPK Pin
Voltage is Internally Clamped to FSB127H
Lower Limit
VIPK=1.5 V,
Duty=0%
ILMT-FL-L
-0.12
A
ILMT-FL-L 0.18
Continued on the following page…
FSB147H
© 2011 Fairchild Semiconductor Corporation
FSB117H / FSB127H / FSB147H • Rev. 1.0.7
V
1.5
FSB117H
ILMT-VA-L
V
(12)
3
FSB147H
ILMT-FL-L
4.0
(12)
FSB117H
ILMT-VA-H
3.5
www.fairchildsemi.com
8
FSB117H / FSB127H / FSB147H — mWSaver™ Fairchild Power Switch (FPS™)
Electrical Characteristics (Continued)
VDD=15 V, TA=25°C unless otherwise specified.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
100
200
ns
280
330
(14)
Current-Sense Section
tPD
Current Limit Turn-Off Delay
tLEB
Leading-Edge Blanking Time
tSS
Soft-Start Time(12)
230
5
ns
ms
GATE Section(14)
DCYMAX
Maximum Duty Cycle
70
%
Over-Temperature Protection Section (OTP)
TOTP
Junction Temperature to trigger OTP(12)
∆TOTP
(12)
Hysteresis of OTP
135
142
25
150
°C
°C
Notes:
12. Guaranteed by design; not 100% tested in production.
13. Pulse test: pulse width ≤ 300 µs, duty ≤ 2%.
14. These parameters, although guaranteed, are tested in wafer-sort process.
© 2011 Fairchild Semiconductor Corporation
FSB117H / FSB127H / FSB147H • Rev. 1.0.7
www.fairchildsemi.com
9
FSB117H / FSB127H / FSB147H — mWSaver™ Fairchild Power Switch (FPS™)
Electrical Characteristics (Continued)
Figure 4. VDD-ON vs. Temperature
Figure 5. VDD-OFF1 vs. Temperature
Figure 6. VDD-OFF2 vs. Temperature
Figure 7. VDD-OVP vs. Temperature
Figure 8. VDD-LH vs. Temperature
Figure 9.
Figure 10. VAC-ON vs. Temperature
© 2011 Fairchild Semiconductor Corporation
FSB117H / FSB127H / FSB147H • Rev. 1.0.7
IDD-OP1 vs. Temperature
Figure 11. VAC-ON – VAC-OFF vs. Temperature
www.fairchildsemi.com
10
FSB117H / FSB127H / FSB147H — mWSaver™ Fairchild Power Switch (FPS™)
Typical Characteristics
Figure 12. VFB-OPEN vs. Temperature
Figure 14.
ZFB vs. Temperature
Figure 16.
fOSC vs. Temperature
© 2011 Fairchild Semiconductor Corporation
FSB117H / FSB127H / FSB147H • Rev. 1.0.7
Figure 13. VFB-OLP vs. Temperature
Figure 15.
IPK vs. Temperature
Figure 17. fOSC-G vs. Temperature
www.fairchildsemi.com
11
FSB117H / FSB127H / FSB147H — mWSaver™ Fairchild Power Switch (FPS™)
Typical Characteristics
Startup Operation
PWM Control
The HV pin is typically connected to the AC line input
through two external diodes and one resistor (RHV), as
shown in Figure 18. When the AC line voltage is
applied, the VDD hold-up capacitor is charged by the line
voltage through the diodes and resistor. After VDD
voltage reaches the turn-on threshold voltage (VDD-ON),
the startup circuit charging VDD capacitor is switched off
and VDD is supplied by the auxiliary winding of the
transformer. Once the FSB-series starts, it continues
operation until VDD drops below 6 V (VDD-OFF1). The IC
startup time with a given AC line input voltage is:
The FSB-series employs current-mode control, as
shown in Figure 19. An opto-coupler (such as the
H11A817A) and shunt regulator (such as the KA431) are
typically used to implement the feedback network.
Comparing the feedback voltage with the voltage across
the Rsense resistor makes it possible to control the
switching duty cycle. A synchronized positive slope is
added to the SenseFET current information to guarantee
stable current-mode control over a wide range of input
voltage. The built-in slope compensation stabilizes the
current loop and prevents sub-harmonic oscillation.
VAC IN 
tSTARTUP  RHV  CDD  ln
VAC IN 
2 2

2 2

(1)
 VDD ON
Figure 19. Current Mode Control
Soft-Start
The FSB-series has an internal soft-start circuit that
progressively increases the pulse-by-pulse current limit
level of MOSFET during startup to establish the correct
working conditions for transformers and capacitors, as
shown in Figure 20. The current limit levels have nine
steps, as shown in Figure 21. This prevents transformer
saturation and reduces stress on the secondary diode
during startup.
Figure 18. Startup Circuit
Brown-in/out Function
The HV pin can detect the AC line voltage using a
switched voltage divider that consists of external
resistor (RHV) and internal resistor (RLS), as shown in
Figure 18. The internal line sensing circuit detects the
real RMS value of the line voltage using sampling circuit
and peak detection circuit. Since the voltage divider
causes power consumption when it is switched on, the
switching is driven by a signal with a very narrow pulse
width to minimize power loss. The sampling frequency
is adaptively changed according to the load condition to
minimize the power consumption in light-load condition.
Based on the detected line voltage, brown-in and
brownout thresholds are determined. Since the internal
resistor (RLS) of the voltage divider is much smaller than
RHV, the thresholds are given as:
VBROWN IN (RMS ) 
RHV VAC ON

200k
2
VBROWN OUT (RMS ) 
RHV VAC OFF

200k
2
© 2011 Fairchild Semiconductor Corporation
FSB117H / FSB127H / FSB147H • Rev. 1.0.7
(2)
(3)
Figure 20. Soft-Start and Current-Limit Circuit
www.fairchildsemi.com
12
FSB117H / FSB127H / FSB147H — mWSaver™ Fairchild Power Switch (FPS™)
Functional Description
AX-CAP™ to Remove X-Cap Discharge Resistor
The EMI filter in the front end of the switched mode
power supply typically includes a capacitor across the
AC line connector, as shown in Figure 24. Most of the
safety regulations, such as UL 1950 and IEC61010-1,
require the capacitor be discharged to a safe level within
a given time after unplugged from the power outlet.
Typically a discharge resister across the capacitor is
used to ensure the capacitor is discharged naturally,
which however introduces power loss of the power
supply. As power level increases, the EMI filter capacitor
tends to increase, requiring a smaller discharge resistor
to maintain same discharge time. This typically results in
more power dissipation in high-power applications. The
innovative AX-CAP™ technology intelligently discharges
the filter capacitor only when the power supply is
unplugged from the power outlet. Since the AX-CAP™
discharge circuit is disabled in normal operation, the
power loss in the EMI filter size can be virtually removed.
Figure 21. Current Limit Variation During Soft-Start
Adjustable Peak Current Limit & H/L Line
Compensation for Constant Power Limit
To make the limited output power constant regardless
of the line voltage condition, a special current-limit
profile with sample and hold is used (as shown in
Figure 22). The current-limit level is sampled and held
at the falling edge of gate drive signal as shown in
Figure 23. Then, the sampled current limit level is used
for the next switching cycle. The sample-and-hold
function prevents sub-harmonic oscillation in currentmode control.
The current-limit level increases as the duty cycle
increases, which reduces the current limit as duty cycle
decreases. This allows lower current-limit level for highline voltage condition where the duty cycle is smaller
than that of low line. Therefore, the limited maximum
output power can remain constant even for a wide input
voltage range.
The peak current limit is programmable using a resistor
on the IPK pin. The internal current 50 µA source for the
IPK pin generates voltage drop across the resistor. The
voltage of the IPK pin determines the current-limit level.
Since the upper and lower clamping voltage of the IPK
pin are 3 V and 1.5 V, respectively, the suggested
resistor value is from 30 kΩ to 60 kΩ.
Figure 24. AX-CAP™ Circuit
Green Mode
The FSB-series modulates the PWM frequency as a
function of FB voltage, as shown in Figure 25. Since the
output power is proportional to the FB voltage in currentmode control, the switching frequency decreases as load
decreases. In heavy-load conditions, the switching
frequency is 100 kHz. Once VFB decreases below VFB-N
(2.6 V), the PWM frequency linearly decreases from
100 kHz to 23 kHz to reduce switching losses at lightload condition. As VFB decreases to VFB-G (2.4 V), the
switching frequency is fixed at 23 kHz.
As VFB falls below VFB-ZDC (2.1 V), the FSB-series enters
Burst Mode operation, where PWM switching is
disabled. Then, the output voltage starts to drop, causing
the feedback voltage to rise. Once VFB rises above VFBZDCR, switching resumes. Burst Mode alternately enables
and disables switching, thereby reducing switching loss
to reduce power consumption, as shown in Figure 26.
Figure 22. ILMT vs. PWM Turn-On Time
Figure 23. Current Limit Variation with Duty Cycle
© 2011 Fairchild Semiconductor Corporation
FSB117H / FSB127H / FSB147H • Rev. 1.0.7
Figure 25.
PWM Frequency
www.fairchildsemi.com
13
FSB117H / FSB127H / FSB147H — mWSaver™ Fairchild Power Switch (FPS™)
mWSaver™ Technology
Over-Temperature Protection (OTP)
The SenseFET and the control IC are integrated in one
package. This makes it easy for the control IC to detect
the abnormal over temperature of the SenseFET. If the
temperature exceeds approximately 140°C, the OTP is
triggered and the MOSFET remains off. When the
junction temperature drops by 25°C from OTP
temperature, the FSB-series resumes normal operation.
Two-Level UVLO
Since all the protections of the FSB-series are autorestart, the power supply repeats shutdown and restartup until the fault condition is removed. FSB-series
has two-level UVLO, which is enabled when protection is
triggered, to delay the re-startup by slowing down the
discharge of VDD. This effectively reduces the input
power of the power supply during the fault condition,
minimizing the voltage/current stress of the switching
devices. Figure 28 shows the normal UVLO operation
and two-step UVLO operation. When VDD drops to 6 V
without triggering the protection, PWM stops switching
and VDD is charged up by the HV startup circuit.
Meanwhile, when the protection is triggered, FSB-series
has a different VDD discharge profile. Once the protection
is triggered, the IC stops switching and VDD drops. When
VDD drops to 9 V, the operating current becomes very
small and VDD is slowly discharged. When VDD is
naturally discharged down to 6 V, the protection is reset
and VDD is charged up by the HV startup circuit. Once
VDD reaches 12 V, the IC resumes switching operation.
Figure 26. Burst-Mode Operation
Protections
The FSB-series provides protection function, that
include Overload / Open-Loop Protection (OLP), OverVoltage Protection (OVP), and Over-Temperature
Protection (OTP). All the protections are implemented
as Auto-Restart Mode. Once the fault condition is
detected, switching is terminated and the SenseFET
remains off. This causes VDD to fall. When VDD falls to
6 V, the protection is reset and HV startup circuit
charges VDD up to 12 V, allowing re-startup.
Open-Loop / Overload Protection (OLP)
Because of the pulse-by-pulse current-limit capability,
the maximum peak current through the SenseFET is
limited and maximum input power is limited. If the
output consumes more than the limited maximum
power, the output voltage (VO) drops below the set
voltage. Then the current through the opto-coupler LED
and the transistor become virtually zero and FB voltage
is pulled HIGH as shown in Figure 27. If feedback
voltage is above 4.6 V for longer than 56 ms, OLP is
triggered. This protection is also triggered when the
feedback loop is open due to a soldering defect.
.
Figure 27. OLP Operation
VDD Over-Voltage Protection (OVP)
If the secondary-side feedback circuit malfunctions or a
solder defect causes an opening in the feedback path,
the current through the opto-coupler transistor becomes
virtually zero. Then feedback voltage climbs up in a
similar manner to the overload situation, forcing the
preset maximum current to be supplied to the SMPS
until the overload protection triggers. Because more
energy than required is provided to the output, the
output voltage may exceed the rated voltage before the
overload protection triggers, resulting in the breakdown
of the devices in the secondary side. To prevent this
situation, an OVP circuit is employed. Since VDD voltage
© 2011 Fairchild Semiconductor Corporation
FSB117H / FSB127H / FSB147H • Rev. 1.0.7
Figure 28. Two-Level UVLO
www.fairchildsemi.com
14
FSB117H / FSB127H / FSB147H — mWSaver™ Fairchild Power Switch (FPS™)
is proportional to the output voltage by the transformer
coupling, the over voltage of output is indirectly detected
using VDD voltage. The OVP is triggered when VDD
voltage reaches 28 V. Debounce time (typically 150 µs) is
applied to prevent false triggering by switching noise.
Application
Fairchild Devices
Input Voltage Range
Output
Standby Auxiliary Power
FSB127H
85 VAC ~ 265 VAC
5 V / 3.2 A
Figure 29. Schematic of Typical Application Circuit
© 2011 Fairchild Semiconductor Corporation
FSB117H / FSB127H / FSB147H • Rev. 1.0.7
www.fairchildsemi.com
15
FSB117H / FSB127H / FSB147H — mWSaver™ Fairchild Power Switch (FPS™)
Typical Application Circuit
Transformer Specification


Core: EI 22
Bobbin: EI 22
EI - 22
1
10 N
5V
Np/2 2
Np/2 3
6
Na 4
5
Figure 30. Transformer Specification
Pin (S → F)
Wire
Turns
Winding Method
4→5
0.15φ×1
12
Solenoid Winding
31
Solenoid Winding
5
Solenoid Winding
31
Solenoid Winding
Pin
Specification
Remark
Primary-Side Inductance
1－3
900 H ±10%
100 kHz, 1 V
Primary-Side Effective Leakage
1－3
< 30 H Maximum
Short All Other Pins
Na
Insulation: Polyester Tape t = 0.025 mm, 1-Layer
Np/2
3→2
0.27φ×1
Insulation: Polyester Tape t = 0.025 mm, 2-Layer
N5V
6 → 10
0.55φ×2
Insulation: Polyester Tape t = 0.025 mm, 2-Layer
Np/2
2→1
0.27φ×1
Insulation: Polyester Tape t = 0.025 mm, 2-Layer
© 2011 Fairchild Semiconductor Corporation
FSB117H / FSB127H / FSB147H • Rev. 1.0.7
www.fairchildsemi.com
16
FSB117H / FSB127H / FSB147H — mWSaver™ Fairchild Power Switch (FPS™)
Typical Application Circuit (Continued)
[
]
0.400 10.160
0.355 9.017
8
5
PIN 1 INDICATOR
1
]
0.015 [0.389] GAGE PLANE
[
0.280 7.112
0.240 6.096
4
HALF LEAD 4X
0.005 [0.126]
FULL LEAD 4X
0.005 [0.126] MIN
[
0.195 4.965
0.115 2.933
MAX 0.210 [5.334]
]
[
0.325 8.263
0.300 7.628
]
SEATING PLANE
[
]
0.150 3.811
0.115 2.922
C
MIN 0.015 [0.381]
0.100 [2.540]
[
0.022 0.562
0.014 0.358
0.300 [7.618]
[
] 4X
0.045 1.144
0.030 0.763
]
[
0.070 1.778
0.045 1.143
0.10
C
] 4X
0.430 [10.922]
MAX
NOTES:
A) THIS PACKAGE CONFORMS TO
JEDEC MS-001 VARIATION BA
B) CONTROLING DIMS ARE IN INCHES
C) DIMENSIONS ARE EXCLUSIVE OF BURRS,
MOLD FLASH, AND TIE BAR EXTRUSIONS.
D) DIMENSIONS AND TOLERANCES PER ASME
Y14.5M -1982
E) DRAWING FILENAME AND REVSION: MKT-N08MREV1.
Figure 31.
8-Pin, Dual In-Line Package (DIP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2011 Fairchild Semiconductor Corporation
FSB117H / FSB127H / FSB147H • Rev. 1.0.7
www.fairchildsemi.com
17
FSB117H / FSB127H / FSB147H — mWSaver™ Fairchild Power Switch (FPS™)
Physical Dimensions
FSB117H / FSB127H / FSB147H — mWSaver™ Fairchild Power Switch (FPS™)
© 2011 Fairchild Semiconductor Corporation
FSB117H / FSB127H / FSB147H • Rev. 1.0.7
www.fairchildsemi.com
18