FAN302HLMY_F117 PWM Controller for Low Standby Power BatteryCharger Applications — mWSaver™ Technology Features Description The FAN302HLMY_F117 advanced PWM controller significantly simplifies isolated power supply design that requires CC regulation of the output. The output current is precisely estimated with information in the primary side of the transformer and controlled with an internal compensation circuit. This removes the output current sensing loss and eliminates all external Control Circuitry (CC). The Green-Mode function, with an extremely low operating current (200µA) in Burst Mode, maximizes the light-load efficiency, enabling conformance to worldwide Standby Mode efficiency guidelines. mWSaver™ Technology Provides Industry’s Best-in-Class Standby Power - Achieves <10mW Below Energy Star’s 5-Star Level: <30mW - Proprietary 500V High-Voltage JFET Startup Reduces Startup Resistor Loss - Low Operation Current in Burst Mode: 350µA Maximum Constant-Current (CC) Control without SecondaryFeedback Circuitry Fixed PWM Frequency at 85kHz with Frequency Hopping to Reduce EMI High-Voltage Startup Cycle-by-Cycle Current Limiting Low Operating Current: 3.5mA Peak-Current-Mode Control with Slope Compensation VDD Over-Voltage Protection (Auto-Restart) Integrated protections include two-level pulse-by-pulse current limit, Over-Voltage Protection (OVP), brownout protection, and Over-Temperature Protection (OTP). Compared with a conventional approach using an external control circuit in the secondary side for CC regulation, the FAN302HLMY_F117 can reduce total cost, component count, size, and weight; while simultaneously increasing efficiency, productivity, and system reliability. Maximum Typical Minimum VO VS Over-Voltage Protection (Latch Mode) VDD Under-Voltage Lockout (UVLO) Gate Output Maximum Voltage Clamped at 15V Fixed Over-Temperature Protection (Latch Mode) Available in an 8-Lead SOIC Package Applications Battery Chargers for Cellular Phones, Cordless Phones, PDAs, Digital Cameras, and Power Tools Replaces Linear Regulators and RCC SMPS IO Figure 1. Typical Output V-I Characteristic Ordering Information Part Number Operating Temperature Range Package Packing Method FAN302HLMY_F117 -40°C to +105°C 8-Lead, Small Outline Package (SOIC), JEDEC MS-012, .150-Inch Narrow Body Tape & Reel © 2012 Fairchild Semiconductor Corporation FAN302HLMY_F117 • Rev. 1.0.1 www.fairchildsemi.com FAN302HLMY_F117 — mWSaver™ PWM Controller for Low Standby Power Battery-Charger Applications June 2012 FAN302HLMY_F117— mWSaver™ PWM Controller for Low Standby Power Battery-Charger Applications Application Diagram Figure 2. Typical Application Internal Block Diagram Figure 3. Functional Block Diagram © 2012 Fairchild Semiconductor Corporation FAN302HLMY_F117 • Rev. 1.0.1 www.fairchildsemi.com 2 F- Fairchild Logo Z: Assembly Plant Code X: Year Code Y: Week Code TT: Die Run Code T: M=SOIC P: Y= Green Package M: Manufacture Flow Code Figure 4.Top Mark Pin Configuration CS HV GATE NC VDD FB VS GND Figure 5. Pin Assignments Pin Definitions Pin # Name Description 1 CS 2 GATE 3 VDD 4 VS 5 GND 6 FB Feedback. Typically, an opto-coupler is connected to this pin to provide feedback information to the internal PWM comparator. This feedback is used to control the duty cycle in CV regulation. 7 NC No Connect 8 HV High Voltage. This pin connects to the DC bus for high-voltage startup. Current Sense. This pin connects a current-sense resistor to sense the MOSFET current for Peak-Current-Mode control for output regulation. The current-sense information is also used to estimate the output current for CC regulation. PWM Signal Output. This pin has an internal totem-pole output driver to drive the power MOSFET. It is internally clamped at 15V. Power Supply. IC operating current and MOSFET driving current are supplied through this pin. This pin is typically connected to an external VDD capacitor. Voltage Sense. This pin detects the output voltage information and diode current discharge time based on the voltage of the auxiliary winding. Ground © 2012 Fairchild Semiconductor Corporation FAN302HLMY_F117 • Rev. 1.0.1 www.fairchildsemi.com 3 FAN302HLMY_F117— mWSaver™ PWM Controller for Low Standby Power Battery-Charger Applications Marking Information Stresses exceeding the Absolute Maximum Ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VHV Parameter Min. HV Pin Input Voltage (1,2) Max. Unit 500 V VVDD DC Supply Voltage 30 V VVS VS Pin Input Voltage -0.3 7.0 V VCS CS Pin Input Voltage -0.3 7.0 V VFB FB Pin Input Voltage -0.3 7.0 V PD Power Dissipation (TA=25°C) 660 mW θJA Thermal Resistance (Junction-to-Air) 150 °C/W θJC Thermal Resistance (Junction-to-Case) 39 °C/W TJ TSTG TL ESD Operating Junction Temperature -40 +150 °C Storage Temperature Range -55 +150 °C +260 °C Lead Temperature, (Wave Soldering or IR, 10 Seconds) Electrostatic Discharge Capability Human Body Model, JEDEC:JESD22_A114 (3) (Except HV Pin) 5000 Charged Device Model, JEDEC:JESD22_C101 (Except HV Pin)(3) 1500 V Notes: 1. All voltage values, except differential voltages, are given with respect to GND pin. 2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. 3. ESD ratings including the HV pin: HBM=400V, CDM=750V. © 2012 Fairchild Semiconductor Corporation FAN302HLMY_F117 • Rev. 1.0.1 www.fairchildsemi.com 4 FAN302HLMY_F117— mWSaver™ PWM Controller for Low Standby Power Battery-Charger Applications Absolute Maximum Ratings VDD=15V and TA=25°C unless noted. Symbol Parameter Condition Min. Typ. Max. Unit HV Section VHV-MIN Minimum Startup Voltage on HV Pin IHV Supply Current Drawn from HV Pin VHV=100V, VDD=0V, Controller Off Leakage Current Drawn from HV Pin VHV=500V, VDD=15V (Controller On with Auxiliary Supply) Continuous Operation Voltage Limited by VDD Over-Voltage Protection (OVP) VDD-ON Turn-On Threshold Voltage VDD Rising 15 VDD-OFF Turn-Off Threshold Voltage VDD Falling 4.7 VDD-LH Threshold Voltage for Latch-Off Release VDD Falling 2.5 IDD-ST Startup Current VDD=VDD-ON – 0.16V IDD-OP Operating Supply Current VDD=18V, f=fOSC, CGATE=1nF IDD-BURST Burst-Mode Operating Supply Current VDD=8V, CGATE=1nF VDD-OVP VDD Over-Voltage Protection Level tD-VDDOVP VDD Over-Voltage Protection Debounce Time IHV-LC 0.8 50 V 1.5 5.0 mA 0.8 3.0 μA 25 V 16 17 V 5.0 5.3 V 400 450 μA 3.5 4.0 mA VDD Section VOP 25.0 f=85kHz V 200 350 μA 26.5 28.0 V 100 180 μs 85 88 Oscillator Section fOSC Frequency Center Frequency VCS=5V, VS=2.5, VFB=5V 82 Hopping Range fOSC-CM-MIN Minimum Frequency for Continuous Conduction Mode (CCM) Prevention Circuit(4) fOSC-CCM Minimum Frequency in Constant Current (CC) Regulation ±3 VCS=5V, VS=0V kHz 13 18 23 kHz 23 26 29 kHz 1/3.5 1/3.0 1/2.5 V/V 38 42 44 kΩ Feedback Input Section AV Internal Voltage Scale-Down Ratio of FB Pin(5) ZFB FB Pin Input Impedance VFB-OPEN FB Pin Pull-Up Voltage FB Pin Open VFB-L FB Threshold to Disable Gate Drive in Burst Mode VFB Falling,VCS=5V, VS=0V 1.2 1.4 1.6 V VFB-H FB Threshold to Enable Gate Drive in Burst Mode VFB Rising,VCS=5V, VS=0V 1.3 1.5 1.7 V +130 +140 +150 °C 5.3 V Over-Temperature Protection Section TOTP Threshold for Over-Temperature Protection (OVP) Continued on the following page… © 2012 Fairchild Semiconductor Corporation FAN302HLMY_F117 • Rev. 1.0.1 www.fairchildsemi.com 5 FAN302HLMY_F117— mWSaver™ PWM Controller for Low Standby Power Battery-Charger Applications Electrical Characteristics VDD=15V and TA=25°C unless noted. Symbol Parameter Condition Min. Typ. Max. Unit 8.75 Voltage-Sense Section ITC 10.00 11.25 μA VVS-CM-MIN VS Sampling Voltage to Switch to the Second Pulse-by-Pulse Current Limit in Power Limit Mode(6) Bias Current VCS=5V 0.55 V VVS-CM-MAX VS Sampling Voltage to Switch Back to the Normal Pulse-by-Pulse Current Limit(6) 0.75 V VSN-CC VS Sampling Voltage to Start Frequency Decreasing in CC Mode VCS=5V, fS1=fOSC-2KHz 2.05 2.15 2.25 V VSG-CC Vs Sampling Voltage to End Frequency Decreasing in CC Mode VCS=5V, fS2=fOSC-CCM +2KHz 0.45 0.70 0.95 V SG-CC Frequency Decreasing Slope of CC Regulation SG-CC= (fS1-fS2) / (VSN-CCVSG-CC) 30 38 46 kHz/V VVS-OFFSET ZCD Comparator Internal Offset Voltage(6) 200 VVS-OVP Output Over-Voltage Protection with VS Sampling Voltage tVS-OVP Output Over-Voltage Protection Debounce fOSC=85kHz Time 2.70 mV 2.80 2.85 V 100 180 μs Current-Sense Section VVR Internal Reference Voltage for CC Regulation VCCR Variation Test Voltage on CS Pin for CC Output (Non-Inverting Input of Error Amplifier for CC Regulation) VSTH Normal Current Limit Threshold Voltage VSTH-VA Second Current Limit Threshold Voltage, Power Limit Mode (VS<VVS-CM-MAX) tPD 2.500 2.525 V 2.405 2.430 2.455 V VVS=0.3V GATE Output Turn-Off Delay VCS=5V, VVS=2.5, VFB=5V (Test Mode) tMIN Minimum On Time tLEB Leading-Edge Blanking Time VSLOPE VCS=0.47V 2.475 (6) Slope Compensation (6) 0.8 V 0.30 V 100 150 ns 430 530 630 ns 100 150 200 ns Maximum Duty Cycle 0.3 V GATE Section DMAX Maximum Duty Cycle 64 67 70 % VGATE-L Output Voltage Low VDD=25V, IO=10mA 0 1.5 V VGATE-H Output Voltage High VDD=8V, IO=1mA 5 8 V VGATE-H Output Voltage High VDD=5.5V, IO=1mA 4.0 5.5 V tr Rising Time VDD=15V, CGATE=1nF 100 140 180 ns tf Falling Time VDD=15V, CGATE=1nF 30 50 70 ns Gate Output Clamping Voltage VDD=25V 13 15 17 V VGATECLAMP Notes: 4. fOSC-CM-MIN occurs when the power unit enters CCM operation. 5. AV is a scale-down ratio of the internal voltage divider of the FB pin. 6. Guaranteed by design; not production tested. © 2012 Fairchild Semiconductor Corporation FAN302HLMY_F117 • Rev. 1.0.1 www.fairchildsemi.com 6 FAN302HLMY_F117— mWSaver™ PWM Controller for Low Standby Power Battery-Charger Applications Electrical Characteristics (Continued) 5.04 16.5 5.01 VDD-OFF (V) VDD-ON (V) 16.8 16.2 15.9 4.98 4.95 15.6 4.92 15.3 4.89 15.0 4.86 -40 -30 -15 0 25 50 75 85 100 125 -40 -30 -15 0 Temperature (ºC) 50 75 85 100 125 Figure 7. VDD Turn-Off Threshold Voltage (VDD-OFF) vs. Temperature 4.0 0.23 3.7 0.22 IDD-BURST (µA) IDD-OP (mA) Figure 6. VDD Turn-On Threshold Voltage (VDD-ON) vs. Temperature 3.4 3.1 2.8 2.5 0.21 0.20 0.19 0.18 2.2 0.17 -40 -30 -15 0 25 50 75 85 100 125 -40 -30 -15 0 Temperature (ºC) 25 50 75 85 100 125 Temperature (ºC) Figure 8. Operating Current (IDD-OP) vs. Temperature Figure 9. Burst Mode Operating Current (IDD-BURST) vs. Temperature 29 1.50 28 1.45 VFB-L (V) fOSC-CCM (KHz) 25 Temperature (ºC) 27 1.40 26 1.35 25 1.30 24 1.25 1.20 23 -40 -30 -15 0 25 50 75 85 100 -40 125 Figure 10. CC Regulation Minimum Frequency (fOSC-CCM) vs. Temperature © 2012 Fairchild Semiconductor Corporation FAN302HLMY_F117 • Rev. 1.0.1 -30 -15 0 25 50 75 85 100 125 Temperature (ºC) Temperature (ºC) Figure 11. Enter Zero-Duty Cycle of FB Voltage (VFB-L) vs. Temperature www.fairchildsemi.com 7 FAN302HLMY_F117— mWSaver™ PWM Controller for Low Standby Power Battery-Charger Applications Typical Performance Characteristics 2.95 1.70 2.90 VFB-H (V) VVS-OVP (V) 1.80 1.60 2.85 1.50 2.80 1.40 2.75 1.30 2.70 1.20 2.65 -40 -30 -15 0 25 50 75 85 100 125 -40 -30 -15 0 Temperature (ºC) 25 50 75 85 100 Figure 13. VS Over-Voltage Protection (VVS-OVP) vs. Temperature 2.53 2.50 2.52 2.48 VVR (V) VCCR (V) Figure 12. Leave Zero Duty Cycle of FB Voltage (VFB-H) vs. Temperature 2.51 2.46 2.50 2.44 2.49 2.42 2.48 2.40 2.47 2.38 -40 -30 -15 0 25 50 75 85 100 125 -40 -30 -15 Temperature (ºC) 0 25 50 75 85 100 125 Temperature (ºC) Figure 14. Reference Voltage of CS (VVR) vs. Temperature Figure 15.Variation Voltage on CS Pin for ConstantCurrent Regulation (VCCR) vs. Temperature 2.20 0.683 2.18 0.680 VSG-CC (V) VSN-CC (V) 125 Temperature (ºC) 2.16 2.14 0.677 0.674 2.12 0.671 2.10 0.668 2.08 0.665 -40 -30 -15 0 25 50 75 85 100 125 -40 Temperature (ºC) -30 -15 0 25 50 75 85 100 125 Temperature (ºC) Figure 16. Starting Voltage of Frequency Decreasing Figure 17. Ending Voltage of Frequency Decreasing of of CC Regulation (VSN-CC) vs. Temperature CC Regulation (VSG-CC) vs. Temperature © 2012 Fairchild Semiconductor Corporation FAN302HLMY_F117 • Rev. 1.0.1 www.fairchildsemi.com 8 FAN302HLMY_F117— mWSaver™ PWM Controller for Low Standby Power Battery-Charger Applications Typical Performance Characteristics 0.45 0.83 0.40 0.81 VSTH-VA (V) VSTH (V) 0.82 0.80 0.79 0.78 0.35 0.30 0.25 0.77 0.20 0.76 0.75 0.15 -40 -30 -15 0 25 50 75 85 100 125 -40 -30 -15 Temperature (ºC) 0 25 50 75 85 100 125 Temperature (ºC) Figure 18. Threshold Voltage for Current Limit (VSTH) vs. Temperature Figure 19. Threshold Voltage for Current Limit at Power Mode (VSTH-VA) vs. Temperature 590 tMIN (ns) 580 570 560 550 540 530 -40 -30 -15 0 25 50 75 85 100 125 Temperature (ºC) Figure 21.Leading-Edge Blanking Time (tLEB) vs. Temperature 67.6 16.5 67.4 16.0 VGATE-CLAMP (V) DCYMAX (%) Figure 20. Minimum On Time (tMIN) vs. Temperature 67.2 67.0 66.8 66.6 15.5 15.0 14.5 14.0 66.4 13.5 -40 -30 -15 0 25 50 75 85 100 125 -40 Temperature (ºC) -15 0 25 50 75 85 100 125 Temperature (ºC) Figure 22. Maximum Duty Cycle (DCYMAX) vs. Temperature © 2012 Fairchild Semiconductor Corporation FAN302HLMY_F117 • Rev. 1.0.1 -30 Figure 23. Gate Output Clamp Voltage (VGATE-CLAMP) vs. Temperature www.fairchildsemi.com 9 FAN302HLMY_F117— mWSaver™ PWM Controller for Low Standby Power Battery-Charger Applications Typical Performance Characteristics Basic Control Principle VEA.I Figure 24 shows the internal PWM control circuit. The constant voltage (CV) regulation is implemented in the same way as the conventional isolated power supply, where the output voltage is sensed using a voltage divider and compared with the internal 2.5V reference of a shunt regulator (KA431) to generate a compensation signal. The compensation signal is transferred to the primary side using an opto-coupler and scaled down through attenuator Av, generating the VEA.V signal. Then the error signal VEA.V is applied to the PWM comparator (PWM.V) to determine the duty cycle. VEA.V VEA.V VEA.I VSAW Gate PWM.V PWM.I Meanwhile, the CC regulation is implemented internally without directly sensing the output current. The output current estimator reconstructs output current information (VCCR) using the transformer primary-side current and diode current discharge time. Then VCCR is compared with a reference voltage (2.5V) by an internal error amplifier, generating the VEA.I signal to determine the duty cycle. OSC CLK CV Regulation CC Regulation Figure 25. PWM Operation for CC and CV Output Current Estimation Figure 26 shows the key waveform of a flyback converter operating in Discontinuous Conduction Mode (DCM), where the secondary-side diode current reaches zero before the next switching cycle begins. Since the output current estimator is designed for DCM operation, the power stage should be designed such that DCM is guaranteed for the entire operating range. The output current is obtained by averaging the triangular output diode current area over a switching cycle: The two error signals, VEA.I and VEA.V, are compared with an internal sawtooth waveform (VSAW) by PWM comparators PWM.I and PWM.V to determine the duty cycle. As shown in Figure 25, the outputs of two comparators (PWM.I and PWM.V) are combined with an OR gate and used as a reset signal of flip-flop to determine the MOSFET turn-off instant. The lower signal, VEA.V or VEA.I, determines the duty cycle, as shown in Figure 25. During CV regulation, VEA.V determines the duty cycle while VEA.I is saturated to HIGH. During CC regulation, VEA.I determines the duty cycle while VEA.V is saturated to HIGH. NP t DIS • (1) NS 2tS where IPK is the peak value of the primary-side current; NP and NS are the number of turns of transformer primary-side and secondary-side, respectively; tDIS is the diode current discharge time; and tS is the switching period. IO =< ID > AVG = IPK With a given current sensing resistor, the output current can be programmed as: 1.25 NP (2) K • RSENSE NS where K is the design parameter of IC, which is 10.5. IO = The peak value of primary-side current is obtained by an internal peak detection circuit, while diode current discharge time is obtained by detecting the diode current zero-crossing instant. Since the diode current cannot be sensed directly with primary-side control, Zero Crossing Detection (ZCD) is accomplished indirectly by monitoring the auxiliary winding voltage. When the diode current reaches zero, the transformer winding voltage begins to drop by the resonance between the MOSFET output capacitance and the transformer magnetizing inductance. To detect the starting instant of the resonance, the VS is sampled at 85% of diode current discharge time of the previous switching cycle, then compared with the instantaneous VS voltage. When instantaneous VS drops below the sampled voltage by more than 200mV, ZCD of diode current is obtained, as shown in Figure 27. Figure 24. Internal PWM Control Circuit © 2012 Fairchild Semiconductor Corporation FAN302HLMY_F117 • Rev. 1.0.1 www.fairchildsemi.com 10 FAN302HLMY_F117 — mWSaver™ PWM Controller for Low Standby Power Battery-Charger Applications Operational Description I PK ⋅ NP NS < I D > AVG = I O Figure 26. Key Waveforms of DCM Flyback Converter Figure 28. tDIS Variation in CC Mode Figure 29. Frequency Reduction with VSH Figure 27. Detailed Waveform for ZCD Frequency Reduction in CC Mode An important design consideration is that the transformer guarantee DCM operation across the whole range since the output current is properly estimated only in DCM operation. As can be seen in Figure 28, the discharge time (tDIS) of the diode current increases as the output voltage decreases in CC Mode. The converter tends to go into CCM as output voltage drops in CC Mode when operating at the fixed switching frequency. To prevent this CCM operation while maintaining good output current estimation in DCM, FAN302HLMY_F117 decreases switching frequency as output voltage drops, as shown in Figure 28 and Figure 29. FAN302HLMY_F117 indirectly monitors the output voltage by the sample-and-hold voltage (VSH) of VS, which is taken at 85% of diode current discharge time of the previous switching cycle, as shown in Figure 27. Figure 30 shows how the frequency reduces as the sample-and-hold voltage of VS decreases. © 2012 Fairchild Semiconductor Corporation FAN302HLMY_F117 • Rev. 1.0.1 Δf = SG −CC ΔV Figure 30. Frequency Reduction Curve in CC Regulation www.fairchildsemi.com 11 FAN302HLMY_F117 — mWSaver™ PWM Controller for Low Standby Power Battery-Charger Applications I PK Even if the power supply is designed to operate in DCM, it can go into CCM when there is not enough design margin to cover all the circuit parameter variations and operating conditions. FAN302HLMY_F117 has a CCMprevention function that delays the next cycle turn-on of MOSFET until ZCD on the VS pin is obtained, as shown in Figure 31. To guarantee stable DCM operation, FAN302HLMY_F117 prohibits the turn-on of the next switching cycle for 10% of its switching period after ZCD is obtained. In Figure 31, the first switching cycle has ZCD before 90% of its original switching period and, therefore, the turn-on instant of the next cycle is determined without being affected by the ZCD instant. The second switching cycle does not have ZCD by the end of the original switching period; thus, the turn-on of the third switching cycle occurs after ZCD is obtained, with a delay of 10% of its original switching period. The minimum switching frequency that CCM prevention function allows is 18kHz (fOSC-CM-MIN). If the ZCD is not given until the end of maximum switching period of 55.6µs (1/18kHz), the converter can go into CCM operation, losing output regulation. Figure 32. Power Limit Mode Operation High-Voltage Startup Figure 33 shows the high-voltage (HV) startup circuit. Internally, JFET is used to implement the high-voltage current source, whose characteristics are shown in Figure 34. Technically, the HV pin can be directly connected to the DC link (VDL). To improve reliability and surge immunity; it is typical to use about a 100kΩ resistor between the HV pin and the DC link. The actual HV current with given DC link voltage and startup resistor is determined by the intersection of V-I characteristics line and load line, as shown in Figure 34. During startup, the internal startup circuit is enabled and the DC link supplies the current, IHV, to charge the holdup capacitor, CVDD, through RSTART. When the VDD voltage reaches VDD-ON, the internal HV startup circuit is disabled and the IC starts PWM switching. Once the HV startup circuit is disabled, the energy stored in CVDD should supply the IC operating current until the transformer auxiliary winding voltage reaches the nominal value. Therefore, CVDD should be designed to prevent VDD from dropping to VDD-OFF before the auxiliary winding builds up enough voltage to supply VDD. Figure 31. CCM Prevention Function Power Limit Mode When the sampled voltage of VS (VSH) drops below VSCM-MIN (0.55V), FAN302HLMY_F117 enters constant Power Limit Mode, where the primary-side current-limit voltage (VCS) changes from VSTH (0.8V) to VSTH-VA (0.3V) to avoid VS sampling and ZCD, as shown in Figure 32. Once VS sampling voltage is higher than VS-CM-MAX (0.75V), the VCS returns to VSTH. This mode prevents the power supply from going into CCM and losing output regulation when the output voltage is too low. This effectively protects the power supply when there is a fault condition in the load, such as output short or overload. This mode also implements soft-start by limiting the transformer current until VS sampling voltage reaches VS-CM-MAX (0.75V). Figure 33. HV Startup Circuit © 2012 Fairchild Semiconductor Corporation FAN302HLMY_F117 • Rev. 1.0.1 www.fairchildsemi.com 12 FAN302HLMY_F117 — mWSaver™ PWM Controller for Low Standby Power Battery-Charger Applications CCM Prevention Function VDL − VHV RHV VDL RHV Figure 36. Burst-Mode Operation VDL Slope Compensation Figure 34.V-I Characteristics of HV Pin The sensed voltage across the current-sense resistor is used for Current-Mode control and pulse-by-pulse current limiting. A synchronized ramp signal with positive slope is added to the current sense information at each switching cycle, improving noise immunity of Current-Mode control. Frequency Hopping EMI reduction is accomplished by frequency hopping, which spreads the energy over a wider frequency range than the bandwidth of the EMI test equipment. The frequency-hopping circuit changes the switching frequency progressively between 82kHz and 88kHz with a period of tp, as shown in Figure 35. Protections The self-protection functions include VDD Over-Voltage Protection (OVP), internal Over-Temperature Protection (OTP), VS Over-Voltage Protection (OVP), and brownout protection. VDD OVP and brownout protection are implemented as Auto-Restart Mode, while the VS OVP and internal OTP are implemented as Latch Mode. When an Auto-Restart Mode protection is triggered, switching is terminated and the MOSFET remains off, causing VDD to drop. When VDD drops to the VDD turn-off voltage of 5V; the protection is reset, the internal startup circuit is enabled, and the supply current drawn from the HV pin charges the hold-up capacitor. When VDD reaches the turn-on voltage of 16V, normal operation resumes. In this manner, auto-restart alternately enables and disables MOSFET switching until the abnormal condition is eliminated, as shown in Figure 37. When a Latch Mode protection is triggered, PWM switching is terminated and the MOSFET remains off, causing VDD to drop. When VDD drops to the VDD turn-off voltage of 5V, the internal startup circuit is enabled without resetting the protection and the supply current drawn from HV pin charges the hold-up capacitor. Since the protection is not reset, the IC does not resume PWM switching even when VDD reaches the turn-on voltage of 16V, disabling HV startup circuit. Then VDD drops down to 5V. In this manner, the Latch Mode protection alternately charges and discharges VDD until there is no more energy in the DC link capacitor. The protection is reset when VDD drops to 2.5V, which is allowed only after the power supply is unplugged from the AC line, as shown in Figure 38. Figure 35. Frequency Hopping Burst-Mode Operation The power supply enters Burst Mode at no-load or extremely light-load conditions. As shown in Figure 36, when VFB drops below VFBL; the PWM output shuts off and the output voltage drops at a rate dependent on load current. This causes the feedback voltage to rise. Once VFB exceeds VFBH, the internal circuit starts to provide switching pulse. The feedback voltage then falls and the process repeats. Burst Mode operation alternately enables and disables switching of the MOSFET, reducing the switching losses in Standby Mode. Once FAN302HLMY_F117 enters Burst Mode, the operating current is reduced from 3.5mA to 200μA to minimize power consumption. © 2012 Fairchild Semiconductor Corporation FAN302HLMY_F117 • Rev. 1.0.1 www.fairchildsemi.com 13 FAN302HLMY_F117 — mWSaver™ PWM Controller for Low Standby Power Battery-Charger Applications I HV = VS Over-Voltage Protection (OVP) VS over-voltage protection prevents damage due to output over-voltage conditions. Figure 39 shows the VS OVP protection method. When abnormal system conditions occur that cause VS to exceed 2.8V, after a period of debounce time; PWM pulses are disabled and FAN302HLMY_F117 enters Latch Mode until VDD drops under VDD-LH. By that time, PWM pulses revive. VS overvoltage conditions are usually caused by open circuit of the secondary-side feedback network or abnormal behavior by the VS pin divider resistor. Figure 37. Auto-Restart Mode Operation Figure 39. VS OVP Protection Leading-Edge Blanking (LEB) Each time the power MOSFET is switched on, a turn-on spike occurs at the sense resistor. To avoid premature termination of the switching pulse, a 150ns leading-edge blanking time is built in. Conventional RC filtering can therefore be omitted. During this blanking period, the current-limit comparator is disabled and it cannot switch off the gate driver. Noise Immunity Noise from the current sense or the control signal can cause significant pulse-width jitter. While slope compensation helps alleviate these problems, further precautions should still be taken. Good placement and layout practices should be followed. Avoid long PCB traces and component leads. Locate bypass filter components near the PWM IC. Figure 38. Latch-Mode Operation Over-Temperature Protection (OTP) The temperature-sensing circuit shuts down PWM output if the junction temperature exceeds 140°C (tOTP). © 2012 Fairchild Semiconductor Corporation FAN302HLMY_F117 • Rev. 1.0.1 www.fairchildsemi.com 14 FAN302HLMY_F117 — mWSaver™ PWM Controller for Low Standby Power Battery-Charger Applications VDD Over-Voltage Protection VDD over-voltage protection prevents IC damage from over-voltage exceeding the IC voltage rating. When the VDD voltage exceeds 26.5V due to an abnormal condition, the protection is triggered. This protection is typically caused by open circuit in the secondary-side feedback network. Application Fairchild Device Input Voltage Range Output Cell Phone Charger FAN302HLMY_F117 90~265VAC 5V/1.2A (6W) Features High Efficiency (>71% Avg.), Meets Energy Star V2.0 Standard (Avg. 68.17%) Ultra-Low Standby Power Consumption, <10mW at 230VAC (Pin=6.3mW for 115VAC and Pin=7.3mW for 230VAC) Output Regulation: CV= ±5%, CC= ±15% Figure 40. Measured Efficiency and Output Regulation C6 EI12.5 93T/7T/11T 1mH R1 10Ω + C1 L1 6.8µF AC Line 470pF C2 VDL - 0Ω R5 1N4148 FAN302HLMY_F117 R4 IN4935 1 CS FOD817S HV 8 2 GATE NC 7 3 VDD FB 6 R9 4 VS 91KΩ R6 0Ω 10nF 1.3Ω GND 5 1nF 40.2KΩ C7 R17 63.4KΩ C11 U1 R8 TL431 C10 33µF R11 5.6KΩ R18 64.9KΩ 100Ω C3 R7 R20 1KΩ 4A/650V Q1 D5 IO C9 330µF R3 D6 FFM107M 47Ω VO L3 C8 330µF D9 R2 10Ω NA NP 1.8µH N S 3A/40V 6.8µF D1~D4 FFM107M*4 10Ω D7 C4 R10 270KΩ 1nF R12 470pF C5 20pF Figure 41.Schematic of Typical Application Circuit © 2012 Fairchild Semiconductor Corporation FAN302HLMY_F117 • Rev. 1.0.1 www.fairchildsemi.com 15 FAN302HLMY_F117 — mWSaver™ PWM Controller for Low Standby Power Battery-Charger Applications Typical Application Circuit (Flyback Charger) Transformer Specification Core: EI12.5 Bobbin: EI12.5 2 1 Auxiliary Winding FLY– FLY+ Secondary Winding 5 Primary Winding 4 BOBBIN Figure 42.Transformer Notes: 7. W1 consists of four layers with different number of turns. The number of turns of each layer is specified in Table 1. Add one insulation tape between the second and third layers. 8. W2 consists of two layers with triple-insulated wire. The leads of positive and negative fly lines are 3.5cm and 2.5cm, respectively. 9. W3 is space winding in one layer. Table 1. NO. Transformer Winding Specifications Terminal Start Pin Wire End Pin Turns Insulation Turns 26 0 25 1 24 0 W1 4 5 2UEW 0.1*1 18 2 W2 Fly+ Fly- TEX-E 0.45*1 7 2 W3 1 2 2UEW 0.18*1 11 2 Core Rounding Tape 3 Core W4 2 0 2UEW 0.18*1 5 2 Note: 10. W4 is the outermost and space winding. Pin Specifications Primary-Side Inductance 4-5 700μH ±7% 100kHz, 1V Primary-Side Leakage Inductance 4-5 130μH ±7% Short One of the Secondary-Side Windings © 2012 Fairchild Semiconductor Corporation FAN302HLMY_F117 • Rev. 1.0.1 Remark www.fairchildsemi.com 16 FAN302HLMY_F117 — mWSaver™ PWM Controller for Low Standby Power Battery-Charger Applications Typical Application Circuit (Continued) 5.00 4.80 A 0.65 3.81 5 8 B 6.20 5.80 PIN ONE INDICATOR 1.75 4.00 3.80 1 5.60 4 1.27 (0.33) 0.25 M 1.27 C B A LAND PATTERN RECOMMENDATION 0.25 0.10 SEE DETAIL A 1.75 MAX 0.25 0.19 C 0.10 0.51 0.33 0.50 x 45° 0.25 R0.10 C OPTION A - BEVEL EDGE GAGE PLANE R0.10 OPTION B - NO BEVEL EDGE 0.36 NOTES: UNLESS OTHERWISE SPECIFIED 8° 0° 0.90 0.406 A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AA, ISSUE C, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS. D) LANDPATTERN STANDARD: SOIC127P600X175-8M. E) DRAWING FILENAME: M08AREV13 SEATING PLANE (1.04) DETAIL A SCALE: 2:1 Figure 43. 8-Lead, Small Outline Package (SOIC), JEDEC MS-012, .150-Inch, Narrow Body Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2012 Fairchild Semiconductor Corporation FAN302HLMY_F117 • Rev. 1.0.1 www.fairchildsemi.com 17 FAN302HLMY_F117 — mWSaver™ PWM Controller for Low Standby Power Battery-Charger Applications Physical Dimensions FAN302HLMY_F117 — mWSaver™ PWM Controller for Low Standby Power Battery-Charger Applications © 2012 Fairchild Semiconductor Corporation FAN302HLMY_F117 • Rev. 1.0.1 www.fairchildsemi.com 18