STMICROELECTRONICS M69AW024BL60ZB8T

M69AW024B
16 Mbit (1M x16) 3V Asynchronous PSRAM
FEATURES SUMMARY
■
■
■
■
■
■
SUPPLY VOLTAGE: 2.7 to 3.3V
ACCESS TIME: 60ns, 70ns
LOW STANDBY CURRENT: 70µA
DEEP POWER DOWN CURRENT: 10µA
LOW VCC DATA RETENTION: 2.3V
COMPATIBLE WITH STANDARD LPSRAM
Figure 1. Package
BGA
TFBGA48 (ZB)
6x8 mm
September 2004
1/29
M69AW024B
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. TFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Address Inputs (A0-A19). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Inputs/Outputs (DQ8-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chip Enable (E1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chip Enable (E2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Upper Byte Enable (UB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lower Byte Enable (LB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VCC Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VSS Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
......
......
......
......
......
......
......
......
......
......
......
......
......
.....6
.....6
.....6
.....6
.....6
.....6
.....6
.....6
.....6
.....6
.....6
.....7
.....8
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power On Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Deep Power-down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 3. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 4.
Figure 5.
Figure 6.
Table 5.
Table 6.
Table 7.
Figure 7.
Figure 8.
Figure 9.
2/29
Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Read and Standby Modes AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Output Enable Controlled, Read Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . 15
Chip Enable Controlled, Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Address Access After G Control, Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . 16
M69AW024B
Figure 10.Address Access After E1 Control, Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . 16
Table 8. Write Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 11.E1 Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 12.W Controlled, Single Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 13.W Controlled, Continuous Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 14.E1 Controlled, Read/Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 15.E1 Controlled, Read/Write AC Waveforms 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 16.G Controlled Read, W Controlled Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 17.G Controlled Read, W Controlled Write AC Waveforms 2 . . . . . . . . . . . . . . . . . . . . . . . 22
Table 9. Power Down and Power-Up AC Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 18.Standby Mode Entry AC Waveforms, After Read or Write . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 19.Power-down AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 20.Power-up Mode AC Waveforms - 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 21.Power-up Mode AC Waveforms - 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 22.Power-up Mode AC Waveforms - 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 10. Low VCC Data Retention Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 23.Low VCC Data Retention AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 24.TFBGA48 6x8mm - 6x8 Ball Array, 0.75mm Pitch, Package Outline, Bottom View . . . . 26
Table 11. TFBGA48 6x8mm - 6x8 Ball Array, 0.75mm Pitch, Package Mechanical Data. . . . . . . . 26
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 12. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 13. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3/29
M69AW024B
SUMMARY DESCRIPTION
The M69AW024B is a 16 Mbit (16,777,216 bit)
CMOS memory, organized as 1,048,576 words by
16 bits, and is supplied by a single 2.7V to 3.3V
supply voltage range.
M69AW024B is a member of STMicroelectronics
PSRAM memory family, based on the one-transistor per-cell architecture. These devices are manufactured using dynamic random access memory
cells, to minimize the cell size, and maximize the
amount of memory that can be implemented in a
given area.
However, through the use of internal control logic,
the device is fully static in its operation, requiring
no external clocks or timing strobes, and has a
standard Asynchronous SRAM Interface.
The internal control logic of the M69AW024B handles the periodic refresh cycle, automatically, and
without user involvement.
Write cycles can be performed on a single byte by
using Upper Byte Enable (UB) and Lower Byte Enable (LB).
The device can be put into standby mode using
Chip Enable (E1) or in deep power down mode by
using Chip Enable (E2).
Power-Down mode achieves a very low current
consumption by halting all the internal activities.
Since the refresh circuitry is halted, the duration of
the power-down should be less than the maximum
period for refresh, if the user has not finished with
the data contents of the memory.
Figure 2. Logic Diagram
Table 1. Signal Names
A0-A19
Address Input
DQ0-DQ15
Data Input/Output
E1, E2
Chip Enable, Power Down
G
Output Enable
W
Write Enable
W
UB
Upper Byte Enable
E1
LB
Lower Byte Enable
VCC
Supply Voltage
VSS
Ground
NC
Not Connected
(no internal connection)
VCC
20
16
A0-A19
E2
DQ0-DQ15
M69AW024B
G
UB
LB
VSS
4/29
AI07406
M69AW024B
Figure 3. TFBGA Connections (Top view through package)
1
2
3
4
5
6
A
LB
G
A0
A1
A2
E2
B
DQ8
UB
A3
A4
E1
DQ0
C
DQ9
DQ10
A5
A6
DQ1
DQ2
D
VSS
DQ11
A17
A7
DQ3
VCC
E
VCC
DQ12
NC
A16
DQ4
VSS
F
DQ14
DQ13
A14
A15
DQ5
DQ6
G
DQ15
A19
A12
A13
W
DQ7
H
A18
A8
A9
A10
A11
NC
AI07409
5/29
M69AW024B
SIGNAL DESCRIPTIONS
See Figure 2., Logic Diagram, and Table
1., Signal Names, for a brief overview of the signals connected to this device.
Address Inputs (A0-A19). The Address Inputs
select the cells in the memory array to access during Read and Write operations.
Data Inputs/Outputs (DQ8-DQ15). The Upper
Byte Data Inputs/Outputs carry the data to or from
the upper part of the selected address during a
Write or Read operation, when Upper Byte Enable
(UB) is driven Low.
Data Inputs/Outputs (DQ0-DQ7). The
Lower
Byte Data Inputs/Outputs carry the data to or from
the lower part of the selected address during a
Write or Read operation, when Lower Byte Enable
(LB) is driven Low.
Chip Enable (E1). When asserted (Low), the
Chip Enable, E1, activates the memory state machine, address buffers and decoders, allowing
Read and Write operations to be performed. When
de-asserted (High), all other pins are ignored, and
the device is put, automatically, in low-power
Standby mode.
6/29
Chip Enable (E2). The Chip Enable, E2, puts the
device in Deep Power-down mode when it
is driven Low. This is the lowest power mode.
Output Enable (G). The Output Enable, G, provides a high speed tri-state control, allowing fast
read/write cycles to be achieved with the common
I/O data bus.
Write Enable (W). The Write Enable, W, controls
the Bus Write operation of the memory.
Upper Byte Enable (UB). The Upper Byte Enable, UB, gates the data on the Upper Byte Data
Inputs/Outputs (DQ8-DQ15) to or from the upper
part of the selected address during a Write or
Read operation.
Lower Byte Enable (LB). The Lower Byte Enable, LB, gates the data on the Lower Byte Data
Inputs/Outputs (DQ0-DQ7) to or from the lower
part of the selected address during a Write or
Read operation.
VCC Supply Voltage. The VCC Supply Voltage
supplies the power for all operations (Read or
Write) and for driving the refresh logic, even when
the device is not being accessed.
VSS Ground. The VSS Ground is the reference for
all voltage measurements.
M69AW024B
Figure 4. Block Diagram
ARBITRATION
LOGIC
INTERNAL
CLOCK
GENERATOR
E2
W
VCC
DYNAMIC
MEMORY
ARRAY
INPUT/OUTPUT
BUFFER
E1
G
ROW DECODER
ADDRESS
REFRESH
CONTROLLER
CONTROL
LOGIC
DQ0-DQ7
DQ8-DQ15
COLUMN
DECODER
LB
UB
VCC
VSS
POWER
CONTROLLER
ADDRESS
AI07410
7/29
M69AW024B
Table 2. Operating Modes
Operation
E2
E1
W
G
LB
UB
A0-A19
DQ0-DQ7
DQ8DQ15
ICC
Data Retention
Standby (Deselect)
VIH
VIH
X (1)
X (1)
X (1)
X (1)
X (1)
Hi-Z
Hi-Z
ISB
Yes
Output Disabled (2)
VIH
VIL
VIH
VIH
X (1)
X (1)
Note (4)
Hi-Z
Hi-Z
ICC
Yes
Output Disabled
(No Read)
VIH
VIL
VIH
VIL
VIH
VIH
Valid
Hi-Z
Hi-Z
ICC
Yes
Word Read(5)
VIH
VIL
VIH
VIL
Word Read
VIH
VIL
VIH
VIL
VIL
Upper Byte Write
VIH
VIL
VIL
VIH
Lower Byte Write
VIH
VIL
VIL
Word Write
VIH
VIL
Power-down (3)
VIL
X (1)
Note: 1.
2.
3.
4.
5.
6.
8/29
Valid
Output Valid
ICC
Yes
VIL
Valid
Output Valid
ICC
Yes
VIH
VIL
Valid
Invalid
Input Valid
ICC
Yes
VIH
VIL
VIH
Valid
Input Valid
Invalid
ICC
Yes
VIL
VIH
VIL
VIL
Valid
Input Valid
Input Valid
ICC
Yes
X (1)
X (1)
X (1)
X (1)
X (1)
Hi-Z
Hi-Z
IPD
No
VIL(6)
X = VIH or VIL.
Output Disable mode should not be kept longer than 1µs.
Power-down mode can be entered from Stand-by state, and all DQ pins are in Hi-Z state.
Can be either VIL or VIH but must be valid before Read or Write.
Byte Read is not supported.
Either or both LB and UB must be Low, VIL, for Read operations.
M69AW024B
OPERATION
Operational modes are determined by device control inputs W, E1, E2, LB and UB as summarized
in the Operating Modes table (see Table 2.).
Power On Sequence
Because the internal control logic of the
M69AW024B needs to be initialized, the following
power-on procedure must be followed before the
memory is used:
– Apply power and wait for VCC to stabilize
– Wait 400µs while driving both Chip Enable
signals (E1 and E2) High
– Activate the memory by driving Chip
Enable (E1) Low.
Read Mode
The device is in Read mode when:
– Write Enable (W) is High and
– Output Enable (G) Low and
– the two Chip Enable signals are asserted
(E1 is Low, and E2 is High).
The time taken to enter Read mode (tELQV, tGLQV
or tBLQV) depends on which of the above signals
was the last to reach the appropriate level.
Data out (DQ15-DQ0) may be indeterminate
during tELQX, tGLQX and tBLQX, but data will always
be valid during tAVQV.
Write Mode
The device is in Write mode when
– Write Enable (W) is Low and
– Chip Enable (E1) is Low and
–
the two Chip Enable signals are asserted
(E1 is Low, and E2 is High)
– one of Upper Byte Enable (UB) or Lower
Byte Enable (LB) is Low, while the other is
High.
The Write cycle begins just after the event (the falling edge) that causes the last of these conditions
to become true (tAVWL or tAVEL or tAVBL).
The Write cycle is terminated by the earlier of a rising edge on Write Enable (W) or Chip Enable (E1).
If the device is in Write mode (Chip Enable (E1) is
Low, Output Enable (G) is Low, Upper Byte Enable (UB) or Lower Byte Enable (LB) is Low), then
Write Enable (W) will return the outputs to high impedance within tWLQZ of its falling edge. Care must
be taken to avoid bus contention in this type of operation. Data input must be valid for tDVWH before
the rising edge of Write Enable (W), or for tDVEH
before the rising edge of Chip Enable (E1), whichever occurs first, and remain valid for tWHDX, tEHDX
Standby Mode
The device is in Standby mode when:
– Chip Enable (E1) is High and
– Chip Enable (E2) is High.
The input/output buffers and the decoding/control
logic are switched off, but the dynamic array continues to be refreshed. In this mode, the memory
current consumption, ISB, is reduced, and the data
remains valid.
Deep Power-down Mode
The device is in Deep Power-down mode when:
– Chip Enable (E2 is Low).
9/29
M69AW024B
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings table may cause permanent damage to the device. Exposure to Absolute Maximum Rating conditions for extended
periods may affect device reliability. These are
stress ratings only and operation of the device at
these or any other conditions above those indicated in the Operating sections of this specification is
not implied.
Table 3. Absolute Maximum Ratings
Symbol
10/29
Parameter
Min
Max
Unit
IO
Output Current
–50
50
mA
TA
Ambient Operating Temperature
–30
85
°C
TSTG
Storage Temperature
–55
125
°C
VCC
Core Supply Voltage
–0.5
3.6
V
VIO
Input or Output Voltage
–0.5
3.6
V
M69AW024B
DC AND AC PARAMETERS
This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and
AC characteristics Tables that follow, are derived
from tests performed under the Measurement
Conditions summarized in Table 4., Operating and
AC Measurement Conditions. Designers should
check that the operating conditions in their circuit
match the operating conditions when relying on
the quoted parameters.
Table 4. Operating and AC Measurement Conditions
M69AW024B
Parameter
–60, –70
Unit
Min
Max
VCC Supply Voltage1
2.7
3.3
V
Ambient Operating Temperature
–30
85
°C
Load Capacitance (CL)
50
pF
Output Circuit Protection Resistance (R1)
50
Ω
Input Rise and Fall Times
4
ns
0 to VCC
V
Input and Output Timing Ref. Voltages
VCC/2
V
Output Transition Timing Ref. Voltages
VRL = 0.3VCC; VRH = 0.7VCC
V
Input Pulse Voltages
Input Transition Time2 (tτ ) between VIL and VIH
5
ns
Note: 1. All voltages are referenced to VSS.
2. The Input Transition Time used in AC measurements is 5ns. For other input transition times, see Table 9.
Figure 5. AC Measurement Load Circuit
Figure 6. AC Measurement I/O Waveform
VCC/2
I/O Timing Reference Voltage
R1
VCC
DEVICE
UNDER
TEST
VCC/2
OUT
0V
CL
Output Timing Reference Voltage
VCC
0V
0.7VCC
0.3VCC
AI07753
CL includes JIG capacitance
AI07222c
11/29
M69AW024B
Table 5. Capacitance
Symbol
CIN
Test
Condition
Parameter
Max
Unit
VIN = 0V
5
pF
VOUT = 0V
8
pF
Input Capacitance on all pins (except DQ)
COUT (1)
Output Capacitance
Min
Note: 1. Outputs deselected.
Table 6. DC Characteristics
Symbol
ICC1
(1)
Parameter
Operating Supply
Current
ILI
Input Leakage
Current
ILO
IPD
ISB
Max
Unit
tRC/tWC =
Min
20
mA
tRC/tWC =
1µs
3.0
mA
–1
1
µA
Output Leakage
Current
0V ≤VOUT ≤VCC
–1
1
µA
Deep Power Down
Current
VCC = 3.3V,
VIN = VIH or VIL,
E2 ≤0.2V
10
µA
3.1V ≤VCC ≤3.3V,
VIN = VIH or VIL,
E1 = VIH and E2 = VIH, IOUT = 0mA
1.5
mA
2.7V ≤VCC ≤3.1V,
VIN = VIH or VIL,
E1 = VIH and E2 = VIH, IOUT = 0mA
1
mA
3.1V ≤VCC ≤3.3V,
VIN ≤0.2V or ≥ VCC –0.2V,
E1 ≥ VCC –0.2V and
E2 ≥ VCC –0.2V), IOUT = 0mA
100
µA
2.7V ≤VCC ≤3.1V,
VIN ≤0.2V or ≥ VCC –0.2V,
E1 ≥ VCC –0.2V and
E2 ≥ VCC –0.2V), IOUT = 0mA
70
µA
Standby Supply
Current CMOS
Input High Voltage
VIL (3)
Input Low Voltage
VOL
VCC = 3.3V,
VIN = VIH or VIL,
E1 = VIL, E2 = VIH, IOUT = 0mA
Min
0V ≤VIN ≤VCC
VIH (2)
VOH
Test Condition
Output High Voltage
Output Low Voltage
3.1V ≤VCC ≤3.3V
2.6
VCC + 0.3
V
2.7V ≤VCC ≤3.1V
2.2
VCC + 0.3
V
3.1V ≤VCC ≤3.3V
–0.3
0.6
V
2.7V ≤VCC ≤3.1V
–0.3
0.5
V
3.1V ≤VCC ≤3.3V, IOH = –0.5mA
2.5
V
2.7V ≤VCC ≤3.1V, IOH = –0.5mA
2.2
V
VCC = 3V, IOL = 1mA
Note: 1. Average AC current, Outputs open, cycling at tAVAX (min).
2. Maximum DC voltage on input and I/O pins is VCC + 0.3V.
During voltage transitions, input may positive overshoot to VCC + 1.0V for a period of up to 5ns.
3. Minimum DC voltage on input or I/O pins is –0.3V.
During voltage transitions, input may positive overshoot to VSS + 1.0V for a period of up to 5ns.
12/29
0.4
V
M69AW024B
Table 7. Read and Standby Modes AC Characteristics
M69AW024B
Symbol
Alt.
Parameter
–60
Min
–70
Max
Min
Unit
Max
tAVAX
tRC
Read Cycle Time
80
90
ns
tAVEH
tRC
Address Valid to Chip Enable High (Read Cycle
Time)
80
90
ns
tAVEL(5)
tASC
Address Set-up Time to Chip Enable Low
–5
–5
ns
tAVGH
tRC
Address Valid to Output Enable High (Read Cycle
Time)
80
90
ns
tAVGL1(3,6)
tASO
Address Valid to Output Enable Low
25
30
ns
5
5
ns
tAVGL2(7)
tASO(ABS) Address Valid to Output Enable Low (absolute)
tAVQV(1,4)
tAA
Address Access Time
60
70
ns
tAXAV(4,8)
tAX
Address Invalid Time
5
5
ns
tAXQX(1)
tOH
Output Hold Time after Address Transition
5
5
ns
tBLEL(5)
tBSC
LB, UB Set-up Time to Chip Enable Low
–5
–5
ns
tBLGL
tBSO
LB, UB Set-up Time to Output Enable Low
0
0
ns
tEHAX
tCHAH
Chip Enable High to Address Hold Time
–5
–5
ns
tEHBH
tCHBH
Chip Enable High to LB, UB High
–5
–5
ns
tEHEL
tCP
Chip Enable High Pulse Width
10
12
ns
tEHQX(1)
tOH
Output Hold Time after Chip Enable Low
5
5
ns
tEHQZ(2)
tCHZ
Chip Enable High to Output Hi-Z
tELAX(4)
tCLAH
Chip Enable Low to Address Hold Time
80
90
ns
tELEH
tRC
Chip Enable Low to Chip Enable High (Read Cycle
Time)
80
90
ns
tELGH
tRC
Chip Enable Low to Output Enable High (Read
Cycle Time)
80
90
ns
tELGL(3,6,9,10)
tCLOL
Chip Enable Low to Output Enable Low Delay Time
25
tELQV(1,3)
tCE
Chip Enable Access Time
tELQX(2)
tCLZ
Chip Enable Low to Output Lo-Z
5
5
ns
tGHAX
tOHAH
Output Enable High to Address Hold Time
–5
–5
ns
tGHBH
tOHBH
Output Enable High to LB, UB High
–5
–5
ns
tGHGL1(6,9,10)
tOP
Output Enable High Pulse Width
25
tGHGL2(7)
tOP(ABS)
Output Enable High Pulse Width (absolute)
10
10
ns
tGHQX(1)
tOH
Output Hold Time after Output Enable Low
5
5
ns
tGHQZ(2)
tOHZ
Output Enable High to Output Hi-Z
tGLAX(4,9)
tOLAH
Output Enable Low to Address Hold Time
45
50
ns
tGLEH(9)
tOLCH
Output Enable Low to Chip Enable High Delay Time
45
50
ns
20
1000
25
30
60
1000
30
20
ns
1000
ns
70
ns
1000
25
ns
ns
13/29
M69AW024B
M69AW024B
Symbol
Alt.
Parameter
–60
Min
tGLQV(1)
tOE
Output Enable Access Time
tGLQX(2)
tOLZ
Output Enable Low to Output Lo-Z
–70
Max
Min
35
0
Unit
Max
40
0
ns
ns
Note: 1. CL = 50pF with 1 TTL and R1=50Ω.
2. CL = 5pF
3. tELQV is applicable if G is brought to Low before E1 goes Low and if actual value of either tAVGL1 or tELGL, or both, is shorter than
the specified value.
4. Only applicable to A0, A1 and A2 when both and G and E1 are kept Low for Address access.
5. Applicable if G is brought to Low before E1 goes Low.
6. tAVGL1, tELGL(Min) and tGHGL1(Min) are reference values when the access time is determined by tGLQV. If the actual value of each
parameter is lower than the specified minimum values, tGLQV is increased by the difference between the actual value and the specified minimum value.
7. tAVGL2 and tGHGL2 correspond to absolute minimum values during G controlled access.
8. tAXAV is applicable when two or more addresses from A0 to A2 are switched from the previous state.
9. If the actual value of tELGL or tGHGL1 is lower than the specified minimum value, tGLAX and tGLEH will be equal to tAVAX(Min) −
tELGL (Actual) and tAVAX (Min) −tGHGL1 (Actual), respectively.
10. The maximum value is applicable if E1 is kept Low.
14/29
M69AW024B
Figure 7. Output Enable Controlled, Read Mode AC Waveforms
A0-A19
ADDRESS VALID
ADDRESS VALID
tGHAX
tELGH
tGHAX
tAVGH
tAVGL2
tELQV
E1
tGLQV
tELGL
tAVGL1
tGLEH
tGLQV
tGHGL1
G
tBLGL
tGHBH
tBLGL
tGHBH
LB, UB
tGHQZ
tGLQX
DQ0-DQ15
tGHQZ
tGHQX
tGLQX tGHQX
VALID
VALID
AI07743
Note: 1. E2 = High and W = High.
2. Either or both LB and UB must be Low when both E1 and G are Low.
Figure 8. Chip Enable Controlled, Read Mode AC Waveforms
A0-A19
ADDRESS VALID
tELEH
tELEH
tAVEL
ADDRESS VALID
tEHAX
tELQV
tAVEL
tEHAX
tELQV
E1
tEHEL
G
tBLEL
tEHBH
tBLEL
tEHBH
LB, UB
tEHQZ
tELQX
DQ0-DQ15
tEHQX
VALID
tEHQZ
tELQX
tEHQX
VALID
AI07744
Note: 1. E2 = High and W = High.
2. Either or both LB and UB must be Low when both E1 and G are Low.
15/29
M69AW024B
Figure 9. Address Access After G Control, Read Mode AC Waveforms
A3-A19
ADDRESS VALID
ADDRESS VALID (no change)
A0-A2
ADDRESS VALID
ADDRESS VALID
tAVAX
tAVGL1
tAVGH
tGLAX
tGHAX
tAXAV
tAVQV
tGHQZ
E1
tGLQV
G
tBLGL
tGHBH
LB, UB
tGLQX
tGHQX
tAXQX
DQ0-DQ15
DATA VALID
DATA VALID
AI07745
Note: 1. E2 = High and W = High.
2. Either or both LB and UB must be Low when both E1 and G are Low.
Figure 10. Address Access After E1 Control, Read Mode AC Waveforms
A3-A19
A0-A2
ADDRESS VALID
ADDRESS VALID
tAVEH
tAVEL
tELAX
tAXAV
tEHAX
tAVQV
E1
tELQV
tEHQZ
G
tBLEL
tEHBH
LB, UB
tELQX
DQ0-DQ15
tAXQX
DATA VALID
tEHQX
DATA VALID
AI07746
Note: 1. E2 = High and W = High.
2. Either or both LB and UB must be Low when both E1 and G are Low.
16/29
M69AW024B
Table 8. Write Mode AC Characteristics
M69AW024B
Symbol
Alt.
Parameter
–60
Min
Max
–70
Min
Unit
Max
tAVEL(2)
tAS
Address Set-up Time to Chip Enable Low
0
0
ns
tAVWL
tAS
Address Set-up Time to Write Enable Low
0
0
ns
Address Invalid to Output Enable Low
25
Address Invalid to Output Enable Low (absolute)
12
15
ns
tAXGL1
(3,4)
tOEH
1000
35
1000
ns
tAXGL2(5)
tOEH(ABS)
tBLEL
tBS
LB, UB Set-up Time to Chip Enable Low
–5
–5
ns
tBLWL
tBS
LB, UB Set-up Time to Write Enable Low
–5
–5
ns
tDVEH
tDS
Data Set-up Time to Chip Enable High
15
20
ns
tDVWH
tDS
Data Set-up Time to Write Enable High
15
20
ns
tEHBH
tBH
LB, UB Hold Time from Chip Enable High
–5
–5
ns
tEHDX
tDH
Input Data Hold Time from Chip Enable High
0
0
ns
tEHEL1(9,10)
tWRC
Chip Enable High Pulse Width to Chip Enable Low
20
20
ns
tEHEL2(10)
tCP
Chip Enable High Pulse Width to Chip Enable Low
10
12
ns
tEHWH
tWH
Write Enable Low Hold Time
0
0
ns
tEHWL
tWH
Write Enable High Hold Time
0
0
ns
tELAX(2)
tAH
Address Hold Time from Chip Enable Low
35
40
ns
tELEH1(1,8)
tCW
Chip Enable Write Pulse Width
45
50
ns
tELEH2(1,9,10)
tWRC
Chip Enable Write Recovery Time
20
20
ns
tELEL
tWC
Chip Enable Write Cycle Time
80
90
ns
tELWL
tCS
Chip Enable Write Set-up Time
0
tGHAX(7)
tOHAH
Address Hold Time from Output Enable High
–5
–5
ns
tGHBH
tBH
LB, UB Hold Time from Output Enable High
–5
–5
ns
tGHEL(6)
tOHCL
Output Enable High to Chip Enable Low Set-up
Time
–5
–5
ns
tGHWL(3)
tOES
Output Enable Set-up Time
0
1000
0
1000
ns
tWHAV(1,3,9,10)
tWR
Write Enable High to Address Valid
20
1000
20
1000
ns
tWHBH
tBH
LB, UB Hold Time from Write Enable High
–5
–5
ns
tWHDX
tDH
Input Data Hold Time from Write Enable High
0
0
ns
tWHEH
tCH
Chip Enable Write Hold Time
0
tWHEL
tWS
Write Enable High Set-up Time
0
tWHWL(1,3,9,10)
tWR
Write Enable Write Recovery Time to Write Enable
Low
20
tWLAV
tWC
Write Enable Low to Address Valid Write Cycle Time
80
90
ns
tWLAX(2)
tAH
Address Hold Time from Write Enable Low
35
40
ns
1000
1000
0
0
1000
1000
0
1000
20
ns
ns
ns
1000
ns
17/29
M69AW024B
M69AW024B
Symbol
Alt.
Parameter
–60
Min
Max
–70
Min
Unit
Max
tWLEL
tWS
Write Enable Low Set-up Time
0
0
ns
tWLWH(1,8)
tWP
Write Enable Write Pulse Width
45
50
ns
tWLWL
tWC
Write Enable Write Cycle Time
80
90
ns
Note: 1. The minimum value must be equal to or greater than the sum of actual tELEH (or tWLWH).
2. The new write address is valid from either E1 High or W High.
3. tAXGL1 is specified from end of tAVAX (Min) and is a reference value when access time is determined by tAXGL1. If actual value is
lower than specified minimum value, tAXGL1 is increased by the difference between the actual value and the specified minimum
value.
4. tAXGL1 maximum is applicable if E1 is kept Low and both W and G are kept High.
5. tAXGL2 is the absolute minimum value if the Write cycle terminates with W and E1 Low.
6. tGHEL (Min) must be kept if the Read cycle is not performed prior to the Write cycle. In case G is disabled after a time tGHEL(Min),
W must go Low tELEH2 (Min) after E1 goes Low. In other words, the Read cycle is initiated if tGHEL (Min) is not kept.
7. Applicable if E1 stays Low after the Read cycle.
8. tELEH or tWLWH is applicable if the Write operation is initiated by E1 or W, respectively.
9. If the write operation is terminated by W followed by E1 High, the sum of actual tELWL and tWLWH and the sum of actual tAVWL and
tWLWH must be equal or greater than 60ns.
10. tEHEL1 or tWHWL is applicable if the Write operation is terminated by E1 or W, respectively. If E1 goes High before tWHWL (Min), then
tEHEL1 (Min) must apply.
11. tEHEL1 and tEHEL2 is applicable if write operation is terminated by E1 and W, respectively. In case E1 is brought to High before satisfaction of tEHEL2 (min), the tEHEL1 (min) is also applied.
12. For other timings please refer to Table 7., Read and Standby Modes AC Characteristics.
18/29
M69AW024B
Figure 11. E1 Controlled, Write AC Waveforms
tELEL
A0-A19
ADDRESS VALID
ADDRESS VALID
tELAX
tAVEL
tAVEL
E1
tEHEL1
tELEH1
tWLEL
tEHWH
tWLEL
tEHBH
tBLEL
W
tBLEL
UB, LB
tGHEL
G
tDVEH
DQ0-DQ15
tEHDX
VALID DATA INPUT
AI07411C
Note: 1. E2 must be High during the Write cycle.
Figure 12. W Controlled, Single Write AC Waveforms
tWLWL
ADDRESS VALID
A0-A19
tGHAX
ADDRESS VALID
ADDRESS VALID
tAVWL
tAVWL
tWHEH
tWLAX
E1
tGHEL
tELWL
tEHEL2
tWLWH
tWHWL
W
tBLWL
tGHBH
tWHBH
UB, LB
tGHWL
G
tGHQZ
DQ0-DQ15
tDVWH
tWHDX
VALID DATA INPUT
AI07412C
Note: 1. E2 must be High during the Write cycle.
19/29
M69AW024B
Figure 13. W Controlled, Continuous Write AC Waveforms
tWLWL
ADDRESS VALID
A0-A19
ADDRESS VALID
tGHAX
ADDRESS VALID
tAVWL
tAVWL
tWLAX
E1
tGHEL
tELWL
tWLWH
tWHWL
W
tWHBH
tBLWL
tGHBH
tBLWL
UB, LB
tGHWL
G
tGHQZ
tDVWH
DQ0-DQ15
tWHDX
VALID DATA INPUT
AI07413C
Note: 1. E2 must be High during the Write cycle.
Figure 14. E1 Controlled, Read/Write AC Waveforms
tELEL
ADDRESS VALID
A0-A19
tEHAX
ADDRESS VALID
ADDRESS VALID
tAVEL
tAVEL
tELAX
E1
tEHEL1
tELEH1
tEHEL1
tWHEL
tEHWH
tEHWL
tWLEL
ELGL
W
tEHBH
tBLEL
tEHBH
tBLGL
UB, LB
tGHEL
G
tEHQZ
tEHQX
DQ0-DQ15
READ DATA OUTPUT
tGLQX
tDVEH
tEHDX
WRITE DATA INPUT
AI07414C
Note: 1. Write address is valid from the falling edge of either E1 or W, whichever occurs later.
20/29
M69AW024B
Figure 15. E1 Controlled, Read/Write AC Waveforms 2
tELEH
A0-A19
READ ADDRESS
tAVEL
WRITE ADDRESS
tEHAX
tAVEL
tEHEL1
E1
tEHEL1(min)
tEHWH
tELQV
tEHEL1
tWHEL
tEHWL
tWLEL
tEHBH
tBLEL
W
tEHBH
tBLEL
UB, LB
tGHEL
tELGL
G
tEHQZ
tEHDX
DQ0-DQ15
tEHQX
tELQX
WRITE DATA INPUT
READ DATA OUTPUT
AI07415C
Figure 16. G Controlled Read, W Controlled Write AC Waveforms
tWLAV
ADDRESS VALID
A0-A19
tGHAX
WRITE ADDRESS
READ ADDRESS
tAVWL
tAVGL1
tWLAX
E1
Low
tWLWH
tWHAV
W
tGHBH
tBLWL
tWHBH
tBLGL
UB, LB
tGHWL
G
tGHQZ
tGHQX
DQ0-DQ15
READ DATA OUTPUT
tDVWH
tWHDX
tGLQX
WRITE DATA INPUT
AI07416C
Note: 1. E1 can be tied to Low for W and G controlled operation. When E1 is tied to Low, output is exclusively controlled by G.
21/29
M69AW024B
Figure 17. G Controlled Read, W Controlled Write AC Waveforms 2
tAVGH
A0-A19
E1
READ ADDRESS
WRITE ADDRESS
tAVGL1
tGHAX
tAVWL
tBLGL
tGHBH
tBLWL
Low
tWHAV
W
tWHBH
UB, LB
tGHWL
G
tGLQV
tWHDX
DQ0-DQ15
WRITE DATA INPUT
tGLQX
tGHQZ
tGHQX
READ DATA OUTPUT
AI07417C
Note: 1. E1 can be tied to Low for W and G controlled operation. When E1 is tied to Low, output is exclusively controlled by G.
22/29
M69AW024B
Table 9. Power Down and Power-Up AC Parameters
M69AW024B
Symbol
Alt.
Parameter
–60
Min
–70
Max
Min
Unit
Max
tCLEL
tCSP
E2 Low Setup Time for Power Down Entry
10
10
ns
tELCH
tC2LP
E2 Low Hold Time after Power Down Entry
80
90
ns
tCHEL
tCHH
E1 High Hold Time following E2 High after PowerDown Exit (Sleep Mode only)
350
350
µs
tEHEL
tCHHP
E1 High Hold Time following E2 High after PowerDown Exit (not in Sleep Mode)
400
400
µs
tEHCH1
tCHS
E1 High Setup Time following E2 High after PowerDown Exit
10
10
ns
tEHCH2
tC2LH
Power-up Time 1
50
50
µs
tC2HL
Power-up Time 2
50
50
µs
tEHGH
tCHOX
E1 High to G Invalid Time for Standby Entry
10
10
ns
tEHWH
tCHWX
E1 High to W Invalid Time for Standby Entry
10
10
ns
tT
tT
Input Transition Time
1
tCHCL12
tCHCL22
25
1
25
ns
Note: 1. Some data may be written to any address location if tEHWH is less than the minimum required time.
2. The device has to enter and exit Power Down mode after tCHCL.
3. The Input Transition Time used in AC measurements is 5ns.
Figure 18. Standby Mode Entry AC Waveforms, After Read or Write
E1
E1
tEHWH
tEHGH
G
G
W
W
Active (Read)
Standby
Active (Write)
Standby
AI07741
Note: Both tEHGH and tEHWH define the earliest entry timing for Stand-by mode. If either of timing is not satisfied, it takes the tAVAX(min) period
from either the last address transition of A0, A1 and A2, or E1 rising edge.
23/29
M69AW024B
Figure 19. Power-down AC Waveforms
E1
tEHCH1
E2
tCHEL
tELCH
tCLEL
DQ
Hi-Z
Power Down
Entry
Power Down Exit
Power Down Mode
AI07739
Note: This Power Down mode can be also be used in “Power-up Mode AC Waveforms - 2”.
Figure 20. Power-up Mode AC Waveforms - 1
E1
tEHCH1
tEHCH2
tCHEL
E2
VCC
VCC min
0V
AI07740
Note: tVHCH starts from V CC reaching VCC(min).
Figure 21. Power-up Mode AC Waveforms - 2
E1
tEHCH1
tCHCL2
tCLEL
tELCH
tCHEL
E2
tCHCL1
VCC
VCC min
0V
AI07742
Note: tVHCL starts from VCC reaching VCC(min).
E1 must be taken High prior to, or together with, the rising edge on E2.
24/29
M69AW024B
Figure 22. Power-up Mode AC Waveforms - 3
E1
tEHEL
E2
VCC
VCC min
0V
AI08054C
Note: Both E1 and E2 must go High as VCC reaches VCC(min). If not, the timings provided in Power-Up Mode AC Waveforms 1 (Figure 20.)
or Power-Up Mode AC Waveforms 2 (Figure 21.) should be used to ensure proper operation.
Table 10. Low VCC Data Retention Characteristics
Symbol
Parameter
Test Condition1
Min
Max
Unit
2.3
3.5
V
70
µA
VDR (2)
Supply Voltage (Data Retention)
E1 = E2 ≥ VCC –0.2V, or
E1 = VIH and E2 = VIH
ICCDR
Supply Current (Data Retention)
VCC = VDR, VIN ≤0.2V or ≥ VCC –0.2V,
E1 = ≥ VCC –0.2V and E2 ≥ VCC –0.2V,
IOUT = 0mA
tCDR (2,3)
tR (3)
∆V/∆t (3)
Chip deselected to Data Retention
Time
VCC = 2.7V
0
ns
Operation Recovery Time
VCC = 2.7V
100
ns
0.2
V/µs
VCC Voltage Transition Time
Note: 1. TA = –30 to 85°C
2. All other Inputs at VIH ≥ VCC –0.2V or VIL ≤0.2V.
3. See Figure 23. for measurement points.
Figure 23. Low VCC Data Retention AC Waveforms
VCC
3.5V
2.7V
tCDR
DATA RETENTION MODE
∆V/∆t
tR
∆V/∆t
E2
2.3V
0.4V
E1
E1 and E2 ≥ VDD – 0.2V or VIH(min)
Data Bus must be Hi-Z
VSS
AI07408
25/29
M69AW024B
PACKAGE MECHANICAL
Figure 24. TFBGA48 6x8mm - 6x8 Ball Array, 0.75mm Pitch, Package Outline, Bottom View
D
D1
FD
FE
SD
SE
BALL "A1"
E
E1
ddd
e
e
b
A
A2
A1
BGA-Z26
Note: Drawing is not to scale.
Table 11. TFBGA48 6x8mm - 6x8 Ball Array, 0.75mm Pitch, Package Mechanical Data
millimeters
inches
Symbol
Typ
Min
A
Typ
Min
1.200
A1
0.0102
0.900
b
Max
0.0472
0.260
A2
0.350
0.450
0.0354
0.0138
0.0177
D
6.000
5.900
6.100
0.2362
0.2323
0.2402
D1
3.750
–
–
0.1476
–
–
ddd
26/29
Max
0.100
0.0039
E
8.000
7.900
8.100
0.3150
0.3110
0.3189
E1
5.250
–
–
0.2067
–
–
e
0.750
–
–
0.0295
–
–
FD
1.125
–
–
0.0443
–
–
FE
1.375
–
–
0.0541
–
–
SD
0.375
–
–
0.0148
–
–
SE
0.375
–
–
0.0148
–
–
M69AW024B
PART NUMBERING
Table 12. Ordering Information Scheme
Example:
M69AW024
B
L
70 ZB
8
T
Device Type
M69 = 1T/1C Memory Cell Architecture
Mode
A = Asynchronous
Operating Voltage
W = 2.7 to 3.3V
Array Organization
024 = 16 Mbit (1M x16)
Option 1
B = 2 Chip Enable; No Write and Standby from UB and LB
Option 2
L = Low Leakage
Speed Class
60 = 60ns
70 = 70ns
Package
ZB = TFBGA48 6x8mm - 6x8 ball array, 0.75mm pitch
Temperature Range
8 = –30 to 85°C
Shipping Method
T = Tape & Reel Packing
The notation used for the device number is as shown in Table 12. For a list of available options (speed,
package, etc.) or for further information on any aspect of this device, please contact your nearest STMicroelectronics Sales Office.
27/29
M69AW024B
REVISION HISTORY
Table 13. Document Revision History
Date
Rev.
01-Jun-2002
1.0
First Issue
04-Feb-2003
2.0
Document completely revised
14-Mar-2003
2.1
AC Testing Load Circuit revised; 60ns access time device added
29-Apr-2003
2.2
Timing parameter names changed in tables and illustrations
25-Jul-2003
2.3
Chip enable signals E1 and E2 must change together during Power-on sequence
07-May-2004
3.0
Datasheet title updated.
Table 2., Operating Modes updated for read operations.
29-Sep-2004
4.0
Minor modification in first paragraph of Summary Description.
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M69AW024B
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