VISHAY SIHFI9610G-E3

IRFI9610G, SiHFI9610G
Vishay Siliconix
Power MOSFET
FEATURES
PRODUCT SUMMARY
VDS (V)
• Isolated Package
• High Voltage Isolation = 2.5 kVRMS (t = 60 s;
f = 60 Hz)
• Sink to Lead Creepage Distance = 4.8 mm
• P-Channel
• Dynamic dV/dt Rating
• Low Thermal Resistance
• Lead (Pb)-free Available
- 200
RDS(on) (Ω)
VGS = - 10 V
3.0
Qg (Max.) (nC)
13
Qgs (nC)
3.2
Qgd (nC)
7.3
Configuration
Single
Available
RoHS*
COMPLIANT
S
TO-220 FULLPAK
DESCRIPTION
Third generation Power MOSFETs from Vishay provide the
designer with the best combination of fast switching,
ruggedized device design, low on-resistance and
cost-effectiveness.
The TO-220 FULLPAK eliminates the need for additional
insulating hardware in commercial-industrial applications.
The moulding compound used provides a high isolation
capability and a low thermal resistance between the tab and
external heatsink. This isolation is equivalent to using a 100
micron mica barrier with standard TO-220 product. The
FULLPAK is mounted to a heatsink using a single clip or by
a single screw fixing.
G
G D S
D
P-Channel MOSFET
ORDERING INFORMATION
Package
TO-220 FULLPAK
IRFI9640GPbF
SiHFI9640G-E3
IRFI9640G
SiHFI9640G
Lead (Pb)-free
SnPb
ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted
PARAMETER
Drain-Source Voltage
Gate-Source Voltage
SYMBOL
VDS
VGS
VGS at - 10 V
Continuous Drain Current
Pulsed Drain Currenta
Linear Derating Factor
Single Pulse Avalanche Energyb
Repetitive Avalanche Currenta
Repetitive Avalanche Energya
Maximum Power Dissipation
Peak Diode Recovery dV/dtc
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature)
Mounting Torque
TC = 25 °C
TC = 100 °C
ID
IDM
TC = 25 °C
EAS
IAR
EAR
PD
dV/dt
TJ, Tstg
for 10 s
6-32 or M3 screw
LIMIT
- 200
± 20
- 2.0
- 1.3
- 8.0
0.22
100
- 2.0
2.7
27
- 11
- 55 to + 150
300d
10
1.1
UNIT
V
A
W/°C
mJ
A
mJ
W
V/ns
°C
lbf · in
N·m
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Starting TJ = 25 °C, L = 51 mH, RG = 25 Ω, IAS = - 2.0 A (see fig. 12).
c. ISD ≤ - 2.0 A, dI/dt ≤ - 250 A/µs, VDD ≤ VDS, TJ ≤ 150 °C.
d. 1.6 mm from case.
* Pb containing terminations are not RoHS compliant, exemptions may apply
Document Number: 91165
S-Pending-Rev. A, 16-Jun-08
WORK-IN-PROGRESS
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IRFI9610G, SiHFI9610G
Vishay Siliconix
THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
TYP.
MAX.
Maximum Junction-to-Ambient
RthJA
-
65
Maximum Junction-to-Case (Drain)
RthJC
-
4.6
UNIT
°C/W
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
VDS
VGS = 0 V, ID = - 250 µA
- 200
-
-
V
ΔVDS/TJ
Reference to 25 °C, ID = - 1 mA
-
- 0.22
-
V/°C
VGS(th)
VDS = VGS, ID = - 250 µA
- 2.0
-
- 4.0
V
nA
Static
Drain-Source Breakdown Voltage
VDS Temperature Coefficient
Gate-Source Threshold Voltage
Gate-Source Leakage
Zero Gate Voltage Drain Current
Drain-Source On-State Resistance
Forward Transconductance
IGSS
IDSS
RDS(on)
gfs
VGS = ± 20 V
-
-
± 100
VDS = - 200 V, VGS = 0 V
-
-
- 100
VDS = - 160 V, VGS = 0 V, TJ = 125 °C
-
-
- 500
-
-
3.0
Ω
0.7
-
-
S
-
180
-
-
66
-
-
12
-
ID = - 1.2 Ab
VGS = - 10 V
VDS = - 50 V, ID = - 1.2
Ab
µA
Dynamic
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
Total Gate Charge
Qg
Gate-Source Charge
Qgs
VGS = 0 V,
VDS = - 25 V,
f = 1.0 MHz, see fig. 5
VGS = - 10 V
ID = - 2.0 A, VDS = - 160 V,
see fig. 6 and 13b
-
-
13
-
-
3.2
pF
nC
Gate-Drain Charge
Qgd
-
-
7.3
Turn-On Delay Time
td(on)
-
12
-
-
17
-
-
19
-
-
15
-
-
4.5
-
-
7.5
-
-
-
- 2.0
-
-
- 8.0
-
-
- 5.8
V
-
130
200
ns
-
700
1050
µC
Rise Time
Turn-Off Delay Time
Fall Time
tr
td(off)
VDD = - 100 V, ID = - 2.0 A,
RG = 24 Ω, VGS = - 10 V,
see fig. 10b
tf
Internal Drain Inductance
LD
Internal Source Inductance
LS
Between lead,
6 mm (0.25") from
package and center of
die contact
D
ns
nH
G
S
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
Pulsed Diode Forward Currenta
Body Diode Voltage
IS
ISM
VSD
Body Diode Reverse Recovery Time
trr
Body Diode Reverse Recovery Charge
Qrr
Forward Turn-On Time
ton
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
A
G
TJ = 25 °C, IS = - 2.0 A, VGS = 0
S
Vb
TJ = 25 °C, IF = - 2.0 A, dI/dt = 100 A/µsb
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width ≤ 300 µs; duty cycle ≤ 2 %.
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Document Number: 91165
S-Pending-Rev. A, 16-Jun-08
IRFI9610G, SiHFI9610G
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
10
10
VGS
-15V
-10V
-8.0V
-7.0V
-6.0V
-5.5V
-5.0V
BOTTOM -4.5V
1
TJ = 25°C
-I D, Drain-to-Source Current (Α )
-I D, Drain-to-Source Current (A)
TOP
-4.5V
0.1
T J = 150°C
1
0.01
0
0.1
1
10
100
4.0
-VDS, Drain-to-Source Voltage (V)
Fig. 1 - Typical Output Characteristics, TC = 25 °C
0.1
20µs PULSE WIDTH
Tj = 150°C
0.01
1
10
100
-VDS, Drain-to-Source Voltage (V)
Fig. 2 - Typical Output Characteristics, TC = 150 °C
Document Number: 91165
S-Pending-Rev. A, 16-Jun-08
7.0
8.0
9.0
10.0
11.0
ID = -2.0A
VGS = -10V
2.0
(Normalized)
-I D, Drain-to-Source Current (A)
-4.5V
0.1
6.0
2.5
VGS
-15V
-10V
-8.0V
-7.0V
-6.0V
-5.5V
-5.0V
BOTTOM -4.5V
TOP
1
5.0
-VGS , Gate-to-Source Voltage (V)
Fig. 3 - Typical Transfer Characteristics
RDS(on) , Drain-to-Source On Resistance
10
VDS = -50V
20µs PULSE WIDTH
20µs PULSE WIDTH
Tj = 25°C
1.5
1.0
0.5
-60 -40 -20
0
20
40
60
80 100 120 140 160
T J , Junction Temperature (°C)
Fig. 4 - Normalized On-Resistance vs. Temperature
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IRFI9610G, SiHFI9610G
Vishay Siliconix
10.0
350
VGS = 0V,
f = 1 MHZ
Ciss = C gs + Cgd, C ds
Crss = Cgd
300
Coss = Cds + Cgd
SHORTED
-I SD, Reverse Drain Current (A)
C, Capacitance (pF)
400
250
Ciss
200
150
Coss
100
50
T J = 150°C
1.0
TJ = 25°C
Crss
VGS = 0V
0.1
0
1
10
0.0
100
1.0
3.0
4.0
5.0
-VSD, Source-toDrain Voltage (V)
-VDS, Drain-to-Source Voltage (V)
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
Fig. 7 - Typical Source-Drain Diode Forward Voltage
100
20
OPERATION IN THIS AREA
LIMITED BY R DS(on)
ID= -2.0A
VDS= -160V
VDS= -100V
VDS= -40V
16
-I D, Drain-to-Source Current (A)
-V GS, Gate-to-Source Voltage (V)
2.0
12
8
4
10
100µsec
1
1msec
FOR TEST CIRCUIT
SEE FIGURE 13
0
0.1
0
2
4
6
8
10
12
14
Q G Total Gate Charge (nC)
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
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Tc = 25°C
Tj = 150°C
Single Pulse
10
10msec
100
1000
-VDS , Drain-toSource Voltage (V)
Fig. 8 - Maximum Safe Operating Area
Document Number: 91165
S-Pending-Rev. A, 16-Jun-08
IRFI9610G, SiHFI9610G
Vishay Siliconix
RD
VDS
2.0
VGS
-ID , Drain Current (A)
D.U.T.
RG
1.6
+
- VDD
10 V
1.2
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
0.8
Fig. 10a - Switching Time Test Circuit
0.4
90 %
VDS
0.0
25
50
75
100
125
150
10 %
VGS
T J , Junction Temperature (°C)
td(on)
Fig. 9 - Maximum Drain Current vs. Case Temperature
td(off) tf
tr
Fig. 10b - Switching Time Waveforms
Thermal Response ( Z thJC )
10
D = 0.50
0.20
1
0.10
0.05
0.02
0.1
0.01
SINGLE PULSE
( THERMAL RESPONSE )
0.01
1E-006
1E-005
0.0001
0.001
0.01
0.1
1
t1 , Rectangular Pulse Duration (sec)
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
L
VDS
IAS
+ VDD
A
D.U.T.
RG
IAS
- 20 V
tp
Driver
0.01 Ω
tp
15 V
Fig. 12a - Unclamped Inductive Test Circuit
Document Number: 91165
S-Pending-Rev. A, 16-Jun-08
VDS
Fig. 12b - Unclamped Inductive Waveforms
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IRFI9610G, SiHFI9610G
Vishay Siliconix
EAS, Single Pulse Avalanche Energy (mJ)
240
ID
-0.9A
-1.3A
BOTTOM -2.0A
TOP
200
160
120
80
40
0
25
50
75
100
125
150
Starting T J , Junction Temperature (°C)
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
Current regulator
Same type as D.U.T.
50 kΩ
QG
- 10 V
12 V
0.2 µF
0.3 µF
QGS
-
QGD
D.U.T.
VG
+ VDS
VGS
- 3 mA
Charge
IG
ID
Current sampling resistors
Fig. 13a - Basic Gate Charge Waveform
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Fig. 13b - Gate Charge Test Circuit
Document Number: 91165
S-Pending-Rev. A, 16-Jun-08
IRFI9610G, SiHFI9610G
Vishay Siliconix
Peak Diode Recovery dV/dt Test Circuit
D.U.T.
+
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
-
-
RG
+
• dV/dt controlled by RG
• ISD controlled by duty factor "D"
• D.U.T. - device under test
+
- VDD
Compliment N-Channel of D.U.T. for driver
Driver gate drive
P.W.
Period
D=
P.W.
Period
VGS = - 10 V*
D.U.T. ISD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
VDD
Body diode forward drop
Inductor current
Ripple ≤ 5 %
*
ISD
VGS = - 5 V for logic level and - 3 V drive devices
Fig. 14 - For P-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see http://www.vishay.com/ppg?91165.
Document Number: 91165
S-Pending-Rev. A, 16-Jun-08
www.vishay.com
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Legal Disclaimer Notice
Vishay
Disclaimer
All product specifications and data are subject to change without notice.
Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf
(collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein
or in any other disclosure relating to any product.
Vishay disclaims any and all liability arising out of the use or application of any product described herein or of any
information provided herein to the maximum extent permitted by law. The product specifications do not expand or
otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed
therein, which apply to these products.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this
document or by any conduct of Vishay.
The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications unless
otherwise expressly indicated. Customers using or selling Vishay products not expressly indicated for use in such
applications do so entirely at their own risk and agree to fully indemnify Vishay for any damages arising or resulting
from such use or sale. Please contact authorized Vishay personnel to obtain written terms and conditions regarding
products designed for such applications.
Product names and markings noted herein may be trademarks of their respective owners.
Document Number: 91000
Revision: 18-Jul-08
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