STA550 70+70W STEREO ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ POWER AMPLIFIER MONOCHIP BRIDGE STEREO AMPLIFIER FOR BASH® ARCHITECTURE 55+55W OUTPUT POWER @ RL = 4/8 Ω, THD = 0.5% 70+70W OUTPUT POWER @ RL = 4/8 Ω, THD = 10% HIGH DYNAMIC PREAMPLIFIER INPUT STAGES EXTERNAL PROGRAMMABLE FEEDBACK TYPE COMPRESSORS AC COUPLED INPUT TO CLASS AB BRIDGE OUTPUT AMPLIFIER PRECISION RECTIFIERS TO DRIVE THE DIGITAL CONVERTER ON-OFF SEQUENCE/ TIMER WITH MUTE AND STANDBY PROPORTIONAL OVER POWER OUTPUT CURRENT TO LIMIT THE DIGITAL CONVERTER ABSOLUTE POWER BRIDGE OUTPUT FLEXIWATT27 ■ ■ ■ ■ ■ TRANSISTOR POWER PROTECTION ABSOLUTE OUTPUT CURRENT LIMIT INTEGRATED THERMAL PROTECTION POWER SUPPLY OVER VOLTAGE PROTECTION FLEXIWATT POWER PACKAGE WITH 27 PIN BASH® LICENCE REQUIRED DESCRIPTION The STA550 is a fully integrated power module designed to implement a BASH® amplifier when used in conjunction with STABP01 digital processor. BLOCK DIAGRAM +VS GND OUT_ PRE1 -VS TRK_1 PWR_INP1 CD+1 ABSOLUTE VALUE BLOCK + - +2 ∆G IN_PRE1 OUT1+ -1 OUT1- COMPRESSOR CD-1 OUTPUT BRIDGE V/l ATT_REL1 CD+ PEAK/2 DETECTOR S1 Ict VOLTAGE PROTECTION Ict THERMAL PROTECTION SOA DETECTOR PROT. TURNON/OFF SEQUENCE STBY/MUTE TRK_OUT THRESH PEAK/2 DETECTOR S1 ATT_REL2 V/l CD+2 +2 COMPRESSOR -1 - ABSOLUTE VALUE BLOCK + OUT_ PRE2 July 2003 OUT2+ ∆G IN_PRE2 TRK_2 OUT2- OUTPUT BRIDGE PWR_INP2 CD-2 D01AU1263 1/16 STA550 DESCRIPTION (continued) Notice that normally only one Digital Converter is needed to supply a stereo or multi-channel amplifier system, therefore most of the functions implemented in the circuit have summing outputs The signal circuits are biased by fixed negative and positive voltages referred to Ground. Instead the final stages of the output amplifiers are supplied by two external voltages that are following the audio signal . In this way the headroom for the output transistors is kept at minimum level to obtain a high efficiency power amplifier. The Compressor circuits, one for each channel, performs a particular transfer behavior to avoid the dynamic restriction that an adaptive system like this requires. To have a high flexibility the attack / release time and the threshold levels are externally programmable. The tracking signal for the external digital converter is generated from the Absolute Value block that rectifies the audio signal present at the compressor output. The outputs of these blocks are decoupled by a diode to permit an easy sum of this signal for the multichannel application. The output power bridges have a dedicated input pin to perform an AC decoupling to cancel the compressor output DC offset. The gain of the stage is equal to 4 (+12dB). A sophisticated circuit performs the output transistor power detector that , with the digital converter, reduces the power supply voltage . Moreover, a maximum current output limiting and the over temperature sensor have been added to protect the circuit itself. The external voltage applied to the STBY/MUTE pin forces the two amplifiers in the proper condition to guarantee a silent turnon and turn-off. ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit +Vs Positive supply voltage referred to pin 13 (GND) 30 V -Vs Negative supply voltage referred to pin 13 (GND) -24 V VCD+ Positive supply voltage tracking rail referred to pin 13 (GND) 22 V VCD+ Positive supply voltage operated to Vs+(1) 0.3 V VCD- Negative supply voltage referred to -Vs (1) -0.3 V VCD- Negative supply voltage tracking rail referred to pin 13 (GND) -22 V VAtt_Rel1 VAtt_Rel2 Pin 3, 25 Negative & Positive maximum voltage referred to GND (pin 13) -0.5 to +20 V VPwr_Imp1 VPwr_Imp2 VTrk_1 VTrk_2 Pin 7, 21, 18, 10 Negative & Positive maximum voltage referred to GND (pin 13) -20 to +20 V VIn_pre1 VIn_pre2 Pin 8, 20 Negative & Positive maximum voltage referred to GND (pin 13) -0.5 to +0.5 V Vthreshold Pin 17 Negative & Positive maximum voltage referred to GND (pin 13) -7 to +0.5 V Istb-max Pin 11 maximum input current (Internal voltage clamp at 5V) 500 µA Pin 11 negative maximum voltage referred to GND (pin 13) -0.5 V Output Current 7.0 A Vstbymute IOUT Note 1: VCD- must not be more negative than -Vs and VCD+ must not be more positive than +VS Note 2: All pins withstand ±2KV ESD but not pin 11 2/16 STA550 Figure 1. Connection Diagram between STA550 and STAbp01 490 PROTECTION STABP01 2K 1K VREF 1V 490 INTERNAL CIRCUIT ON 10V 6.82K UVLO: 7V = on 5V = off - Q R Q S +10V 10V + 14 1V + 13 250Hz 1V CLOCK EMI BARRIER OPTIONAL 10 CD+ 4 VFB 3 - V+ 2 + 2K Q Q - S COMP ERROR AMP 100K 2200pF COMP/3 GATE 10pF 5 + CURRENT_SENSE - 680pF 499K DISCHARGE (RESET) TRANSISTOR FA IN 1V 10V + R17 18 16 REC_OUT ONE SHOT +VS -VS 14 27 OUT_ PRE1 9 COMPRESSOR 3 - TRK_1 10 EMI BARRIER OPTIONAL GND PWR_INP1 7 13 CD+1 PEAK/2 DETECTOR 4 5 OUT1CD-1 15 CD+ 12 PROT. PROTECTION OTHER STA575 PROTECTION TURNON/OFF SEQUENCE Ict 11 STBY/MUTE PEAK/2 DETECTOR S1 25 CD+2 V/l 20 OUT1+ 2 SOA DETECTOR VOLTAGE PROTECTION RSENSE 6 +2 OUTPUT BRIDGE RSENSE 22 +2 24 OUT2+ COMPRESSOR ABSOLUTE VALUE BLOCK ∆G - 2.55K DUTY ACCEL V/l 15K 2.43K ONE SHOT DELAY OPEN DRAIN OUTPUT + 17 +25V IN_PRE2 - 17 1V THERMAL PROTECTION 1000pF Q 16 OTHER STA575 TRK-OUT 100pF D 1V -1 Ict ATT_REL2 ISENSE 15 Q ∆G 680pF 95K 10V RESET ABSOLUTE VALUE BLOCK 8 +25V THRESH ISENSE 1V R 1 S1 TRK_OUT GROUND2 CD+ CLK FAST ATTACK CONTROL - ATT_REL1 9 + + IN_PRE1 OUTPUT CD- BUFFER + - BUFFER OUT Q GATE 8 ONE SHOT SIGNAL 19 20 R DEAD TIME 1V PWM LATCH BUFFER IN Q SOFT SW RESET POWER_VS2 + - S 6 GROUND1 7 Q RESET 1K 2.67K 1V + R 11 D Q - 10K +10V 12 1V + R CLK CURRENT SENSE COMPARATOR 2R 4.99K OUTPUT SOFT SWITCH + 1V POWER SUPPLY1 -1 + 23 19 OUT_ PRE2 18 TRK_2 21 OUT2CD-2 OUTPUT BRIDGE 26 STA575 PWR_INP2 D02AU1391 GND-AUDIO GND 3/16 STA550 THERMAL DATA Symbol Tj Parameter Max Junction temperature Rth j_case Thermal Resistance Junction to case .............................. ..max Value Unit 150 °C 1 °C/W Value Unit OPERATING RANGE Symbol Parameter +Vs Positive supply voltage +20 to +30 V -Vs Negative supply voltage -10 to -22 V 5V ≤ (Vs+ - VCD+) ≤ 10V V ∆Vs+ Delta positive supply voltage VCD+ Positive supply voltage tracking rail +3 to 17 V VCD- Negative supply voltage tracking rail -17 to -3 V Current at pin In_Pre1, In_Pre2, related to compressor behaviour -1 to +1 mA peak Voltage at pin Threshold -5 to 0 V Ambient Temperature Range 0 to 70 °C 200 µA Iin_Max Vtrheshold Tamb Isb_max Pin 11 maximum input current (Internal voltage clmp at 5V) PIN CONNECTION CD-2 OUT2+ ATT_REL2 CD+2 OUT2- IN_PRE2 PWR_INP2 TRK_2 OUT_PRE2 TRK_OUT THRESHOLD +VS CD+ GND PROTECTION TRK_1 STBY/MUTE IN_PRE1 OUT_PRE1 CD+1 PWR_INP1 OUT1- OUT1+ ATT-REL1 CD-1 -VS 4/16 -Vs 27 1 D01AU1251 STA550 PIN FUNCTION N° Name Description 1 -Vs 2 CD-1 3 Att_Rel1 4 Out1+ Channel 1 speaker positive output 5 Out1- Channel 1 speaker negative output 6 CD+1 Channel 1 positive power supply 7 Pwr_Inp1 8 In_pre1 9 Out_pre1 10 Trk_1 11 Stby/mute Standby/mute input voltage control 12 Protection Protection signal for STABP01 digital processor 13 Gnd Analog Ground 14 +Vs Positive Bias Supply 15 CD+ Time varying tracking rail positive power supply 16 Trk_out Reference output for STABP01 digital processor 17 Threshold 18 Trk_2 19 Out_pre2 20 In_pre2 21 Pwr_Inp2 22 CD+2 Channel 2 positive power supply 23 Out2- Channel 2 speaker negative output 24 Out2+ Channel 2 speaker positive output 25 Att_Rel2 26 CD-2 27 -Vs Negative Bias Supply Channel 1 Time varying tracking rail negative power supply Attack release rate for channel 1 Input to channel 1 power stage Pre-amp input for channel 1 (virtual ground) Output channel 1 pre-amp Absolute value block input for channel 1 Compressor threshold input Absolute value block input for channel 2 Output channel 2 pre-amp Pre-amp input for channel 2 (virtual ground) Input to channel 2 power stage Attack release rate for channel 2 Channel 2 Time varying tracking rail negative power supply Negative Bias Supply 5/16 STA550 ELECTRICAL CHARACTERISTCS (Test Condition: Vs+ = 26V, Vs- = -22V, V CD+ = 17V, VCD- = -17V, RL = 8Ω, external components at the nominal value f = 1KHz, Tamb = 25°C unless otherwise specified Symbol Parameter Test Condition Min. Typ. Max. Unit 10 11 12 Vpeak 0.8 mA 0.65 12 V V V -1 V PREAMPLIFIER AND COMPRESSOR Vout clamp Maximum Voltage at Out_pre pin Iin Audio input current Vcontrol Voltage at Attack_Release pin Attenuation = 0dB Attenuation = 6dB Attenuation = 26dB 0.35 6 0 0.5 9 Th Input voltage range for the compression Zth Input impedance of Threshold pin Voffset Output Offset at Out_pre pin with: VCRT= 0V; Attenuation = 0dB VCRT= 0.5V; Attenuation = 6dB VCRT= 9V; Attenuation = 26dB Distortion at Out_pre: VCRT= 0V; Attenuation = 0dB VCRT= 0.5V; Attenuation = 6dB VCRT= 9V; Attenuation = 26dB 0.01 VCRT= 0V; Attenuation = 0dB VCRT= 0.5V; Attenuation = 6dB VCRT= 9V; Attenuation = 26dB 10(2) 50 60 µV µV µV 1.5 mA VComp_ THD EN Noise at Out_pre pin : Ict Attack time current at pin Attack_release -5 100 KΩ -10 -250 -450 10 250 450 mV mV mV 5 5 % % % 1. This value is due to the thermal noise of the external resistors Rr and Ri. TRACKING PARAMETERS Tracking reference voltage gain 13 14 Vtrk_out Tracking ref. output voltage 0 20 Itrk_out Current capability 5 6 Ztrk_in Input impedance (TRK1/2) Gtrk 15 V V 7 1 mA MΩ OUTPUT BRIDGE Gout Half Output bridge gain 5.5 6 6.5 dB Gch Output bridge differential gain 11 12 13 dB ∆Gch Output bridges gain mismatch -1 1 dB Pout Continuous Output Power THD Total harmonic distortion of the output bridge THD = 0.5% THD = 10% 50 64 55 70 W W THD = 10%; RL= 4Ω; VCD+ = 13V; VCD- = -13V; VS+ = 20V; VS- = -20V 64 70 W 0.01 % Po = 5W f = 20Hz to 20KHz; Po = 30W VOff 6/16 Output bridge D.C. offset 0.1 % 50 mV STA550 ELECTRICAL CHARACTERISTCS (continued) Symbol EN Parameter Noise at Output bridge pins Test Condition Min. f = 20Hz to 20KHz; Rg = 50Ω Typ. Max. Unit µV 12 Zbr_in Input impedance Rdson Output power Rdson OLG Open Loop Voltage Gain 100 dB GB Unity Gain Bandwidth 1.4 MHz SR Slew Rate 7 V/µs 100 IO = 1A 140 180 KΩ 200 400 mΩ PROTECTION Vstby Stby voltage range 0 0.8 V Vmute Mute voltage range 1.6 3 V Vplay Play voltage range 4 5 V Th1 First Over temperature threshold 130 °C Th2 Second Over temperature threshold 150 °C Unbal. Ground Upper Unbalancing ground threshold Referred to (CD+ - CD-)/2 5 V Unbal. Ground Lower Unbalancing ground threshold Referred to (CD+ - CD-)/2 -5 V Under voltage threshold |Vs+| + |Vs-| 20 V Pd_reg. Power dissipation threshold for system regulation Iprot = 50µA; @ Vds = 10V Pd_max Switch off power dissipation threshold @ Vds = 10V 48 W Iprot Protection current slope for Pd > Pdreg 400 µA/W Ilct Limiting Current threshold UVth 25 5.5 31 6 6.5 W A I+Vs Positive supply current Stby (Vstby/mute pin = 0V) Mute (Vstby/mute pin = 2.5V) Play (Vstby/mute pin = 5V no signal) 4 35 35 mA mA mA I-Vs Negative supply current Stby (Vstby/mute pin = 0V) Mute (Vstby/mute pin = 2.5V) Play (Vstby/mute pin = 5V no signal) 4 35 35 mA mA mA ICD+ Positive traking rail supply current Stby (Vstby/mute pin = 0V) Mute (Vstby/mute pin = 2.5V) Play (Vstby/mute pin = 5V no signal) 100 110 110 µA mA mA ICD- Negative traking rail supply current Stby (Vstby/mute pin = 0V) Mute (Vstby/mute pin = 2.5V) Play (Vstby/mute pin = 5V no signal) 100 110 110 µA mA mA 7/16 STA550 FUNCTIONAL DESCRIPTION The circuit contains all the blocks to build a stereo amplifier. Each single channel is based on the Output Bridge Power Amplifier, and its protection circuit. Moreover, the compression function and a signal rectifier are added to complete the circuit. The operation modes are driven by The Turn-on/off sequence block. In fact the IC can be set in three states by the Stby/mute pin: Standby ( Vpin < 0.8V), Mute (1.6V < Vpin < 3V), and Play (Vpin > 4V). In the Standby mode all the circuits involved in the signal path are in off condition, instead in Mute mode the circuits are biased but the Speakers Outputs are forced to ground potential. These voltages can be get by the external RC network connected to Stby/Mute pin. The same block is used to force quickly the I.C. In standby mode or in mute mode when the I.C. dangerous condition has been detected. The RC network in these cases is used to delay the Normal operation restore. The protection of the I.C. are implemented by the Over Temperature, Unbalance Ground, Output Short circuit, Under voltage, and output transistor Power sensing as shown in the following table: Table 1. Protection Implementation Fault Type Condition Protection strategy Action time Release time Chip Over temperature Tj > 130 °C Mute Fast Slow Related to Turn_on sequence Chip Over temperature Tj > 150 °C Standby Fast Slow, Related to Turn_on sequence Unbalancing Ground |Vgnd| > ((CD+) (CD-))/2 + 5V Standby Fast Slow, Related to Turn_on sequence Short circuit Iout > 6A Standby Fast Slow, related to Turn_on sequence Under Voltage |Vs+| + |Vs-|< 20V Standby Fast Slow, related to Turn_on sequence Extra power dissipation at output transistor Pd tr. >25W Reducing DIGITAL CONVERTER output voltage. Related to the DIGITAL CONVERTER Related to the DIGITAL CONVERTER Maximum power dissipation at output transistor Pd tr. > 48W Standby Fast Slow, related to Turn_on sequence See the POWER PROTECTION paragraph for the details Compression An other important function implemented, to avoid high power dissipation and clipping distortion, is the Compression of the signal input. In fact the preamplifier stage performs a voltage gain equal to 5, fixed by Ri and Rr external resistor, but in case of high input signal or low power supply voltage, its gain could be reduced of 26dB. This function is obtained with a feedback type compressor that , in practice, reduces the impedance of the external feedback network. The behavior of compression it's internally fixed but depends from the Audio input voltage signal level, and from the Threshold voltage applied to the Threshold pin. The attack and release time are programmable by the external RC network connected to the Att_Rel pins. The constraints of the circuit in the typical application are the following: Vthreshold range = -5 to 0 Vin peak max = 8V Vout peak max = 10V 8/16 STA550 Gain without compression (G) =5 Max Attenuation ratio = 26 dB The following graph gives the representation of the Compressor activation status related to the Vthreshold and the input voltage. The delimitation line between the two fields, compression or not, is expressed by the formula : 2 ⋅ Vthresh old V in = ------------------------------------------G Where G is the preamplifier gain without compression. In the compression region the gain of the preamplifier will be reduced (G = 2·Vthreshold/Vin) to maintain at steady state the output voltage equal 2*|Vthreshold| . Instead in the other region the compressor will be off (G = 5). The delimitation line between the two fields can be related to the output voltage of the preamplifier: in this case the formula is : V o ut = 2 ⋅ Vthre sho ld Figure 2. Compressor activation field VIN PEAK 8 6 COMPRESSION G<5 4 2 G=5 D01AU1264 1 2 3 4 5 |Vthreshold| The relative attenuation introduced by the variable gain cell is the following : V th 2 Attenu atio n = 20 log --- ⋅ ---------------------5 V in _peak The total gain of the stage will be: Gdb = 20log5 + Attenuation The maximum input swing is related to the value of input resistor, to guarantee that the input current remain under Iin_Max value (1 mA). V in_peak R i > ---------------------I in_max 9/16 STA550 Figure 3. Compressor attenuation vs. input amplitude Attenuation(dB) 0 -6 |Vth -12 =5| |Vth -18 |Vt =2. 5| h= 1| -24 D01AU1265 1 2 3 4 5 6 7 8 |Vinpk| ABSOLUTE VALUE BLOCK The absolute value block rectifies the signal after the compression to extract the control voltage for the external digital converter. The output voltage swing is internally limited, the gain is internally fixed to 14. The input impedance of the rectifier is very high , to allow the appropriate filtering of the audio signal before the rectification (between Out_pre and Trk pins). OUTPUT BRIDGE The Output bridge amplifier makes the single-ended to Differential conversion of the Audio signal using two power amplifiers, one in non-inverting configuration with gain equal to 2 and the other in inverting configuration with unity gain. To guarantee the high input impedance at the input pins, Pwr_Inp1 and Pwr_Inp2, the second amplifier stages are driven by the output of the first stages respectively. POWER PROTECTION To protect the output transistors of the power bridge a power detector is implemented (fig 3). The current flowing in the power bridge and trough the series resistor Rsense is measured reading the voltage drop between CD+1 and CD+. In the same time the voltage drop on the relevant power (Vds) is internally measured. These two voltages are converted in current and multiplied: the resulting current , Ipd, is proportional to the instantaneous dissipated power on the relevant output transistor. The current Ipd is compared with the reference current Ipda, if bigger (dissipated power > 25W) a current, Iprot, is supplied to the Protection pin. The aim of the current Iprot is to reduce the reference voltage for the digital converter supplying the power stage of the chip, and than to reduce the dissipated power. The response time of the system must be less than 200µSec to have an effective protection. As further protection, when Ipd reaches an higher threshold (when the dissipated value is higher then 48W) the chip is shut down, forcing low the Stby/Mute pin, and the turn on sequence is restarted. 10/16 STA550 Figure 4. Power Protection Block Diagram RSENSE CD+ CD+1 ILOAD V/I OC1 ILIM MULTIPLIER CURRENT COMP X PDP1 IPD V/I IPDP I_PD TO TURN-ON/OFF SEQUENCE CURRENT COMP IPD OPA TO TURN-ON/OFF SEQUENCE IPROT TO PROT PAD OPA IPDA OUT1+ CD- D01AU1266 OUT1- In fig. 4 there is the power protection strategy pictures. Under the curve of the 25W power, the chip is in normal operation, over 48W the chip is forced in Standby. This last status would be reached if the digital converter does not respond quikly enough reducing the stress to less than 48W. The fig.5 gives the protection current, Iprot, behavior. The current sourced by the pin Prot follows the formula: –4 ( Pd – Pd_av _th ) ⋅ 5 ⋅ 10 Iprot ≡ -----------------------------------------------------------------1.25V for Pd < Pd_av_th the Iprot = 0 Independently of the output voltage, the chip is also shut down in the folowing conditions: When the currentthrough the sensing resistor, R sense, reaches 6A (Voltage drop (CD+) - (CD+1) = 700mV). When the average junction temperature of the chip reaches 150°C. When the ground potential differ from more than 5V from the half of the power supply voltage, ((CD+)-(CD-))/2 When the sum of the supply voltage |Vs+| + |Vs-| <20V The output bridge is muted when the average junction temperature reaches 130°C. 11/16 STA550 Figure 5. Power protection threshold Figure 6. Protection current behaviour Ids (mA) Iprot(mA) Ilim = 6A 6 20 Standby Bu Pd_Max = 48W cK 4 Iprot slope=0.4mA/W Lim Pd_reg = 25W ita tio Normal n Operation 2 10 Vds (V) 10 20 30 10 D01AU1306 40 20 30 40 50 Pd(W) 60 Figure 7. Test and Application Circuit C5 C17 C7 R3 INPUT1 OUT_PRE1 R1 R7 R9 C1 TRK_1 9 8 R11 PWR_INP1 10 7 4 OUT1+ IN_PRE1 R5 ATT_REL1 5V 3 5 R16 CD+1 CD+ CD+ R17 R24 C12 C14 CD+2 +VS +VS R22 C15 -VS -VS CD- CD-1 CD-2 TRK-OUT TRK-OUT PROT R19 15 11 22 R14 C9 14 THRESH 13 24 PROT THRESH 27 MUTE STBY R15 OUT2+ 23 1 OUT2- 2 C4 26 16 25 ATT_REL2 12 17 R18 21 18 PWR_INP2 C2 19 TRK_2 R10 R12 12/16 STBY/ MUTE C11 -VS D1 R20 6 C10 GND C13 R13 OUT1- C3 R8 20 R6 IN_PRE2 INPUT2 R2 OUT_PRE2 C8 C6 R4 C16 D01AU1267 STA550 EXTERNAL COMPONENTS Name Function Value Formula Ri R1 = R2 Input resistor 10KΩ (|G| = 5, Rr = 50KΩ) Rr R i = ------G Rr R3 = R4 Feedback resistor 50KΩ (|G| = 5, Ri = 10KΩ Rr = G ⋅ Rr Cac C1 = C2 AC Decoupling capacitor 100nF (fp = 16Hz, Rac =100KΩ ) 1 Cac = --------------------------------2π ⋅ fp ⋅ Rac Cct C3 = C4 Capacitor for the attack time 2.2µF (Tattack = 13mSec, Vcontrol = 9V, Ict = 1.5mA) Ict Cct = attack ------------------------Vcontrol R5 = R6 Release constant time Resistor 470KΩ (t = 1 Sec. , Cct = 2.2 µF ) τ Rct = --------Cct R7 = R8 Resistor for tracking input voltage filter 10KΩ R9 = R10 Resistor for tracking input voltage filter 56KΩ R11 = R12 Resistor for tracking input voltage filter 10KΩ C5 = C6 Capacitor for Tracking input voltage filter 1nF C7 = C8 Dc decoupling capacitor 1µF R13 Bias Resistor for Stby/Mute function 10KΩ R14 Stby/Mute constant time resistor 30KΩ R15 Mute resistor 30KΩ C9 Capacitor for Stby/Mute resistor 2.2µF R16 = R17 Sensing resistor for SOA detector 120mΩ 5% 4W R18 Conversion resistor for threshold voltage 100KΩ C10 = C11 Power supply filter capacitor 100nF R22 = R24 Centering resistor C12 = C13 Tracking rail power supply filter 400 Ω , 1W 680nF R19 Protection 1KΩ R20 TRK_out 40KΩ 470 µF , 63V C14 = C15 Power supply filter capacitor C16 = C17 Feedback capacitor 100pF Schottky diode SB360 D1 Note: Vcontrol is the voltage at Att_Rel pin. 13/16 STA550 APPLICATION HINTS PREAMPLIFIER AND COMPRESSOR In the application circuit showed in figure 7, R 1/R3 (or R2/R4) ratio fix the gain of the preamplifier. If the input signal is very low, is possible to increase the gain fixing the product Vin∗G = cost. In that case is possible to increase G decreasing R1,2 from 10KΩ until 2KΩ without relevant effetcs on the circuitbehavior and remaining in the operating range Iin_max = Vin_max/R1(2),<1mA. So it is possible to increase the preamplifier gain until 25. If no compression is present (equivalnt compressor Gm=0), the effects are: – The output voltage offset increase – The SNR decrease The following table shows these variations: R1,2 VIN MAX G VOFFSET EN 10KΩ 8V 5 15mV 10µV 5KΩ 4V 10 30mV 13µV 2KΩ 1.6V 25 75mV 20µV R3(4) = 50KΩ and all the other external components are the same Attenuation = 0 dB If the compression is active the circuit behaviour is the same. It”s also possible to eliminate the compressor. In this case the ATT_REL (1,2) pin must be connected to gnd. STBY-MUTE CIRCUIT In the suggested application circuit (figure 7), the resistor for Standby/Mute function (R13) is connected between the Standby/Mute switches and 5V Supply. It is possible to connect the resistor to another Supply Voltage level VL, but in that case also the resistor value (R13,14) must be changed according to the following formula (fixing VSTBY/MUTE = 2.5V and R15 = 10KΩ): R 13 = ( 4 ⋅ VL – 10 )KΩ R 14 = ( 4 ⋅ VL + 10 )KΩ HEADROOM In the suggested application circuit the supply voltage to obtain 75W (Power Output) on 8Ω (Rload) is: V supply = ∆V + I L, MAX ⋅ R DS on It is also possible to increase the system’s efficiency forcing the headroom to follow the output signal (variable drop insteadof a constant drop). In that case: V sup ply = ∆ V + IL ( V ) ⋅ RDS on 14/16 STA550 DIM. MIN. 4.45 1.80 A B C D E F (1) G G1 H (2) H1 H2 H3 L (2) L1 L2 (2) L3 L4 L5 M M1 N O R R1 R2 R3 R4 V V1 V2 V3 0.75 0.37 0.80 25.75 28.90 22.07 18.57 15.50 7.70 3.70 3.60 mm TYP. 4.50 1.90 1.40 0.90 0.39 1.00 26.00 29.23 17.00 12.80 0.80 22.47 18.97 15.70 7.85 5 3.5 4.00 4.00 2.20 2 1.70 0.5 0.3 1.25 0.50 MAX. 4.65 2.00 MIN. 0.175 0.070 1.05 0.42 0.57 1.20 26.25 29.30 0.029 0.014 22.87 19.37 15.90 7.95 0.869 0.731 0.610 0.303 4.30 4.40 0.145 0.142 0.031 1.014 1.139 inch TYP. 0.177 0.074 0.055 0.035 0.015 0.040 1.023 1.150 0.669 0.503 0.031 0.884 0.747 0.618 0.309 0.197 0.138 0.157 0.157 0.086 0.079 0.067 0.02 0.12 0.049 0.019 MAX. 0.183 0.079 OUTLINE AND MECHANICAL DATA 0.041 0.016 0.022 0.047 1.033 1.153 0.904 0.762 0.626 0.313 0.169 0.173 5˚ (Typ.) 3˚ (Typ.) 20˚ (Typ.) 45˚ (Typ.) Flexiwatt27 (vertical) (1): dam-bar protusion not included (2): molding protusion included V C B V H H1 V3 A H2 O H3 R3 L4 R4 V1 R2 L2 N L3 R L L1 V1 V2 R2 D R1 L5 Pin 1 R1 R1 E G G1 F FLEX27ME M M1 7139011 15/16 STA550 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 2003 STMicroelectronics - All Rights Reserved is the registered trademark and patented technology of INDIGO manufacturing inc. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States.. http://www.st.com 16/16