STKM2000 SERIES ® 2 µ/2 POLY/2 METAL BiCMOS MIXED ANALOG-DIGITAL STANDARD CELLS ■ ■ ■ ■ ■ ■ ■ ■ ADVANCED BICMOS 2 µ/2 POLY/ 2 METAL PROCESS TWIN TUB PROCESS HIGH LATCH-UP IMMUNITY POWER SUPPLY : MAXIMUM RATING : -0.5V TO 12V OPERATING CONDITIONS : 3V TO 10V MIXED ANALOG - DIGITAL LIBRARY : ANALOG BIPOLAR LIBRARY ANALOG CMOS LIBRARY ANALOG BICMOS LIBRARY DIGITAL CMOS LIBRARY HIGH PROCESS PERFORMANCES: TRANSITION FREQUENCY, NPN = 6 GHz VERTICAL PNP = 2, 5 GHz DIGITAL CMOS OPERATING FREQUENCY : UP TO 30 MHz CAD SOFTWARE SUPPORT: FULLY INTEGRATED A.D.S. (ANALOG DESIGN SYSTEM) WITH ANALOG BLOCK GENERATORS, SWITCHED CAPACITOR FILTER COMPILER; DIGITAL FUNCTIONS GENERATOR, RAM, ROM, PLA GENERATORS AVAILABILITY OF EEPROM DEVICES, ZENER DIODE, SCHOTTKY DIODE ■ ■ OPERATING TEMPERATURE RANGE: COMMERCIAL: 0 TO 70oC INDUSTRIAL: -40 TO 85oC MILITARY: -55 TO 125oC PACKAGE OPTIONS: DIL: PLASTIC OR CERAMIC SMD: SO, PLCC, QFP WAFER OR DIE ASIC PRODUCTS DESCRIPTION With the STKM2000 series, SGS-THOMSON Microelectronics introduces the “state of the art” product for analog signal processing, chain from sensor to actuator. The introduction of new concepts (cells library and CAD) opens the design of analog functions and mixed analog and digital circuits with a safe and powerful approach. This new ASIC approach is the combination of innovative : ● ● ● ● ● BICMOS process Mixed libraries (ANALOG + DIGITAL) Generators and compilers “User friendly” CAD system Customer interface Figure 1 : The STKM2000 Series, a complete system solution ~ SENSOR A A ~ ACTUATOR A/D CONVERTER DSP D/A CONVERTER A ~ BIP : GB = 100MHz MOS : GB = 10MHz 500 mA max. f C(MAX) = 150kHz f MAX = 30MHz 12 Bits +-1/2 Bit 15 µ s November 1989 12 Bits +-1/2 Bit 15 µ s 1/10 STKM2000 SERIES STKM2000 ARCHITECTURE Technology T h e ST KM 20 0 0 Se r ie s de vel ope d by SGS-THOMSON Microelectronics uses an advanced BICMOS silicon gate process with dual polysilicon layers and dual metal layers. This process is optimized to achieve high performance in digital CMOS applications. Depending on the operating supply voltage (10V, or 5V), the CMOS process behaves as an N-WELL technology (respectively with 2 µ gate length or 1.8 µ gate length) with operating speeds up to 30MHz. Thanks to the two metal layers, the digital part of the circuit can reach high gate density with low parasitic capacitances. For analog functions, the STKM2000 series takes advantage of the bipolar structure: ● ● very high speed NPN transistor : fT = 6 GHz very high speed vertical PNP : fT = 2.5 GHz This allows high gain - bandwith operational amplifier (50 MHz), low noise input amplifier, short propagation delay comparator, ... With the same BICMOS process, the analog CMOS performance come from the high density CMOS structure with a double poly layer for accurate capacitors, low consumption CMOS amplifier (30 µA), CMOS switches, high accuracy switched capacitor filters (up to 100 kHz for center frequency). STKM2000 cell concepts SG S-T H O MSO N M ic ro el e ct r on i cs h as predesigned and precharacterized cells which are selected, placed and interconnected on the chip to implement digital and analog cells having different height and supply voltages. In addition some macrocells are designed as fixed blocks, so called “hard blocks” : filters, A/D and D/A converters; some hard blocks are automatically generated and parametrized from a compiler: S.C. filters, PLA, RAM, ROM... STKM2000 chip topology The chip is optimized versus the cell complexity, in a row based structure with different heights. 2/10 ® Peripheral cells surround the internal active chip area to interface with its external environment. Despite the row based architecture, “hard blocks” can be implemented with efficient floor planning organization. STKM2000 Cell libraries SGS-THOMSON Microelectronics introduces the “programmable” library; instead of working with a finite number of cells of the library, the designer has now access to an infinite number of functions. Defining only some properties, the designer is able to create himself the cells needed for his application. For example, the following electrical parameters are accessible and adjustable: ● ● ● ● ● ● ● ● gain-bandwith product phase margins, frequency compensation output buffer current biasing currents resistor, capacitor fields current, source or sink adjustable Ron switch resistor supply voltage assignment The analog library is operating in a large voltage range: 3V to 10V. The basic analog library contains: ● ● 60 analog CMOS functions 25 analog BIPOLAR functions From single transitor to 12 bits A to D converter (with autocalibration), each setup becomes possible. The digital CMOS library uses the same flexibility with a complete set of basic digital functions (NAND, NOR, Flip-Flop, ...) and some cell generators: register, counter, logic comparator, ... More than 60 digital cells are available. ● STKM2000 SERIES Figure 2: The STKM2000 Series, a complete system solution ANALOG LIBRARY NPN transistor Lateral PNP Substrate PNP Isolated PNP NPN input comparator PNP input comparator N input comparator P input comparator N-MOS transistor P-MOS transistor NPN high-speed amplifier N input CMOS Op-Amp P input CMOS Op-Amp Crystal oscillator RC oscillator Transconductance Power-on reset (with adjustable threshold and hysteresis) Analog multiplexer Voltage to current converter Voltage reference 8 bits, A/D and D/A converters 12 bits A/D and D/A converters DIGITAL LIBRARY AND, NAND, OR, NOR, inverter Exclusive OR, NOR D latch Input buffer (TTL/CMOS) Output buffer (TTL/CMOS) Shift register Binary counter Decimal counter Magnitude comparator 3/10 ® STKM2000 SERIES CAD SUPPORT: A.D.S. (Analog Design System) SGS-THOMSON Microelectronics has introduced a sophisticated CAD approach to reduce the development leadtime and to increase design flexibility and safety. Programmable cells in the library are defined as: ● alternative cell or, ● adjustable cell or, ● telescopic cell or, ● parametrisable cell ● ● ● Operational amplifier generator From a generic symbol and some properties, several parameters of the amplifier will be adjusted: Biasing current which controls major parameters of amplifier (gain-bandwidth, slew rate, power consumption). Frequency compensation which allows to adjust and optimize the dynamic parameters versus the capacitive and resistive load. Power down capabilities. Supply voltage of the cell. ● Some specific parts of the design are automatically handled by an analog design manager, in order to: ● A major step has been made with the introduction of function generator and compiler approaches to improve design automation and design efficiency. reduce capture errors make unexperienced designer’s task easier improve schematics lisibility check electrical design rules (Analog or Digital) The Analog Design manager takes into account: ● transconductance block generation ● automatic cell biasing ● unconnected pins and power down processing ● multipower supplies processing ● ● ● A specific software manages all these properties and automatically updates all libraries included in the design flow: macro models and transistor level models, footprint, GDS2 layout, LVS netlist. Figure 3: Analog Design System (A.D.S.) flow Schematic Capture DIGITAL Generator D Digital Analog Symbols Data Base Netlist Extractor Top Level Simulation SABER Digital Models Filter Compiler G Analog Generator G Behavioral Models G Programmable Cells Generation Transistor Models G Place & Route D Analog Simulation Cells Boxes G Back Annotation ST SPICE Digital Simulation HILO 3 GDSII File DRC/LVS PG Tape 4/10 ® Cells Layout G STKM2000 SERIES Filter compiler From the template defined at the beginning up to the complete layout, the software handles automatically the filter synthesis and the layout compilation: ● evaluation/mathematical analysis ● switched capacitor synthesis ● simulation ● Monte-Carlo analysis ● layout generation The schematic capture uses a block which is programma ble according t o t he required complexity. Any kind of filters is available from 2nd up to 12th order. A part from the software automation, the A.D.S. CAD tool works around standard softwares. Digital cell generator For a set of basic digital cells, the user has access to generators which handle the netlists and interface with the layout tools. The generator creates a “ so-called” soft macrocell taking into account the complete netlist: ● ● ● counters shift registers magnitude comparators, ... The CAD approach is compatible with both approaches: ● ● VAXTM/VMS operating system SUNTM/UNIX operating system VAXTM SUNTM CASS EDGE (SILVAR LISCOTM) (CADENCETM) HILO 3 MOZART (GENRADTM) (SGS-THOMSON) ST-SPICE ST-SPICE (SGS-THOMSON) (SGS-THOMSON) SABER SABER (ANALOGYTM) (ANALOGYTM) Schematic capture Logic simulation Analog simulation Top level simulation CALMP Layout (SILVAR LISCOTM) EDGE (CADENCETM) DRACULA EDGE (CADENCETM) (CADENCETM) DRC - LVS 5/10 ® STKM2000 SERIES Customer design interface SGS-THOMSON Micorelectronics has developed several interfaces for customers giving them easy and flexible design approaches for STKM2000. Users can access Analog Design System (A.D.S.): ● ● ● via SGS-THOMSON design centers via SGS-THOMSON associated design centers via CAE workstations C AE w o rst at i o n ca p ab i l it i e s a re und er development on: ● ● ● Dazix System Mentor Graphics Sun In that case,direct interfaces will be offered in order to make design implementation with A.D.S. (layout and test generations). According to these design possibilities, SGS- THOMSON defines 3 main interfaces. Figure 4 outlines these interfaces. Each interface details the responsibilities of customer and SGS-THOMSON during circuit development flow. Figure 4: SGS-THOMSON - CUSTOMER interfaces Responsibility level Circuit definition Interface 2 Interface 3 Interface 4 Breadboard schematics Simulated schematics Layout tape Ctm Ctm Schematics Simulations Ctm ST ST Layout Final control Prototyping phase ST + Ctm ST + Ctm ST + Ctm ST ST ST 6/10 ® STKM2000 SERIES MAXIMUM RATINGS Symbol Min Max Unit Supply voltage - 0.5 12.0 V VI, VO I/O voltage - 0.5 VDD + 0.5 V II, IO I/O current - 40 + 40 nA Tstg storage temp. (ceramic) - 65 + 150 o storage temp. (plastic) - 40 + 125 o VDD Parameter Note 1: Stresses above those under “maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation for the device at these or any other C C conditions above indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED DC OPERATING CONDITIONS Voltage referred to VSS Symbol Parameter VDD Operating supply voltage Tamb Operating ambient temperature Military Industrial Commercial Min Max Unit 2.7 11 V - 55 + 125 o - 40 + 85 o 0 + 70 o C C C DIGITAL LIBRARY AC ELECTRICAL CHARACTERISTICS ABSTRACT Standard condition = 2 loads + 1 mm of metal interconnect Cell code VDD = 10V ± 10%, T = 25oC Description TPHL TPLH Unit OTHER IV1 Standard inverter 2.26 2.01 ns ND2 2 - input NAND 1.74 2.44 ns NR2 2 - input NOR 2.55 2.02 ns FD1 D Flip - Flop 6.44 8.26 From C to QN OB11 TSU 5.00 TH 1.75 TWH 8.25 TWL 5.00 ns CMOS inverting output buffer capacitance load = 100 pF 12.4 12.3 ns 7/10 ® STKM2000 SERIES DC GENERAL ELECTRICAL CHARACTERISTICS VDD = 5V ± 10% or VDD = 10V ± 10% (unless otherwise specified) Symbol VIH VIL Parameter High level TTL input voltage Low level TTL input voltage Condition Min Typ Max To = 0oC / + 70oC 2.0 V To = - 40oC / + 85oC 2.25 V To = - 55oC / + 125oC 2.25 V VDD = 5V ± 10% 0.8 all temp. ranges VIH High level CMOS input voltage VIL Low level CMOS input voltage IOZH Tristate output leakage current IIH 70%VDD 30%VDD 2.5 µA To = - 40oC / + 85oC 5 µA To = - 55oC / + 125oC 10 µA µA To = 0oC / + 70oC - 2.5 µA To = - 40oC / + 85oC - 5.0 µA To = - 55oC / + 125oC - 10.0 µA VO = VDD 1.0 µA T = - 40 C / + 85 C 3.0 µA To = - 55oC / + 125oC 5.0 µA o ICC Low level input leakage current V VO = VDD To = 0oC / + 70oC IIL V VO = VSS High level input leakage current V V To = 0oC / + 70oC IOZL Unit VDD = 5V ± 10% o o VI = VSS To = 0oC / + 70oC - 1.0 µA To = - 40oC / + 85oC - 3.0 µA To = - 55oC / + 125oC - 5.0 µA Max admissible current per pin: - analog ± 20 mA - digital ± 40 mA 8/10 ® STKM2000 SERIES ANALOG LIBRARY AC ELECTRICAL CHARACTERISTICS ABSTRACT Cell code Description Parameters Min Typ Max Unit 1 1.4 ms Offset ±3 ± 10 mV Static BICMOS Propagation delay 90 110 ns comparator (overdrive = 5 mV) ±2 ±7 mV 50 pF Test conditions CMP11 CMP31 Static CMOS Propagation delay comparator (overdrive = 5 mV) Offset CPX11 Capacitor fields Unit capacitance Capacitor value range 0.1 0.1 ± 15 % 1.0 % 1 100 pF ± 15 % 6.5 3000 KΩ Absolute accuracy Matching (capacitor ratio) CPP11 Monolithic Capacitor Capacitor range 0.5 Absolute accuracy RPM/PPM Resistor/Potentiometer P-Base SWI1 Analog switch Resistor value range Absolute accuracy ± 20 % Matching ±1 % Temperature coefficient 0.2 % Voltage coefficient 0.05 % 25 KΩ Elementary switch RON value Number of switches in parallel MN11 Telescopic NMOS pF RON value 5 1 3 Ω 100 transistor OPA31 OPA41 General purpose Unity gain bandwidth 3.3 MOS Operational Current consumption 700 amplifier Phase margin Internal bipolar Operational Amplifier 4.6 MHz µA o (C1 = 100 pF, R2 = 10 kΩ) 60 Offset ±3 ± 10 mV Unity gain-bandwidth 9 30 MHz current consumption 240 µA Phase margin 62 o (CL = 15 pF, RL = 100kΩ) ±1 Offset OPA71 ±5 mV Rail to rail external Unity gain bandwidth 2.3 MHz MOS operational current consumption 360 uA Amplifier Phase margin 80 o (CL = 100 pF, RL = 100KΩ) OTA11 Offset ±3 MOS Unity gain - bandwidth 24 transconductance (CL = 2 pF) ± 10 mV MHz amplifier POR11 Programmable Power on Reset Active Level Accuracy Hysteresis Accuracy ±5 ±5 % % VRF11 Voltage bandgap Output voltage accuracy ±2 % 100 ppm reference Temperature coefficient Current consumption 15 µA 9/10 ® STKM2000 SERIES ANALOG LIBRARY AC ELECTRICAL CHARACTERISTICS ABSTRACT Cell code Description Parameters Min Typ Max Unit 20 MHz 800 KHz Test conditions OSC11 Programmable crystal Frequency 0.1 Frequency 1 oscillator OSC41P RC oscillator Stability versus temperature One pad I.C oscillator Filters ADC81 DAC81 Frequency % / oC 0.01 Stability versus voltage OSC31P 100 0.5 2 %/V 200 KHz Stability versus temperature 0.01 % / oC Stability versus voltage 0.5 %/V Order 2 12 Center frequency 100 KHz 8 bit analog to Conversion time 5 µs digital converter Integral non linearity ± 0.5 LSB Differential non linearity ± 0.5 LSB 1 µs ± 0.5 LSB 8 bit analog to Conversion time digital converter (CL = 2 pF) Integral non linearity Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of SGS-THOMSON Microelectronics. © 1994 SGS-THOMSON Microelectronics - All rights reserved. Purchase of I 2C Components by SGS-THOMSON Microelectronics conveys a license under the Philips I 2C Patent. Rights to use these com2 ponents in an I C system is granted provided that the system conforms to the I 2C Standard Specification as defined by Philips. SGS-THOMSON Microelectronics Group of Companies Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. 10/10 ®