STLC7550 LOW POWER LOW VOLTAGE ANALOG FRONT END . . . . .. .. . . .. . .. . GENERAL PURPOSE SIGNAL PROCESSING ANALOG FRONT END (AFE) TARGETED FOR V.34bis MODEM AND 56Kbps MODEM APPLICATIONS 16-BIT OVERSAMPLING Σ∆ A/D AND D/A CONVERTERS 83dB SIGNAL TO NOISE RATIO FOR SAMPLING FREQUENCY UP TO 9.6kHz @ 3V 87dB DYNAMIC RANGE @ 3V FILTER BANDWIDTHS : 0.425 x THE SAMPLING FREQUENCY ON-CHIP REFERENCE VOLTAGE SINGLE POWER SUPPLY RANGE : 2.7 TO 5.5V LOW POWER CONSUMPTION LESS THAN 30mW OPERATING POWER 3V STAND-BY MODE POWER CONSUMPTION LESS THAN 3µW at 3V PROGRAMMING SAMPLING FREQUENCY MAX. SAMPLING FREQUENCY : 45kHz SYNCHRONOUS SERIAL INTERFACE FOR PROCESSOR DATAS EXCHANGE. MASTER OR SLAVE OPERATIONS 0.50µm CMOS PROCESS TQFP44 PACKAGE STLC7546 MODE OF OPERATION COMPATIBLE Maximum Power Dissipation 30mW is well suited for Battery operations. In case of battery low, STLC7550 will continue to work even at a 2.7V level. STLC7550 also provides clock generator for all sampling frequencies requested for V.34bis and 56Kbps applications. This new AFE can also be used for PC mother boards or add-on cards or stand alone MODEMs. It can be used in a master mode or slave mode. The slave mode eases multi AFE architecture design in saving external logical glue. TQFP44 (10 x 10 x 1.40 mm) (Full Plastic Quad Flat Pack) ORDER CODE : STLC7550TQFP DESCRIPTION The STLC7550 is a single chip Analog Front-end (AFE) designed to implement modems up to 56Kbps. It has been especially designed for host processing application in which the modulation software (V.34bis, 56Kbps) is performed by the main application processor : Pentium, Risc or DSP processors. The main target of this device is stand alone appliances as Hand Held PC (HPC), Personnal Digital Assistants (PDA), Webphones, Network Computers, Set Top Boxes for Digital Television (Satellite and Cable). To comply with such applications STLC7550 is powered nominally at 3V only. November 1998 TQFP48 (7 x 7 x 1.40mm) (Full Plastic Quad Flat Pack) ORDER CODE : STLC7550TQF7 1/17 STLC7550 XTALIN/MCLK XTALOUT MCM DGND DVDD FS SCLK PIN CONNECTIONS (TQFP44) 11 10 9 8 7 6 5 4 3 2 1 12 44 13 43 HC1 14 42 DOUT HC0 15 41 DIN PWRDWN 16 40 TSTD1 M/S 17 39 TS VREFP 18 38 RESET VREFN 19 37 OUT- AGND1 20 36 OUT+ 21 35 22 34 7550-01.EPS AGND2 VCM AVDD IN- IN+ AUXIN- AUXIN+ 23 24 25 26 27 28 29 30 31 32 33 XTALIN/MCLK XTALOUT MCM DGND DVDD FS SCLK PIN CONNECTIONS (TQFP48) 12 11 10 9 8 7 6 5 4 3 2 1 13 48 14 47 HC1 15 46 HC0 16 45 DOUT PWRDWN 17 44 DIN M/S 18 43 TSTD1 VREFP 19 42 TS VREFN 20 41 RESET AGND1 21 40 OUT- 22 39 OUT+ 23 38 24 37 2/17 7550-01.EPS AGND2 VCM AVDD IN- IN+ AUXIN- AUXIN+ 25 26 27 28 29 30 31 32 33 34 35 36 STLC7550 PIN LIST Name Type Description NC - SCLK FS DVDD DGND MCM XTALOUT XTALIN/MCLK HC1 HC0 PWRDWN M/S O I/O I I I O I I I I I Shift Clock Output Frame Synchronization Input (slave)/Output (master) Positive Digital Power Supply (2.7V TO 5.5V) Digital Ground Master Clock Mode Crystal Output Crystal Input (MCM = 1) / External Clock (MCM = 0) Hardware Control Input Hardware Control Input Power down Input Master/Slave Mode Control Pin Input Not connected 18 19 20 19 20 21 VREFP VREFN AGND1 O O I 16-bit D/A and A/D Positive Reference Voltage 16-bit D/A and A/D Negative Reference Voltage Analog Ground 25 26 27 28 29 30 31 36 37 38 39 40 41 42 27 28 29 30 31 32 33 39 40 41 42 43 44 45 AUXIN+ AUXININ+ INAVDD VCM AGND2 OUT+ OUTRESET TS TSTD1 DIN DOUT I I I I I O I O O I I I/O I O Non-inverting Input to Auxiliary Analog Input Inverting Input to Auxiliary Analog Input Non-inverting Input to Analog Input Amplifier Inverting Input to Analog Input Amplifier Positive Analog Power Supply (2.7V to 5.5V) Common Mode Voltage Output (AVDD/2) Analog Ground Non-inverting Smoothing Filter Output Inverting Smoothing Filter Output Reset Function to initialize the internal counters Timeslot Control Input Digital Input/Output reserved for test Serial Data Input Serial Data Output 7550-01.TBL Pin Number TQFP44 TQFP48 1 - 2, 10 to 13, 1 - 2, 10 to 14, 21 to 24, 32 to 22 to 26, 34 to 35, 43 - 44 38, 46 to 48 3 3 4 4 5 5 6 6 7 7 8 8 9 9 14 15 15 16 16 17 17 18 PIN DESCRIPTION 1 - POWER SUPPLY (5 pins) 1.1 - Analog VDD Supply (AVDD) This pin is the positive analog power supply voltage for the DAC and the ADC section. 1.2 - Digital VDD Supply (DVDD) This pin is the positive digital power supply for DAC and ADC digital internal circuitry. It is not internally connected to digital VDD supply (DVDD). 1.3 - Analog Ground (AGND1, AGND2) These pins are the ground return of the analog DAC (ADC) section. In any case the voltage on this pin must be higher or equal to the voltage of the Digital power supply (DVDD). 1.4 - Digital Ground (DGND) This pin is the ground for DAC and ADC internal digital circuitry. Notes : 1. To obtain published performance, the analog VDD and Digital VDD should be decoupled with respect to Analog Ground and Digital Ground, respectively. The decoupling is intended to isolate digital noise from the analog section ; decoupling capacitors should be as close as possible to the respective analog and digital supply pins. 2. All the ground pins must be tied together. In the following section, the ground and supply pins are referred to as GND and VDD, respectively. 3/17 STLC7550 PIN DESCRIPTION (continued) 2 - HOST INTERFACE (10 pins) 2.1 - Data In (DIN) In Data Mode, the data word is the input of the DAC channel. In software, the data word is followed by the control register word. 2.2 - Data Out (DOUT) In Data Mode, the data word is the ADC conversion result. In software, the data word is followed by the register read. 2.3 - Frame Synchronization (FS) In master mode, the frame synchronization signal is used to indicate that the device is ready to send and receive data. The data transfer begins on the falling edge of the frame-sync signal. The framesync is generated internally and goes low on the rising edge of SCLK in master mode. In slave mode the frame is generated externally. 2.4 - Serial Bit Clock (SCLK) SCLK clocks the digital data into DIN and out of DOUT during the frame synchronization interval. The Serial bit clock is generated internally. 2.5 - Reset Function (RESET) The reset function is to initialize the internal counters and control register. A minimum low pulse of 100ns is required to reset the chip. This reset function initiates the serial data communications. The reset function will initialize all the registers to their default value and will put the device in a pre-programmed state. After a low-going pulse on RESET, the device registers will be initialized to provide an over-sampling ratio equal to 160, the serial interface will be in data mode, the DAC attenuation will be set to infinite, the ADC gain will be set to 0dB, the Differential input mode on the ADC converter will be selected, and the multiplexor will be set on the main inputs IN+ and IN-. After a reset condition, the first frame synchronization corresponds to the primary channel. 2.6 - Power Down (PWRDWN) The Power-Down input powers down the entire chip (< 50µW). When PWRDWN Pin is taken low, the device powers down such that the existing internally programmed state is maintained. When 4/17 PWRDWN is driven high, full operation resumes after 1ms. If the PWRDWN input is not used, it should be tied to VDD. 2.7 - Hardware Control (HC0, HC1) These two pins are used for Hardware/Software Control of the device. The data on HC0 and HC1 will be latched on to the device on the rising edge of the Frame Synchronization Pulse. If these two pins are low, Software Control Mode is selected. When in Software Control Mode, the LSB of the 16-bit word will select the Data Mode (LSB = 0) or the Control Mode (LSB = 1). Other combinations of HC0/HC1 are for Hardware Control. These inputs should be tied low if not used. 2.8 - Master/Slave Control (M/S) When M/S is high, the device is in master mode and Fs is generated internally. When M/S is low, the device is in slave mode and Fs must be generated externally. 2.9 - Master Clock Mode (MCM) When MCM is high, XTALIN is provided externally and must be equal to 36.864MHz. When MCM is low, XTALIN is provided externally and must be equal to oversampling frequency : Fs x Over (see Clock Block Diagram and §4 Modes of Operation). 2.10 - Timeslot Control (TS) When TS = 0 the data are assigned to the first 16 bits after falling edge of FS (7546 mode) otherwise the data are bits 17 to 32. The case M/S = 1 with TS = 1 is reserved for life-test (transmit gain fixed to 0dB). 3 - CLOCK SIGNALS (2 pins) Depending on MCM value, these pins have different function. 3.1 - MCM = 1 (XTALIN, XTALOUT) These pins must be tied to external crystal. For the value of crystal see Functional Description Chapter Part 3. 3.2 - MCM = 0 (MCLK, XTALOUT) MCLK Pin must be connected to an external clock. XTALOUT is not used. STLC7550 PIN DESCRIPTION (continued) 4 - ANALOG INTERFACE (9 pins) 4.1 - DAC and ADC Positive Reference Voltage Output (VREFP) This pin provides the Positive Reference Voltage used by the 16-bit converters. The reference voltage, VREF, is the voltage difference between the VREFP and VREFN outputs, and its nominal value is 1.25V. VREFP should be externally decoupled with respect to VCM. 4.2 - DAC and ADC Negative Reference Voltage Output (VREFN) This pin provides the Negative Reference Voltage used by the 16-bit converters, and should be externally decoupled with respect to VCM. 4.3 - Common Mode Voltage Output (VCM) This output pin is the common mode voltage (AVDD - AGND)/2. This output must be decoupled with respect to GND. 4.4 - Non-inverting Smoothing Filter Output(OUT+) This pin is the non-inverting output of the fully differential analog smoothing filter. 4.5 - Inverting Smoothing Filter Output (OUT-) This pin is the inverting output of the fully differential analog smoothing filter. Outputs OUT+ and OUTprovide analog signals with maximum peak-topeak amplitude 2 x VREF, and must be followed by an external two pole smoothing filter. The external filter follows the internal single pole switch capaci- tor filter. The cutoff frequency of the external filter must be greater than two times the sampling frequency (FS), so that the combined frequency response of both the internal and external filters is flat in the passband . The attenuator of the last output stage can be programmed to 0dB, 6dB or infinite. 4.6 - Non-inverting Analog Input (IN+) This pin is the differential non-inverting ADC input. 4.7 - Inverting Analog Input (IN-) This pin is the differential inverting ADC input. These analog inputs (IN+, IN-) are presented to the Sigma-Delta modulator. The analog input peak-topeak differential signal range must be less than 2 x VREF, and must be preceded by an external single pole anti-aliasing filter. The cut-off frequency of the filter must be lower than one half the oversampling frequency. These filters should be set as close as possible to the IN+ and IN- pins. The gain of the first stage is programmable (see Table 3). 4.8 - Non-inverting Auxiliary Analog Input (AUX IN+) This pin is the differential non-inverting auxiliary ADC input. The characteristics are same as the IN+ input. 4.9 - Inverting Auxiliary Analog Input (AUX IN-) This pin is the differential inverting auxiliary ADC input. The characteristics are same as the IN- input. The input pair (IN+/IN- or AUX IN+/AUX IN-) are software selectable. BLOCK DIAGRAM (TQFP44) HC0 HC1 15 14 28 AUXIN+ 25 ANALOG MODULATOR LOW-PASS (0.425 x sampling frequency) MUX AUXIN- 26 (0 + 6dB in diff. input) OUT+ OUT- DAC 1 BIT 36 ATTEN. 0dB/+6dB/ INFINITE 37 VREFP 18 VREFN 19 VCM 30 First order differential switched capacitor filter LOW-PASS (0.425 x sampling frequency) 2nd ORDER MODULATOR 7 MCM 42 DOUT 41 DIN 40 TSTD1 39 TS 17 M/S 4 FS 3 SCLK CLOCK GENERATOR 29 AVDD 20 31 AGND1 AGND2 8 9 XTALOUT XTALIN 5 6 38 16 DVDD DGND RESET PWRDWN STLC7550 7550-02.EPS 27 IN- SERIAL PORTS AND CONTROL REGISTER IN+ 5/17 STLC7550 FUNCTIONAL DESCRIPTION 1 - TRANSMIT D/A SECTION The functions included in the Tx D/A section are detailed hereafter. 16-bit 2’s complement data format is used in the DAC channel. 1.1 - Transmit Low Pass Filters The transmit low pass filter is basically an interpolating filter including a sinx/x correction. It is a combination of Finite Impulse Response filter (FIR) and an Infinite Impulse Response filter (IIR). The digital signal from the serial interface gets interpolated by 2, 3, 4, 5 or 6 x Sampling Frequency (FS) through the IIR filter. The signal is further interpolated by 32 x FS x n (with n equal to 2, 3, 4, 5, 6) through the IIR and FIR filter. The low pass filter is followed by the DAC. The DAC is oversampled at 64, 96, 128, 160, 192 x FS. The oversampling ratio is user selectable. 1.2 - D/A Converter The oversampled D/A converter includes a second order digital noise shaper, a one bit D/A converter and a single pole analog low-pass filter. The attenuation of the last output stage can be programmed to 0dB, +6dB or infinite. The cut-off frequency of the single pole switch-capacitor lowpass filter is : fc−3dB = OCLK 2 ⋅ π ⋅ 10 with OCLK = Oversampling Clock frequency. Continuous-time filtering of the analog differential output is necessary using an off-chip amplifier and a few external passive components. At least 79dB signal to noise plus distortion ratio can be obtained in the frequency band of 0.425 x 9.6kHz (with an oversampling ratio equal to 160). 2 - RECEIVE A/D SECTION The different functions included in the ADC channel section are described below. 16-bit 2’s complement data format is used in the ADC. 2.1 - A/D Converter The oversampled A/D converter is based on a second order sigma-delta modulator. To produce excellent common-mode rejection of unwanted signals, the analog signal is processed differentially until it is converted to digital data. Single-ended mode can also be used. The ADC is oversampled at 64, 96, 128, 160 or 192 x FS. The oversampling ratio is user selectable. At least -85dB SNDR can be expected in the 0.425 x 9.6kHz bandwidth with a -6dBr differential input signal and an oversampling ratio equal to 160. 6/17 2.2 - Receive Low Pass Filter It is a decimation filter. The decimation is performed by two decimation digital filters : one decimation FIR filter and one decimation IIR filter. The purpose of the FIR filter is to decimate 32 times the digital signal coming from the ADC modulator. The IIR is a cascade of 5 biquads. It provides the low-pass filtering needed to remove the noise remaining above half the sampling frequency. The output of the IIR will be processed by the DSP. 3 - CLOCK GENERATOR The master clock, MCLK is provided by the user thanks to a crystal or external clock generator (see Figure 1). The MCLK could be equal to 36.864MHz (MCM = 1). In that case thanks to the divider M x Q, the STLC7550 is able to generate all V.34bis and 56 Kbps sampling frequencies (see Table 1). When MCM = 0, the MCLK must be equal to the oversampling frequency : Fs x OVER (7546 mode). The ADC and DAC are oversampled at the OCLK frequency. OCLK is equal to the shift clock used in the serial interface. The MCLK frequency should be : MCLK = K x Sampling frequency Combination of M, Q and oversampling ratios allows to generate several sampling frequencies. Recommended values for classical modem applications are as follow : Table 1 : Sampling Frequencies Generation FQ = FQ = FQ = F 36.864MHz (1) 18.432MHz 9.216MHz (kHz) M Q over M Q over M Q over 16.00 3 6 128 2 4.5 128 1 6 96 13.96 3 5.5 160 13.71 3 7 128 1 7 192 1 7 96 12.80 3 6 160 2 4.5 160 1 4.5 160 12.00 3 8 128 2 6 128 1 6 128 11.82 3 6.5 160 10.97 3 7 160 10.47 4 5.5 160 2 5.5 160 1 5.5 160 10.29 4 7 128 2 7 128 1 7 128 9.60 4 6 160 2 6 160 1 6 160 9.00 4 8 128 2 8 128 1 8 128 8.86 4 6.5 160 2 6.5 160 1 6.5 160 8.23 4 7 160 2 7 160 1 7 160 8.00 4 6 192 2 6 192 1 6 192 7.20 4 8 160 2 8 160 1 8 160 Note : 1. Recommended value. STLC7550 FUNCTIONAL DESCRIPTION (continued) Figure 1 : Clock Block Diagram XTALIN (MCLK) XTALOUT SCLK MCM (OCLK) M/S Sync VDD ÷M ÷Q % OVER 7550-03.EPS FS Internal Sampling Bit 3-4-5 Cont. Reg. : Bit 8-9-10-11-12-13 The configuration 4 is equivalent to configuration 3 but the Fs is generated and phase controlled by the processor. 4 - MODES OF OPERATION Thanks to MCM and M/S programmation pins we can get the following configuration. Figure 3 : Configuration 2 Configuration 1 : MCM = 1, M/S = 1 The STLC7550 is in master mode and we have : Fs = XTAL IN / (M x Q x OVER) Fs and SCLK are output pins. fQ = 36.864MHz Figure 2 : Configuration 1 XTALIN BCLK XTALIN FS DO DIN DI PROCESSOR DOUT DO DIN DI M/S VDD MCM VDD PROCESSOR M/S MCM TS DOUT GND VDD GND STLC7550 Figure 4 : Configuration 3 (7546 mode) TS GND STLC7550 Configuration 2 : MCM = 1, M/S = 0 The STLC7550 is in slave mode. SCLK is provided by the STLC7550, the processor generates the Fs and controls the phase of the sampling frequency. Fs must be the result of a division of a number of cycles of SLCK (Fs = SCLK % OVER). Configuration 3 : MCM = 0, M/S = 1 The STLC7550 is in master mode and the processor provides the XTAL IN = MCLK = OCLK. The STLC7550 generates the Fs from OCLK. In this mode the configuration 3 is equivalent to the STLC7546 mode. Configuration 4 : MCM = 0, M/S = 0 The STLC7550 is in slave mode. fQ = K x Fs XTALIN BCLK SCLK FS FS DO DIN DI PROCESSOR DOUT M/S VDD MCM GND TS GND STLC7550 Configuration 5 : MCM = 1, M/S = 1 (master codec) MCM = 0, M/S = 0 (slave codec) This is dual codec application. The master codec has his data in timeslot 0 and the slave codec has his data in timeslot 1 thanks to the programmation of TS. 7/17 7550-06.EPS SCLK FS FS 7550-04.EPS BCLK SCLK FS 7550-05.EPS fQ = 36.864MHz STLC7550 FUNCTIONAL DESCRIPTION (continued) Figure 5 : Configuration 4 fQ = K x Fs BCLK SCLK FS FS DO DIN DI PROCESSOR M/S GND MCM GND TS GND DOUT STLC7550 7550-07.EPS XTALIN Figure 6 : Configuration 5 fQ = 36.864MHz XTALIN PROCESSOR BCLK SCLK FS FS DO DIN DI DOUT M/S VDD MCM VDD TS GND STLC7550 HC0 HC1 HC0 HC1 XTAKIN VDD TS M/S GND FS MCM GND DOUT STLC7550 8/17 7550-08.EPS DIN STLC7550 FUNCTIONAL DESCRIPTION (continued) 5 - HOST INTERFACE The data to the device, input/output are MSB-first in 2’s complement format (see Table 2). The Host interface consist of the shift clock, the frame synchronization signal, the ADCchannel data output, and the DAC-channel data input. When Control Mode is selected, the device will internally generate an additional Frame Synchronization Pulse (Secondary Frame Synchronization Pulse) at the midpoint of the original Frame Period. If the device is in slave mode the additional frame sync (secondary frame sync pulse) must be generated by the processor. The Original Frame Synchronization Pulse will also be referred to as the Primary Frame Synchronization Pulse. Two modes of serial transfer are available : - First : Software mode for 15-bit transmit data transfer and 16-bit receive data transfer - Second : hardware mode for 16-bit data transfer. Both modes are selected by the Hardware Control pins (HC0, HC1). Table 2 : Mode Selection HC1 HC0 LSB 0 0 0 1 0 0 1 X 0 1 X X Secondary FSYNC 15bits No 15bits (+16bits reg.) Yes 16bits No 16bits (+16bits reg.) Yes Useful Data Description Software Mode for Data Transfer only. Software Mode for Data Transfer + Control Register Transfer. Hardware Mode for Data Transfer only. Hardware Mode for Data Transfer + Control Register Transfer. Figure 7 : Data Mode Sampling period FS SCLK - - D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 - - - D15 D14 TxDO - - D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 - - - D15 D14 7550-09.EPS TxDI 00 or 01 HC1, HC0 Figure 8 : Mixed Mode Sampling Period 1/2 Sampling Period (see Note) FS TxDI Data Word Input Control Word TxDO Data Word Output Register Word HC1, HC0 1X 01 Note : In slave mode, this 1/2 Sampling Period is not mandatory. If 1/2 Sampling Period is not provided, one sample is lost. 9/17 7550-10.EPS SCLK STLC7550 FUNCTIONAL DESCRIPTION (continued) 6 - CONTROL REGISTER This section defines the control and device status information. The register programming occurs only during Secondary Frame Synchronization. After a reset condition, the device is always in data mode. Table 3 : Bits Assignment Bits Name 0 - 1 2 Function Reset Value - 0 D1 Aux/Main Input 0 D2 Receive Gain 0 3 D3 Oversampling bit 0 0 4 D4 Oversampling bit 1 0 5 D5 Oversampling bit 2 0 6 D6 Attenuator transmit bit 0 0 7 D7 Attenuator transmit bit1 0 8 M M Divider 1 9 Q0 Q0 Divider 1 10 Q1 Q1 Divider 0 11 Q2 Q2 Divider 0 12 T0 M Divider and Test mode bit 0 0 13 T1 M Divider and Test mode bit 1 0 14 TEST2 Test mode bit 2 0 15 TEST3 Test mode bit 3 0 Table 4 : Aux/Main Input D1 Function 0 Main Receive Input 1 Auxiliary Receive Input Table 5 : Receive Gain D2 Function DIFFERENTIAL INPUT 0 0dB gain (commun mode fixed) 1 +6dB gain (commun mode non-fixed) SINGLE ENDED (one input used, other at VCM) 0 -6dB gain (see Note 1) 1 0dB gain Note 1 : Not recommended case. Performances could be reduced. 10/17 Table 6 : Oversampling Ratio D5 0 0 0 0 1 1 1 1 D4 0 0 1 1 0 0 1 1 D3 0 1 0 1 0 1 0 1 Function 160 192 Reserved Reserved Reserved 64 96 128 Table 7 : Transmit Attenuation D7 0 0 1 1 D6 0 1 0 1 Function Infinite Reserved -6dB 0dB Table 8 : Q Divider Clock Generator D11 0 0 0 0 1 1 1 1 D10 0 0 1 1 0 0 1 1 D9 0 1 0 1 0 1 0 1 Function Q divider = 5 Q divider = 6 Q divider = 7 Q divider = 8 Q divider = 4.5 Q divider = 5.5 Q divider = 6.5 Q divider = 7.5 Table 9 : M Divider Clock Generator D13 0 0 0 1 1 1 D12 0 0 1 0 1 1 D8 0 1 X X 0 1 Function M divider = 3 M divider = 4 Reserved Reserved M divider = 1 M divider = 2 Table 10 : Reserved Mode D15 X D14 X Function Reserved for test This two bits must be set to 0 for normal operation. STLC7550 ELECTRICAL SPECIFICATIONS Unless otherwise noted, Electrical Characteristics are specified over the operating range. Typical values are given for VDD = 3V, Tamb = 25°C and for nominal Master clock frequency MCLK = 1.536MHz and oversampling ratio = 160. Absolute Maximum Ratings (referenced to GND) Symbol VDD VI,VIN II,IIN IO IOUT Toper Tstg PDMAX ESD Parameter DC Supply Voltage Digital or Analog Input Voltage Digital or Analog Input Current Digital Output Current Analog Output Current Operating Temperature Storage Temperature Maximum Power Dissipation Electrostatic Discharge Value -0.3, 7.0 -0.3, VDD+0.3 ±1 ±20 ±10 0, 70 -40, 125 200 2000 Unit V V mA mA mA °C °C mW V Nominal DC Characteristics (VDD = 3V ± 5%, GND = 0V, TA = 0 to 70°C unless otherwise specified) Symbol VDD Parameter Supply Voltage Range Min. 2.70 Typ. 3 VDD/2-5% 6 4 1 200 VDD/2 Max. 5.5 Unit V 10 mA mA µA µA V POWER SUPPLY AND COMMON MODE VOLTAGE SINGLE POWER SUPPLY (DVDD = AVDD) IDDA Analog Supply Current Digital Supply Current IDDD IDD-LP Supply Current in Low Power Mode VCM MCLK Stopped MCLK Running Output Common Mode Voltage VCM Output Voltage Load Current (see Note 1) VDD/2+5% DIGITAL INTERFACE VIL VIH II VOH VOL Low Level Input Voltage High Level Input Voltage Input Current VI = VDD or VI = GND High Level Output Voltage (ILOAD = -600µA) Low Level Output Voltage (ILOAD = 800µA) -0.3 DVDD-0.5 -10 DVDD-0.5 0.5 ±1 0.3 V V µA V V 1.35 V 10 ANALOG INTERFACE Differential Reference Voltage Output VREF = (VREFP - VREFN) Tempco (VREF) VREF Temperature Coefficient Input Common Mode Offset Voltage = [(IN+)+(IN-)]/2 -VCM VCMO IN VDIF IN Differential Input Voltage : [(IN+)-(IN-)] ≤ 2 x VREF Differential Input DC Offset Voltage VOFF IN VCMO OUT Output Common Mode Voltage Offset : (OUT+ + OUT-)/2 - VCM (see Note 1) VDIF OUT Differential Output Voltage : OUT+ - OUT- ≤ 2 x VREF Differential Output DC Offset Voltage : (OUT+ - OUT-) (0000x) VOFF OUT RIN Input Resistance IN+, IN- (id. AUX IN) ROUT Output Resistance (OUT+, OUT-) RL Load Resistance (OUT+, OUT-) CL Load Capacitance (OUT+, OUT-) Output A/D Modulator Voltage Offset : IN+ = IN- = VCM VADO OUT VREF 1.15 1.25 200 -100 100 2 x VREF -100 -20 100 20 2 x VREF -100 100 100 50 10 -1000 20 +1000 ppm/°C mV Vpp mV mV V mV kΩ Ω kΩ pF LSB Note : 1. Device is very sensitive to noise on VCM Pin. VCM output voltage load current must be DC (<10µA). in order to drive dynamic load, VCM must be buffered. AC variation in VCM current magnitude decrease A/D and D/A performance. 11/17 STLC7550 ELECTRICAL SPECIFICATIONS (continued) Nominal AC Electrical Characteristics (Reference level VIL = 0.5V, VIH = DVDD - 0.5V, VOL = 0.3V, VOH = DVDD - 0.5V, DVDD = 3V, Output load = 50pF unless otherwise) Symbol N° Parameter Min. Typ. Max. Unit SERIAL CHANNEL TIMING (see Figure 9 for Parameter numbers) 1 2 3 4 5 6 7 8 9 10 11 12 SCLK Period SCLK Width Low SCLK Width High SCLK Rise Time SCLK Fall Time FS Setup FS Hold DIN Setup DIN Hold DOUT Valid HC0,HC1 Set-up 300 150 150 50 ns ns ns ns ns ns ns ns ns ns ns ns 2.8 55 MHz % 10 10 100 100 50 0 20 20 0 MASTER CLOCK INTERFACE (MCLK) (MCM = 0) MCLK Master Clock Input Master Clock Duty Cycle 0.92 45 1.54 Figure 9 : Serial Interface Timing Diagram 1 12 2.4 3 5 SCLK 6 7 FS 8 DIN 9 MSB 10 DOUT 11 HC0 12/17 7550-11.EPS MSB STLC7550 ELECTRICAL SPECIFICATIONS (continued) Transmit Characteristics Performance of the Tx channel Typical values are given for AVDD = 3V, Tamb = 25°C and for nominal master clock MCLK = 1.536MHz, differential mode and oversampling ratio = 160. Measurement band = 100Hz to 0.425 x Sampling frequency. Symbol Parameter Gabs Absolute Gain at 1kHz Ripple Ripple in Band : 0 to 0.425 x FS Min. -0.5 Max. 0 0.5 Unit dB ±0.2 dB -92 dB THD Total Harmonic Distortion (differential Tx signal : VOUT = 1.25VPP, f = 1kHz) DR Dynamic Range (f = 1kHz) (measured over the full 0 to FS/2 with a -20dBr output signal and extrapolated to full scale) (see Note 2) 87 dB Crosstalk (transmit channel to receive channel) 85 dB CRxTx -85 Typ. Smoothing filter transfer characteristics The cut-off frequency of the single pole switch-capacitor low-pass filter following the DAC is : n ⋅ 32 ⋅ FS fc−3dB = with n = 2, 3, 4, 5, 6 (see paragraph Functional Description 1.2). 2 ⋅ π ⋅ 10 Receive Characteristics Performance of the Rx channel Typical values are given for AVDD =3V, Tamb = 25°C and for nominal master clock MCLK = 1.536MHz, differential mode and oversampling ratio = 160. Measurement band = 100Hz to 0.425 x Sampling Frequency. Symbol Parameter Min. -0.5 Typ. Max. 0 0.5 Unit Gabs Absolute Gain at 1kHz Ripple Ripple in Band : 0 to 0.425 x FS ±0.2 dB dB THD Total Harmonic Distortion (differential Rx signal : VIN = 1.25VPP, f = 1kHz) -92 dB DR Dynamic Range (f = 1kHz) (measured over the full 0 to FS/2 with a -20dBr input and extrapolated to full scale) (see Note 2) 87 dB PSRR Power Supply Rejection Ratio (f = 1kHz, VAC = 200mVPP) 50 dB CTxRx Crosstalk (transmit channel to receive channel) 85 dB DR − 1.76 Note 2 : The dynamic range can be measured in bit with : Nbit = with DR in dB. 6.02 13/17 STLC7550 TYPICAL APPLICATION Line Interface - Differential Duplexor Figure 10 22kW 100pF 13.2kW C : Improve the low frequency response. Its value depends on the transformer inductance. C' : Reduces the DC offset gain. Z0 : Nominal line impedance 22kW Z0/2 OUT+ C VCM 680pF 13.2kW 2R Z0/2 22kW Phone Line OUTC 22kW 100pF 2R R 1.2kW IN+ R' 2.2nF VCM r 2.2nF C' IN- R All capacitor, resistor and impedance values are provided for indication only. These values must be readjusted according to line transformer characteristics and also telecommunication regulations in force in individual countries. Refer to Application Note AN930 for more detailed information. Contact your local representative. 14/17 7550-12.EPS R' 1.2kW STLC7550 DEFINITION AND TERMINOLOGY Data Transfer Interval Signal Data Data Mode Control Mode Frame Sync. Frame Sync and Sampling Period ADC Channel DAC Channel OverSampling Ratio Resolution Dynamic Range Signal-to-(Noise+Distortion) Crosstalk Power Supply Rejection Ratio The time during which data is transfered from DOUT and to DIN. This interval is 16 shift clocks provides by the chip. This refers to the input signal and all the converted representations through the ADC channel and the DAC channel. This refers to the data transfer. Since the device is synchronous, the signal data words from the ADC channel and to the DAC channel occur simultaneously. This refers to the digital control data transfer into DIN and the register read data from DOUT. The control mode interval occurs when requested by hardware or software. Frame sync refers only to the falling edge of the signal which initiates the data transfer interval. The primary frame sync starts the Data Mode and the secondary frame sync starts the Control Mode. The time between falling edges of successive primary frame sync signals. This term refers to all signal processing circuits between the analog input and the digital conversion result at DOUT. This term refers to all signal processing circuits between the digital data word applied to DIN and the differential output analog signal available at OUT+ and OUT- pins. This term refer to the ratio between the master clock MCLK corresponding to the oversampling frequency and the sampling frequency FS. The number of bits in the input words to the DAC, and the output words in the ADC. The S/(N+D) with a 1kHz, -20dBr input signal and extrapolated to full scale. Use of a small input signal reduces the harmonic distortion components of the noise to insignificance. Units in dB or in Nbit as explained before. S/(THD+N) is the ratio of the rms of the input signal to the rms of all other spectral components within the measurement bandwidth (0.425 x Sampling Frequency). Units in dB. The amount of 1kHz signal present on the output of the grounded input channel with 1kHz 0dB signal present on the other channel. Units in dB. PSRR. The amount of 1kHz signal present on the output of the grounded input channel with 1kHz 200mVPP signal present on the power supply. 15/17 STLC7550 PACKAGE MECHANICAL DATA (continued) 44 PINS - PLASTIC QUAD FLAT PACK (THIN) A A2 e 44 A1 34 33 11 23 E3 E1 E B 1 0,10 mm .004 inch SEATING PLANE c Dimensions A A1 A2 B C D D1 D3 e E E1 E3 L L1 K 16/17 Min. 0.05 1.35 0.30 0.09 0.45 Millimeters Typ. 1.40 0.37 12.00 10.00 8.00 0.80 12.00 10.00 8.00 0.60 1.00 Max. 1.60 0.15 1.45 0.40 0.20 0.75 Min. 0.002 0.053 0.012 0.004 0.018 0o (Min.), 7o (Max.) PM-4Y.EPS K 0,25 mm .010 inch GAGE PLANE Inches Typ. 0.055 0.015 0.472 0.394 0.315 0.031 0.472 0.394 0.315 0.024 0.039 Max. 0.063 0.006 0.057 0.016 0.008 0.030 4Y.TBL 22 L D3 D1 D L1 12 STLC7550 PACKAGE MECHANICAL DATA (continued) 48 PINS - PLASTIC QUAD FLAT PACK (THIN) A A2 e 48 A1 37 36 12 25 E3 E1 E B 1 0,10 mm .004 inch SEATING PLANE c 24 Dimensions A A1 A2 B C D D1 D3 e E E1 E3 L L1 K Min. 0.05 1.35 0.17 0.09 0.45 Millimeters Typ. 1.40 0.22 9.00 7.00 5.50 0.50 9.00 7.00 5.50 0.60 1.00 Max. 1.60 0.15 1.45 0.27 0.20 0.75 Min. 0.002 0.053 0.007 0.004 0.018 PM-5B.EPS K 0,25 mm .010 inch GAGE PLANE Inches Typ. 0.055 0.009 0.354 0.276 0.216 0.0197 0.354 0.276 0.216 0.024 0.039 Max. 0.063 0.006 0.057 0.011 0.008 0.030 5B.TBL L D3 D1 D L1 13 0o (Min.), 7o (Max.) Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No licence is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics © 1998 STMicroelectronics - All Rights Reserved Purchase of I2C Components of STMicroelectronics, conveys a license under the Philips I2C Patent. Rights to use these components in a I2C system, is granted provided that the system conforms to the I2C Standard Specifications as defined by Philips. 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