STLVDS385 +3.3V PROGRAMMABLE LVDS TRANSMITTER 24-BIT FLAT PANEL DISPLAY (FPD) LINK-85MHZ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 20 TO 85 MHz SHIFT CLOCK SUPPORT BEST–IN–CLASS SET & HOLD TIMES ON TxINPUTs Tx POWER CONSUMPTION <130 mW (typ) @85MHz GRAYSCALE Tx POWER-DOWN MODE <200µW (max) SUPPORTS VGA, SVGA, XGA aND SINGLE/ DUAL PIXEL SXGA. NARROW BUS REDUCES CABLE SIZE AND COST UP TO 2.38 Gbps THROUGHPUT UP TO 297.5 Megabytes/sec BANDWIDTH 345 mV (typ) SWING LVDS DEVICES FOR LOW EMI PLL REQUIRES NO EXTERNAL COMPONENTS COMPATIBLE WITH TIA/EIA -644 LVDS STANDARD DESCRIPTION The STLVDS385 transmitter converts 28 bits of LVCMOS/LVTTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS TSSOP56 link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. At a transmit clock frequency of 85 MHz, 24 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 595 Mbps per LVDS data channel. Using a 85 MHz clock, the data throughput is 297.5 Mbytes/sec. The transmitter can be programmed for Rising edge strobe or Falling edge strobe through a dedicated pin. A Rising edge or Falling edge strobe transmitter will inter operate with a Falling edge strobe Receiver without any translation logic. ORDERING CODES Type Temperature Range Package Comments STLVDS385BTR -10 to 70°C TSSOP56 (Tape & Reel) 2000 parts per reel February 2004 1/14 STLVDS385 PIN CONFIGURATION PIN DESCRIPTION PlN N° SYMBOL 1, 9, 26 VCC Power Supply pins for TTL Inputs TXIN TTL level input. This includes: 8 Red, 8 Green, 8 Blue and 4 control linesFPLINE, FPFRAME, and DRDY (also referred to as HSYNC, VSYNC, Data Enable) 2, 3, 4, 6, 7, 8, 10, 11, 12, 14, 15, 16, 18, 19, 20, 22, 23, 24, 25, 27, 28, 30, 50, 51, 52, 54, 55, 56 5, 13, 21, 29 17 31 GND R_FB TxCLKIN 32 PWRDWN 33, 35 PLL GND PLL VCC 34 36, 43, 49 37, 41, 45, 47 38, 42, 46, 48 39 40 44 2/14 LVDS GND TxOUT+ TxOUTTxCLK OUT+ TxCLK OUTLVDS VCC NAME AND FUNCTION Ground pins for TTL Inputs Programmable strobe select (See Table 1) TTL level clock input. Pin name TxCLK IN TTL level input. When asserted (low input) TRI-STATES the outputs, ensuring low current at power down Ground pins for PLL Power Supply pin for PLL Ground pins for LVDS outputs Positive LVDS differential data output Negative LVDS differential data output Positive LVDS differential clock output Negative LVDS differential clock output Power Supply pin for LVDS outputs STLVDS385 TABLE 1 PROGRAMMABLE TRANSMITTER PlN CONDITION STROBE STATUS R_FB R_FB = VCC Rising edge strobe R_FB R_FB = GND or NC Falling edge strobe ABSOLUTE MAXIMUM RATINGS Symbol VCC VI Parameter Supply Voltage -0.3 to 4 V -0.5 to (VCC + 0.3) V -0.3 to (VCC + 0.3) V VDO LVDS Driver Output Voltage LVDS Output Short Circuit Duration ESD HBM EIAJ Latch Up Tolerance TJ Tstg Unit CMOS/TTL Input Voltage IOSD ILATCH Value Continuous Junction Temperature Storage Temperature Range 7 500 KV V ± 300 mA +150 °C -65 to +150 °C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied. RECOMMENDED OPERATING CONDITIONS Symbol VCC TA ∆VCC fTxCLKIN Parameter Supply Voltage Operating Free Air Temperature Min. Typ. Max. Unit 3.0 3.3 3.6 V 0 Supply Noise Voltage TxCLKIN frequency 20 70 °C 100 mVPP 85 MHz RECOMMENDED TRANSMITTER INPUT CHARACTERISTICS (VCC = 3.3V, TJ = -10 to 70°C unless otherwise noted. Typical values are referred to TA = 25°C) Symbol Parameter Min. Typ. Max. Unit tCIT TxCLK IN Transition Time (Fig. 5) 1.0 6.0 ns tCIP TxCLK IN Period (Fig. 6) 11.76 T 50 ns tCIH TxCLK IN High Time (Fig. 6) 0.35T 0.5T 0.65T ns tCIL TxCLK IN Low Time (Fig. 6) 0.35T 0.5T 0.65T ns tXIT TxIN Transition Time 6.0 ns 1.5 ELECTRICAL CHARACTERISTICS LVCMOS/LVTTL DC SPECIFICATIONS (VCC = 3.3V, TJ = -10 to 70°C unless otherwise noted. Typical values are referred to TA = 25°C) Symbol Parameter Test Conditions VIH High Level Input Voltage VIL Low Level Input Voltage VCL Input Clamp Voltage ICL = -18mA Input Current VI =0.4 V, 2.5 or VCC II Min. Typ. 2.0 GND VI = GND -0.79 Max. Unit VCC mV 0.8 mV -1.5 V 10 -10 0 µA µA 3/14 STLVDS385 LVDS DC SPECIFICATIONS (VCC = 3.3V, TJ = -10 to 70°C unless otherwise noted. Typical values are referred to TA = 25°C) Symbol VOD ∆VOD VOS ∆VOS Parameter Test Conditions Differential Output Voltage RL = 100Ω Change in VOD between Complimentary Output States Offset Voltage (Note 2) RL = 100Ω RL = 100Ω IOS Change in VOS between RL = 100Ω Complimentary Output States Output Short Circuit Current VO = 0, IOZ Output Tri-State Current Min. Typ. Max. 250 345 450 mV 35 mV 1.125 RL = 100Ω POWERDOWN = 0, VO = 0 or VCC 1.25 Unit 1.375 V 35 mV -3.5 -5 mA ±1 ±10 µA TRANSMITTER SUPPLY CURRENT (VCC = 3.3V, TJ = -10 to 70°C unless otherwise noted. Typical values are referred to TA = 25°C) Symbol Parameter ICCTW Transmitter Supply Current Worst Case RL = 100Ω, CL = 5pF, Worst Case Pattern (Fig. 1, 3) ICCTG Transmitter Supply Current 16 Grayscale RL = 100Ω, CL = 5pF, 16 Grayscale Pattern (Fig. 1, 3) ICCTZ Transmitter Supply Current Power Down Powerdown = Low Driver Outputs in Tri-State under Power Down Mode 4/14 Test Conditions f = 32.5 MHz f = 40 MHz f = 65 MHz f = 85 MHz f = 32.5 MHz f = 40 MHz f = 65 MHz f = 85 MHz Min. Typ. Max. Unit 31 32 37 42 29 30 35 39 10 45 50 55 60 38 40 45 50 55 mA mA µA STLVDS385 TRANSMITTER SWITCHING CHARACTERISTICS (VCC = 3.3V, TJ = -10 to 70°C unless otherwise noted. Typical values are referred to TA = 25°C) Symbol Parameter Test Conditions Min. Typ. Max. Unit 0.75 1.5 ns tLLHT LVDS Low-to-High Transition Time (Fig. 4) tLLLT LVDS High-to-Low Transition Time (Fig. 4) tTPP0 tTPP1 Transmitter Output Pulse Position for BIT 0 (Fig.11 - Note 3) Transmitter Output Pulse Position for BIT 1 tTPP2 Transmitter Output Pulse Position for BIT 2 6.89 tTPP3 Transmitter Output Pulse Position for BIT 3 10.46 tTPP4 Transmitter Output Pulse Position for BIT 4 14.04 14.29 14.54 ns tTPP5 Transmitter Output Pulse Position for BIT 5 17.61 17.86 18.11 ns tTPP6 Transmitter Output Pulse Position for BIT 6 21.18 21.43 21.68 ns tTPP0 -0.20 0 0.20 ns tTPP1 Transmitter Output Pulse Position for BIT 0 (Fig.11 - Note 3) Transmitter Output Pulse Position for BIT 1 2.00 2.20 2.40 ns tTPP2 Transmitter Output Pulse Position for BIT 2 4.20 4.40 4.60 ns tTPP3 Transmitter Output Pulse Position for BIT 3 6.39 6.59 6.79 ns tTPP4 Transmitter Output Pulse Position for BIT 4 8.59 8.79 8.99 ns tTPP5 Transmitter Output Pulse Position for BIT 5 10.79 10.99 11.19 ns tTPP6 Transmitter Output Pulse Position for BIT 6 12.99 13.19 13.99 ns tTPP0 -0.20 0 0.20 ns tTPP1 Transmitter Output Pulse Position for BIT 0 (Fig.11 - Note 3) Transmitter Output Pulse Position for BIT 1 1.48 1.68 1.88 ns tTPP2 Transmitter Output Pulse Position for BIT 2 3.16 3.36 3.56 ns tTPP3 Transmitter Output Pulse Position for BIT 3 4.84 5.04 5.24 ns tTPP4 Transmitter Output Pulse Position for BIT 4 6.52 6.72 6.92 ns tTPP5 Transmitter Output Pulse Position for BIT 5 8.20 8.40 8.60 ns tTPP6 Transmitter Output Pulse Position for BIT 6 9.88 10.08 10.28 ns f = 40 MHz f = 65 MHz f = 85 MHz 0.75 1.5 ns -0.25 0 0.25 ns 3.32 3.57 3.82 ns 7.14 7.39 ns 10.71 10.96 ns tSTC TxIN Setup to TxCLK IN (Fig. 6) 2.5 ns tHTC TxIN Hold to TxCLK IN (Fig. 6) 0 ns tCCD TxCLK IN to TxCLK OUT Delay (Fig. 7) tCCD TxCLK IN to TxCLK OUT Delay (Fig. 7) tJCC Transmitter Jitter Cycle-to-Cycle (Fig. 12 - Note 4) tPLLS tPDD TA = 25°C, VCC = 3.3V 3.8 6.3 ns 2.8 7.1 ns ps Transmitter Phase Lock Loop Set (Fig. 8) 150 230 370 10 ms Transmitter Power Down Delay (Fig. 10) 100 ns f = 85 MHz f = 65 MHz f = 40 MHz 110 210 350 Note 1: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise specified (except VOD and ∆VOD). Note 2: VOS previously referred as VCM. Note 3: The Minimum and Maximum Limits are based on statistical analysis of the device performance over process, voltage, and temperature range. This parameter is functionality tested only on Automatic Test Equipment (ATE). Note 4: The limits are based on bench characterization of the device’s jitter response over the power supply voltage range. Output clock jitter is measured with a cycle-to-cycle jitter of ± 3ns applied to the input clock signal while data inputs are switching (See Figures 15 and 16). A jitter event of 3ns, represents worse case jump in the clock edge from most graphics controller VGA chips currently available. Note 5: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O. Note 6: The 16 grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern approximates signal switching needed to produce groups of 16 vertical stripes across the display. Note 7: Figures 1, 2 show a falling edge data strobe (TxCLK IN/RxCLK OUT). Note 8: Recommended pin to signal mapping. Customer may choose to define differently. 5/14 STLVDS385 AC TIMING DIAGRAMS Figure 1 : "Worst Case" Test Pattern (Note 5) 6/14 STLVDS385 Figure 2 : "16 Grayscale" Test Patter (Notes 6, 7, 8) 7/14 STLVDS385 Figure 3 : (Transmitter) LVDS Output Load Figure 4 : (Transmitter) LVDS Transition Time Figure 5 : (Transmitter) Input Clock Transition Time 8/14 STLVDS385 Figure 6 : (Transmitter) Setup/Hold and High/Low Times (Falling Edge Strobe) Figure 7 : (Transmitter) Clock In to Clock Out Delay 9/14 STLVDS385 Figure 8 : (Transmitter) Phase Lock Loop Set Time Figure 9 : 28 Parallel TTL Data Inputs Mapped to LVDS Outputs 10/14 STLVDS385 Figure 10 : Transmitter Power Down Delay Figure 11 : Transmitter LVDS Output Pulse Position Measurement 11/14 STLVDS385 TSSOP56 MECHANICAL DATA mm. inch DIM. MIN. TYP MAX. A MIN. TYP. 1.2 A1 0.05 0.047 0.15 A2 MAX. 0.002 0.006 0.9 0.035 b 0.17 0.27 0.0067 0.011 c 0.09 0.20 0.0035 0.0079 D 13.9 14.1 0.547 0.555 E 7.95 8.25 0.313 0.325 E1 6.0 6.2 0.236 0.244 e 0.5 BSC 0.0197 BSC K 0˚ 8˚ 0˚ 8˚ L 0.45 0.75 0.020 0.030 A A2 A1 b K e L E c D E1 PIN 1 IDENTIFICATION 1 7065590B 12/14 STLVDS385 Tape & Reel TSSOP56 MECHANICAL DATA mm. inch DIM. MIN. A TYP MAX. MIN. 330 MAX. 12.992 C 12.8 D 20.2 0.795 N 60 2.362 T 13.2 TYP. 0.504 30.4 0.519 1.197 Ao 8.7 8.9 0.342 0.350 Bo 17.2 17.4 0.677 0.685 Ko 1.4 1.6 0.055 0.063 Po 3.9 4.1 0.153 0.161 P 11.9 12.1 0.468 0.476 13/14 STLVDS385 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners © 2004 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com 14/14