NSC DS90CF581MTD

DS90CF581
LVDS Transmitter 24-Bit Color Flat Panel Display (FPD)
Link
General Description
Features
The DS90CF581 transmitter converts 28 bits of CMOS/TTL
data into four LVDS (Low Voltage Differential Signaling) data
streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle
of the transmit clock 28 bits of input data are sampled and
transmitted. At a transmit clock frequency of 40 MHz, 24 bits
of RGB data and 4 bits of LCD timing and control data
(FPLINE, FPFRAME, DRDY, CNTL) are transmitted at a rate
of 280 Mbps per LVDS data channel. Using a 40 MHz clock,
the data throughput is 140 Megabytes per second. This
transmitter is intended to interface to any of the FPD Link receivers.
The chipset is an ideal means to solve EMI and cable size
problems associated with wide, high speed TTL interfaces.
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Up to 140 Megabyte/sec Bandwidth
Narrow bus reduces cable size and cost
290 mV swing LVDS devices for low EMI
Low power CMOS design
Power-down mode
PLL requires no external components
Low profile 56-lead TSSOP package
Falling edge data strobe
Compatible with TIA/EIA-644 LVDS standard
Block Diagrams
DS90CF581
DS012486-28
Order Number DS90CF581MTD
See NS Package Number MTD56
Application
DS012486-2
TRI-STATE ® is a registered trademark of National Semiconductor Corporation.
© 1998 National Semiconductor Corporation
DS012486
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DS90CF581 LVDS Transmitter 24-Bit Color Flat Panel Display (FPD) Link
June 1998
Connection Diagram
DS90CF581
DS012486-3
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2
Absolute Maximum Ratings (Note 1)
DS90CF581
Derate Package:
DS90CF581
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
1.63W
12.5 mW/˚C above
+25˚C
This device does not meet 2000V ESD rating. (Note 4)
Supply Voltage (VCC)
−0.3 to +6V
CMOS/TTL Input Voltage
−0.3 to (VCC + 0.3V)
LVDS Driver Output Voltage
−0.3 to (VCC + 0.3V)
LVDS Output Short Circuit
Duration
continuous
Junction Temperature
+150˚C
Storage Temperature Range
−65˚C to +150˚C
Lead Temperature
(Soldering, 4 sec.)
+260˚C
Maximum Package Power Dissipation @ +25˚C
MTD56 (TSSOP) Package:
Recommended Operating
Conditions
Supply Voltage (VCC)
Operating Free
Air Temperature (TA)
Receiver Input Range
Supply Noise Voltage (VCC)
Min
4.5
Nom
5.0
Max
5.5
Units
V
−10
0
+25
+70
2.4
100
˚C
V
mVP-P
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Units
V
CMOS/TTL DC SPECIFICATIONS
VIH
High Level Input Voltage
2.0
VCC
VIL
Low Level Input Voltage
GND
0.8
V
VCL
Input Clamp Voltage
−0.79
−1.5
V
IIN
Input Current
± 5.1
± 10
µA
290
450
mV
35
mV
ICL = −18 mA
VIN = VCC, GND, 2.5V or 0.4V
LVDS DRIVER DC SPECIFICATIONS
VOD
Differential Output Voltage
∆VOD
Change in VOD between
RL = 100Ω
250
Complimentary Output States
VOS
Offset Voltage (Note 5)
∆VOS
Change in VOS between
1.1
1.25
1.375
V
35
mV
1.6
V
−2.9
−5
mA
±1
± 10
µA
f = 32.5 MHz
f = 37.5 MHz
34
51
mA
36
53
mA
f = 32.5 MHz
f = 37.5 MHz
27
47
mA
28
48
mA
1
25
µA
Complimentary Output States
VOH
High Level Output Voltage
VOL
Low Level Output Voltage
IOS
Output Short Circuit Current
IOZ
Output TRI-STATE ® Current
1.3
0.9
VOUT = 0V, RL = 100Ω
Power Down = 0V, VOUT = 0V or VCC
1.01
V
TRANSMITTER SUPPLY CURRENT
ICCTW
ICCTG
Transmitter Supply Current,
RL = 100Ω, CL = 5 pF,
Worst Case
Worst Case Pattern
(Figure 1, Figure 3)
RL = 100Ω, CL = 5 pF,
Transmitter Supply Current,
16 Grayscale
ICCTZ
Transmitter Supply Current,
Grayscale Pattern
(Figure 2, Figure 3)
Power Down = Low
Power Down
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
Note 2: Typical values are given for VCC = 5.0V and TA = +25˚C.
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise specified (except VOD and ∆VOD).
Note 4: ESD Rating: HBM (1.5 kΩ, 100 pF)
PLL VCC ≥ 1000V
All other pins ≥ 2000V
EIAJ (0Ω, 200 pF) ≥ 150V
Note 5: VOS previously referred as VCM.
3
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Transmitter Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Typ
Max
Units
LLHT
Symbol
LVDS Low-to-High Transition Time (Figure 3)
Parameter
Min
0.75
1.5
ns
LHLT
LVDS High-to-Low Transition Time (Figure 3)
0.75
1.5
ns
TCIT
TxCLK IN Transition Time (Figure 4)
8
ns
TCCS
TxOUT Channel-to-Channel Skew (Note 6) (Figure 5)
TPPos0
Transmitter Output Pulse Position for Bit 0 (Figure 11)
TPPos1
Transmitter Output Pulse Position for Bit 1
6.3
7.2
7.5
ns
TPPos2
Transmitter Output Pulse Position for Bit 2
12.8
13.6
14.6
ns
TPPos3
Transmitter Output Pulse Position for Bit 3
20
20.8
21.5
ns
TPPos4
Transmitter Output Pulse Position for Bit 4
27.2
28
28.5
ns
TPPos5
Transmitter Output Pulse Position for Bit 5
34.5
35.2
35.6
ns
TPPos6
Transmitter Output Pulse Position for Bit 6
ns
TPPos0
Transmitter Output Pulse Position for Bit 0 (Figure 11)
TPPos1
f = 20 MHz
−200
150
350
ps
350
ps
42.2
42.6
42.9
−100
100
300
ps
Transmitter Output Pulse Position for Bit 1
2.9
3.3
3.9
ns
TPPos2
Transmitter Output Pulse Position for Bit 2
6.1
6.6
7.1
ns
TPPos3
Transmitter Output Pulse Position for Bit 3
9.7
10.2
10.7
ns
TPPos4
Transmitter Output Pulse Position for Bit 4
13
13.5
14.1
ns
TPPos5
Transmitter Output Pulse Position for Bit 5
17
17.4
17.8
ns
TPPos6
Transmitter Output Pulse Position for Bit 6
20.3
20.8
21.4
ns
TCIP
TxCLK IN Period (Figure 6)
25
T
50
ns
TCIH
TxCLK IN High Time (Figure 6)
0.35T
0.5T
0.65T
ns
0.35T
0.5T
0.65T
ns
TCIL
TxCLK IN Low Time (Figure 6)
TSTC
TxIN Setup to TxCLK IN (Figure 6)
THTC
f = 40 MHz
f = 20 MHz
f = 40 MHz
TxIN Hold to TxCLK IN (Figure 6)
14
ns
8
2.5
ns
2
ns
TCCD
TxCLK IN to TxCLK OUT Delay @ 25˚C, VCC = 5.0V (Figure 7)
9.7
ns
TPLLS
Transmitter Phase Lock Loop Set (Figure 8)
10
ms
TPDD
Transmitter Powerdown Delay (Figure 10)
100
ns
5
Note 6: This limit based on bench characterization.
AC Timing Diagrams
DS012486-15
FIGURE 1. “WORST CASE” Test Pattern
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AC Timing Diagrams
(Continued)
DS012486-16
Note 7: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O.
Note 8: The 16 grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern approximates signal switching needed
to produce groups of 16 vertical stripes across the display.
Note 9: Figure 1 and Figure 2 show a falling edge data strobe (TxCLK IN/RxCLK OUT).
Note 10: Recommended pin to signal mapping. Customer may choose to define differently.
FIGURE 2. “16 GRAYSCALE” Test Pattern (Notes 7, 8, 9, 10)
DS012486-8
DS012486-9
FIGURE 3. DS90CF581 (Transmitter) LVDS Output Load and Transition Timing
5
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AC Timing Diagrams
(Continued)
DS012486-17
FIGURE 4. DS90CF581 (Transmitter) Input Clock Transition Time
DS012486-18
Note 11: Measurements at Vdiff = 0V
Note 12: TCCS measured between earliest and latest initial LVDS edges.
Note 13: TxCLK OUT Differential High→Low Edge for DS90CF581
TxCLK OUT Differential Low→High Edge for DS90CR581
FIGURE 5. DS90CF581 (Transmitter) Channel-to-Channel Skew
DS012486-12
FIGURE 6. DS90CF581 (Transmitter) Setup/Hold and High/Low Times
DS012486-19
FIGURE 7. DS90CF581 (Transmitter) Clock In to Clock Out Delay
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AC Timing Diagrams
(Continued)
DS012486-14
FIGURE 8. DS90CF581 (Transmitter) Phase Lock Loop Set Time
DS012486-23
FIGURE 9. 28 Parallel TTL Data Inputs Mapped to LVDS Outputs (DS90CF581)
DS012486-24
FIGURE 10. Transmitter Powerdown Delay
7
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AC Timing Diagrams
(Continued)
DS012486-26
FIGURE 11. Transmitter LVDS Output Pulse Position Measurement
DS90CF581 Pin Description — FPD Link Transmitter
I/O
No.
TxIN
Pin Name
I
28
Description
TxOUT+
O
4
Positive LVDS differential data output
TxOUT−
O
4
Negative LVDS differential data output
FPSHIFT IN
I
1
TTL level clock input. The falling edge acts as data strobe.
TxCLK OUT+
O
1
Positive LVDS differential clock output
TxCLK OUT−
O
1
Negative LVDS differential clock output
PWR DOWN
I
1
TTL level input. Assertion (low input) TRI-STATE the outputs, ensuring low current at power
down.
TTL level input. This includes: 8 Red, 8 Green, 8 Blue, and 4 control lines (FPLINE,
FPFRAME, DRDY, CNTL). (Also referred to as HSYNC, VSYNC and DATA ENABLE)
VCC
I
4
Power supply pins for TTL inputs
GND
I
5
Ground pins for TTL inputs
PLL VCC
I
1
Power supply pin for PLL
PLL GND
I
2
Ground pins for PLL
LVDS VCC
I
1
Power supply pin for LVDS outputs
LVDS GND
I
3
Ground pins for LVDS outputs
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DS90CF581 LVDS Transmitter 24-Bit Color Flat Panel Display (FPD) Link
Physical Dimensions
inches (millimeters) unless otherwise noted
56-Lead Molded Thin Shrink Small Outline Package, JEDEC
Order Number DS90CF581MTD
NS Package Number MTD56
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be reasonably expected to result in a significant injury
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