STMICROELECTRONICS STP80N05-09

STP80N05-09
N - CHANNEL ENHANCEMENT MODE
”ULTRA HIGH DENSITY” POWER MOS TRANSISTOR
TYPE
STP80N05-09
■
■
■
■
■
■
VDS S
RDS(o n)
ID
50 V
< 0.009 Ω
80 A
ULTRA HIGH DENSITY TECHNOLOGY
TYPICAL RDS(on) = 7 mΩ
AVALANCHE RUGGED TECHNOLOGY
LOW GATE CHARGE
HIGH CURRENT CAPABILITY
o
175 C OPERATING TEMPERATURE
3
1
APPLICATIONS
■ SYNCROUNOUS RECTIFIERS
■ HIGH CURRENT, HIGH SPEED SWITCHING
■ DC-DC & DC-AC CONVERTER ABSOLUTE
MAXIMUM RATINGS
2
TO-220
INTERNAL SCHEMATIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Symbol
VDS
Parameter
Drain-source Voltage (VGS = 0)
VDGR
Drain- gate Vol tage (R GS = 20 kΩ)
V GS
Gate-s ource Voltage
o
Value
Unit
50
V
50
V
± 20
V
ID
Drain Current (conti nuous) at Tc = 25 C
80
A
ID
o
60
A
I DM (•)
Pt ot
Drain Current (conti nuous) at Tc = 100 C
Drain Current (pulsed)
320
A
Total Dis sipation at Tc = 25 o C
150
W
1
W/ oC
5
V/ns
Derating Fac tor
dV/dt(1 ) Peak Diode Recov ery vo ltage slo pe
Tstg
Tj
Storage Temperature
Max. Operating Junction Temperature
(•) Pulse width limited by safe operating area
March 1997
-65 to 175
o
C
175
o
C
(1) ISD ≤ 60 A, di/dt ≤ 200 A/ms, V DD ≤ V(BR)DSS, TJ ≤ TJMAX
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STP80N05-09
THERMAL DATA
Rt hj-case
R th j-amb
R thc-sin k
Tl
Thermal Resist ance Junc tion-case
Max
Thermal Resist ance Junc tion-ambi ent
Max
Thermal Resist ance Case -sink
Typ
Max imum Lead Temperature For Sol dering Purpose
o
1
62.5
0.5
300
C/W
C/W
o
C/W
o
C
o
AVALANCHE CHARACTERISTICS
Symbol
Parameter
I AR
Avalanche Current, Repetitive or Not-Repetitive
(pulse width limit ed by Tj max , δ < 1%)
E AS
Sin gle Pul se Aval anc he Energy
o
(starting Tj = 25 C, ID = I AR , V DD = 25 V)
Max Value
Unit
60
A
600
mJ
ELECTRICAL CHARACTERISTICS (Tcase = 25 oC unless otherwise specified)
OFF
Symbol
V(BR)DSS
Parameter
Drain-so urce
Breakdown Voltage
Test Conditions
I D = 250 µA
Min.
VGS = 0
IDS S
Zero G ate Voltage
VDS = Max Rating
Drain Current (VG S = 0) VDS = Max Rating
I GSS
Gate-body Leak age
Current (VDS = 0)
Typ.
Max.
50
Unit
V
Tc = 125 oC
VG S = ± 20 V
1
10
µA
µA
± 100
nA
Max.
Unit
ON (∗)
Symbol
Parameter
Test Conditions
VGS( th)
Gate Threshold Voltage VDS = V GS
RDS( on)
Static Drai n-s ource On
Resistance
I D(on)
Min.
ID = 250 µA
2
VG S = 10V I D = 40 A
On State Drai n Current VDS > I D(on) x R DS(on)max
VG S = 10 V
Typ.
3
4
V
0.007
0.009
Ω
80
A
DYNAMIC
Symbol
gfs (∗)
C iss
C oss
C rss
2/9
Parameter
Test Conditions
Forward
Transconductance
VDS > I D(on) x R DS(on)max
Input Capac itance
Output Capacitance
Reverse Trans fer
Capacitance
VDS = 25 V
f = 1 MHz
Min.
ID = 40 A
VGS = 0
Typ.
Max.
Unit
25
S
5900
900
230
pF
pF
pF
STP80N05-09
ELECTRICAL CHARACTERISTICS (continued)
SWITCHING ON
Symbol
t d(on)
tr
(di/ dt)on
Qg
Qgs
Qgd
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
42
200
ns
ns
Turn-on Time
Rise Time
VDD = 30 V
ID = 40 A
RG = 4.7 Ω
V GS = 10 V
(see test circuit, figure 3)
32
160
Turn-on Current Slope
VDD = 48 V
ID = 80 A
RG =5 0 Ω
VGS = 10 V
(see test circuit, figure 5)
240
Total Ga te Charge
Gate-Source Charge
Gate-Drain Charge
VDD = 40 V
230
30
60
280
nC
nC
nC
Typ.
Max.
Unit
35
175
240
46
230
300
ns
ns
ns
Typ.
Max.
Unit
80
320
A
A
1.5
V
I D = 80 A V GS = 10 V
A/µs
SWITCHING OFF
Symbol
tr(Vof f)
tf
tc
Parameter
Off-volt age Rise Time
Fal l Time
Cross-over Time
Test Conditions
Min.
VDD = 48 V
ID = 40 A
V GS = 10 V
RG = 4.7 Ω
(see test circuit, figure 5)
SOURCE DRAIN DIODE
Symbol
Parameter
Test Conditions
I SD
ISD M (•)
Source-drain Current
Source-drain Current
(pulsed)
VSD (∗)
Forward On Voltage
I SD = 80 A
Reverse Recovery
Tim e
Reverse Recovery
Charge
Reverse Recovery
Current
I SD = 80 A
t rr
Qrr
I RRM
Min.
VGS = 0
di/dt = 100 A/µs
VR = 30 V
Tj = 150 o C
(see test circuit, figure 5)
125
ns
0.6
µC
10
A
(∗) Pulsed: Pulse duration = 300 µs, duty cycle 1.5%
(•) Pulse width limited by safe operating area
Safe Operating Area
Thermal Impedance
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STP80N05-09
Derating Curve
Output Characteristics
Transfer Characteristics
Transconductance
Static Drain-source On Resistance
Gate Charge vs Gate-source Voltage
4/9
STP80N05-09
Capacitance Variations
Normalized Gate Threshold Voltage vs
Temperature
Normalized On Resistance vs Temperature
Turn-on Current Slope
Turn-off Drain-source Voltage Slope
Cross-over Time
5/9
STP80N05-09
Switching Safe Operating Area
Accidental Overload Area
Source-drain Diode Forward Characteristics
Fig. 1: Unclamped Inductive Load Test Circuit
6/9
Fig. 2: Unclamped Inductive Waveform
STP80N05-09
Fig. 3: Switching Times Test Circuits For
Resistive Load
Fig. 4: Gate Charge test Circuit
Fig. 5: Test Circuit For Inductive Load Switching
And DIode Recovery Times
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STP80N05-09
TO-220 MECHANICAL DATA
mm
DIM.
MIN.
inch
MAX.
MIN.
A
4.40
TYP.
4.60
0.173
0.181
C
1.23
1.32
0.048
0.051
D
2.40
2.72
0.094
D1
TYP.
MAX.
0.107
1.27
0.050
E
0.49
0.70
0.019
0.027
F
0.61
0.88
0.024
0.034
F1
1.14
1.70
0.044
0.067
F2
1.14
1.70
0.044
0.067
G
4.95
5.15
0.194
0.203
G1
2.4
2.7
0.094
0.106
H2
10.0
10.40
0.393
L2
0.409
16.4
0.645
13.0
14.0
0.511
0.551
L5
2.65
2.95
0.104
0.116
L6
15.25
15.75
0.600
0.620
L7
6.2
6.6
0.244
0.260
L9
3.5
3.93
0.137
0.154
DIA.
3.75
3.85
0.147
0.151
D1
C
D
A
E
L4
H2
G
G1
F1
L2
F2
F
Dia.
L5
L9
L7
L6
8/9
L4
P011C
STP80N05-09
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express
written approval of SGS-THOMSON Microelectonics.
 1996 SGS-THOMSON Microelectronics - Printed in Italy - All Rights Reserved
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