STPIC44L02 4 CHANNEL SERIAL AND PARALLEL LOW SIDE PRE-FET DRIVER ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 4-CHANNEL SERIAL-IN PARALLEL-IN LOW SIDE PRE-FET DRIVER DEVICES ARE CASCADABLE INTERNAL 55V INDUCTIVE LOAD CLAMP AND VGS PROTECTION CLAMP FOR EXTERNAL POWER FETS INDEPENDENT SHORTED-LOAD AND SHORT-TO-BATTERY FAULT DETECTION ON ALL GATE TERMINALS INDEPENDENT OFF-STATE OPEN-LOAD FAULT SENSE OVER-BATTERY-VOLTAGE LOCKOUT PROTECTION AND FAULT REPORTING UNDER-BATTERY VOLTAGE LOCKOUT PROTECTION ASYNCRONOUS OPEN-GATE FAULT FLAG DEVICE OUTPUT CAN BE WIRED OR WITH MULTIPLE DEVICES FAULT STATUS RETURNED THROUGH SERIAL OUTPUT TERMINAL INTERNAL GLOBAL POWER-ON RESET OF DEVICE AND EXTERNAL RESET TERMINAL HIGH IMPEDANCE CMOS COMPATIBLE INPUTS WITH HYSTERESIS TRANSITION FROM THE GATE OUTPUT TO A LOW DUTY CYCLE PWM MODE WHEN A SHORTED LOAD FAULT OCCURS DESCRIPTION The STPIC44L02 is a low-side predriver that provides serial and parallel input interfaces to control four external FET power switches. It is mainly designed to provide low-frequency switching, inductive load applications such as solenoids and relays. Fault status is available in a serial-data format. Each driver channel has independent off-state open-load detection and on-state shorted load short to battery detection. The STPIC44L02 offers a battery over voltage and undervoltage detection and shutdown. If a fault occurs while using the STPIC44L02, the channel transitates into a low duty cycle, pulse width modulated (PWM) signal as long as the fault is present. These devices provide control of output channels through a serial input interface or a parallel input interface. A command to enable the output from July 2003 SOP either interface enables the respective channels gate output to the external FET. The serial interface is recommended when the number of signals between the control device and the predriver are minimized and the speed of operation is not critical. In applications where the predriver must respond very quickly or asynchronously, the parallel input interface is recommended. For serial operation, the control device must transitate CS from high to low to activate the serial input interface. When this occurs, SDO, is enabled, fault data is latched into the serial interface, and the fault flag is refreshed. Data is clocked into the serial registers on low to high transitions of SCLK through SDI. Each string of data must consist of at least four bits of data. In applications where multiple devices are cascaded together, the string of data must consist of four bits for each device. A high data bit turns the respective output channel on and a low data bit turns it off. Fault data for the device is clocked out of SDO as serial input data is clocked into the device. Fault data consists of fault flags for shorted load and open load flags (bits 0-3) for each of the four output channels. Fault register bits are set or cleared asynchronously to reflect the current state of the hardware. A fault must be present when CS is transitated from high to low to be captured and reported in the serial fault data. New faults cannot be captured in the serial register when CS is low. CS must be transitated high after all of the serial data has been clocked into the device. A low to high transition of CS transfers the last four bits of serial data to the 1/21 STPIC44L02 output buffer that puts SDO in a high impedance state and clears and reenables the fault register. The STPIC44L02 was designed to allow the serial input interfaces of multiple devices to be cascated together to simplify the serial interface of the controller. Serial input data flows through the device and is transferred out SDO following the fault data in cascaded configurations. For parallel operation, data is transferred directly from the parallel input interface IN0-IN3 to the respective GATE(0-3) output asynchronously. SCLK or CS is not required for parallel control. A 1 on the parallel input turns the respective channel on, where as a 0 turns it off. Note that either the serial input interface or the parallel input interface can enable a channel. Under parallel operation, fault data must still be collected through the serial data interface. The predriver monitors the drain voltage for each channel to detect shorted load or open load fault conditions, in the on and off state respectively. These devices offer the option of using an internally generated fault reference voltage or an externally supplied fault reference voltage through VCOMP for fault detection. The internal fault reference is selected by connecting VCOMPEN to GND and the external reference is selected by connecting VCOMPEN to VCC. The drain voltage is compared to the fault reference when the channel is turned on to detect shorted load conditions and when the channel is off to detect open load conditions. If a fault occurs, the channel transitates into a low duty cycle, pulse width modulated (PWM) signal as long as the fault is present. Shorted load fault conditions must be present for at least the shorted load deglicth time, t(STBDG), to be flagged as a fault. A fault flag is sent to the control device as well as the serial fault register bits. More detail on fault detection operation is presented in the device operation section of this datasheet. The device provides protection from over battery voltage and under battery voltage conditions irrespective of the state of the output channels. When the battery voltage is greater than the overvoltage threshold or less than the undervotlage threshold, all channels are disabled and a fault flag is generated. Battery voltage faults are not reported in the serial fault data. The outputs return to normal operation once the battery voltage fault has been corrected. When an over battery/under battery voltage condition occurs, the device reports the battery fault, but disables fault reporting for open and shorted load conditions. Fault reporting for open and shorted load conditions are reenabled after the battery fault condition has been corrected. This device provides inductive transient protection on all channels. The drain voltage is clamped to protect the FET. The clamp voltage is defined by the sum of VCC and turn on voltage of the external FET. The predriver also provides a gate to source voltage (VGS) clamp to protect the gate source terminals of the power FET from exceeding their rated voltages. An external active low RESET is provided to clear all register and flags in the device. GATE(0-3) outputs are disabled after RESET has been pulled low. The device provide pull-down resistors on all inputs except CS and RESET. A pull-up resistor is used on CS and RESET. ORDERING CODES 2/21 Type Package Comments STPIC44L02PTR SSOP24 (Tape & Reel) 1350 parts per reel STPIC44L02 Figure 1 : Schematic Diagram 3/21 STPIC44L02 PIN DESCRIPTION PIN No SYMBOL I/O NAME AND FUNCTION 1 FLT I 2 VCOMPEN I 3 VCOMP I 4 5 6 7 8 IN0 IN1 IN2 IN3 CS I Fault Flag. FLT is a logic level open-drain output that provides a real time fault flag for shorted-load, open-load, over-battery voltage, under-battery voltage faults. The device can be ORed with FLT terminals on other devices for interrupt handling. FLT requires an external pull-up resistor. Fault reference voltage select. VCOMPEN selects the internally generated fault reference voltage (0) or an external fault reference (1) to be used in the shorted and open load fault detection circuitry. Fault reference voltage. VCOMP provides an external fault reference voltage for the shorted-load and open load fault detection circuitry. Parallel gate driver. IN0 trough In3 are real-time controls for the gate pre drive circuitry. They are CMOS compatible with hysteresis. 9 SDO O 10 SDI I 11 SCLK I 12 VCC I 13 14 16 19 21 15 17 18 20 22 GND DRAIN0 DRAIN1 DRAIN2 DRAIN3 GATE0 GATE1 GATE2 GATE3 RESET I I Ground FET drain inputs. DRAIN0 through DRAIN3 are used for both open load and short circuit fault detection at the drain of the external FETs. They are also used for inductive transient protection. O Gate drive output. GATE0 through GATE3 outputs are derived from the VBAT supply voltage. Internal clamps prevent voltages on these nodes from exceeding the VGS rating of most FETs. I 23 24 NC VBAT Reset. A high-to low transition of RESET clears all registers and flags. Gate outputs turn off and the FLT flag is cleared. Not Connected Battery Supply Voltage 4/21 I I Chip select. A high to low transition on CS enables SDO, latches fault data into the serial interface, and refreshes FLT. When CS is high, the fault register can change fault status. On the falling edge of CS, fault data is latched into the serial output register and transferred using SDO and SCLK. On a low to high transition of CS, serial data is latched in to the output control register. Serial data output. SDO is a 3-state output that transfers fault data to the controlling device. It also passes serial input data to the next stage for cascaded operation. SDO is taken to a high-impedance state when CS is in a high state. Serial data input. Output control data is clocked into the serial register through SDI. A 1 on SDI commands a particular gate output on and a 0 turns it off. Serial clock. SCLK clocks the shift register. Serial data is clocked into SDI and serial fault data is clocked out of SDO on the falling edge of the serial clock. Logic Supply Voltage STPIC44L02 Figure 2 : Pin Configuration ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit V VCC Logic Supply Voltage (See Note 1) -0.3 to 7 VBAT Battery Supply Voltage -0.3 to 60 V VI Logic Input Voltage Range -0.3 to 7 V VO Output Voltage (SDO and FLT) -0.3 to 7 V VO Output Voltage -0.3 to 15 V VI Logic Input Voltage Range -0.3 to 7 V VDS Drain to Source Voltage -0.3 to 60 V TC Operating Case Temperature Range -40 to +125 °C TJ Maximum Junction Temperature 150 °C -40 to +150 °C Tstg Storage Temperature Range Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied. Note 1: All voltage value are with respect to GND RECOMMENDED OPERATING CONDITIONS Symbol Parameter VCC Logic Supply Voltage VBAT Battery Supply Voltage VIH High Level Input Voltage VIL Min. Min. Max. Unit 4.5 5 5.5 V 8 24 V 0.85VCC VCC V 0.15VCC Low Level Input Voltage 0 ts Set-up Time, SDI High Before SCLK ↑ 10 th Hold Time, SDI High After SCLK ↑ 10 TC Operating Case Temperature -40 V ns ns 125 °C 5/21 STPIC44L02 ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING FREE-AIR TEMPERATURE RANGE (unless otherwise specified.) Symbol Parameter Test Conditions Min. Typ. Max. Unit IBAT Supply Current All Outputs OFF, VBAT = 12V 50 150 250 µA ICC Supply Current All Outputs OFF, VBAT = 5.5V 0.5 1.5 3 mA (see figure 21) 32 34 36 V 0.1 0.3 0.5 V 4.1 4.8 5.4 V 50 150 300 mV 13.5 V V(ovsd) Vhys(ov) V(uvsd) Vhys(uv) VG IO(H) IO(L) V(stb) Vhys(stb) Over Battery Voltage Gate Disabled Shutdown Over Battery Voltage Reset Hysteresys Under Battery Voltage Gate Disabled Shutdown Under Battery Voltage Reset Hysteresys Gate Drive Voltage VBAT = 8 to 24V IO = 100µA VBAT = 5.5 to 8V IO = 100µA (see figure 20) Maximum Current Output VO = GND For Drive Terminal Pull-Up Maximum Current Output VO = 7V For Drive Terminal Pull-Down Short to Battery, Shorted VCOMPEN = L Load, Open Load Detection Voltage Short to Battery Hysteresys Open Load OFF State Detection Voltage Threshold Vhys(open) Open Load Hysteresys Open Load Off State II(open) Detection Current VD(open) 7 8 V 0.5 5 1.8 2.5 mA 0.5 1.2 2.5 mA 1.1 1.25 1.4 V 30 VCOMPEN = L 1.1 1.25 mV 1.4 60 VDRAIN = VREF = 1.25V 30 60 V mV 80 µA VDRAIN = 24V (see figure 24) 250 µA II(PU) Input Pull-up Current VCC = 5V VI = 0 10 µA II(PD) Input Pull-down Current VCC = 5V VI = 5V 10 µA Vhys Input Voltage Hysteresys VCC = 5V 0.6 High Level Serial Output Voltage Low Level Serial Output Voltage 3-State Current Serial Data Output Fault Interrupt Output Voltage Fault External Reference Voltage Output Clamp Voltage IO = 1mA 0.8VCC VO(SH) VO(SL) IOZ(SD) VO(CFLT) VI(COMP) VC 6/21 IO = 1mA VCC = 0 to 5.5V -10 IO = 1mA VCOMPEN = H dc < 1% 0.85 47 V V 0.1 0.4 V 1 10 µA 0.1 0.5 V 3 V 63 V 1 tW = 100µs 1.1 55 STPIC44L02 SWITCHING CHARACTERISTICS (VCC=5V, VBAT=5V, TC= 25°C, unless otherwise specified.) Symbol Parameter t(STBFM) (see figures 16, 17) 60 µs (see figures 16, 17) 12 µs C(gate) = 400pF 3.5 µs C(gate) = 400pF 4 µs tr1 Short to Battery, Shorted Load, Open Load Fault Mask Time Short to Battery, Shorted Load, Deglitch Time Propagation Turn-On Delay Time, CS or IN0-IN3 to Gate0-Gate3 Propagation Turn-Off Delay Time, CS or IN0-IN3 to Gate0-Gate3 Rise Time, Gate0-Gate3 C(gate) = 400pF 1.5 µs tf1 Fall Time, Gate0-Gate3 C(gate) = 400pF 2 µs f(SCLK) Serial Clock Frequency trf(SB) Refresh Time Short to (see figure 16) Battery Refresh pulse width Short (see figure 16) to Battery Setup Time CS ↓ to SCLK ↓ (see note 1) t(STBDG) tPLH tPHL tW) tsu1 tpd1 tpd2 tpd3 Propagation Delay Time CS to SDO Valid Propagation Delay Time SCLK to SDO Valid Propagation Delay Time CS to SDO 3-State tr2 Rise Time, SDO 3-State to SDO Valid tf2 Fall Time, SDO 3-State to SDO Valid tr3 Rise Time, FLT tf3 Rise Time, FLT Test Conditions Min. Typ. Max. 10 RL = 10KΩ (see figure 6) RL = 10KΩ (see figure 6) RL = 10KΩ to GND Over Battery Fault RL = 10KΩ to GND No Fault RL = 10KΩ (see figure 9) RL = 10KΩ (see figure 9) Unit MHz 10 ms 68 µs (see figure 4) 10 ns CL = 200pF 40 ns 20 ns 2 µs 30 ns CL = 50pF CL = 200pF (see figure 7) CL = 200pF (see figure 8) CL = 50pF 20 ns 1.2 µs CL = 50pF 15 ns Note 1: The td1 is referred to the falling edge of the first clock after the CS falls down 7/21 STPIC44L02 Figure 3 : Switching Time Figure 4 : Setup Time CS ↓ to SCLK ↓ 8/21 STPIC44L02 Figure 5 : Propagation Delay Time Figure 6 : Propagation Delay Time Figure 7 : SDO Switching Time 9/21 STPIC44L02 Figure 8 : SDO Switching Time Figure 9 : FLT Switching Time PRINCIPLES OF OPERATION SERIAL DATA OPERATION The STPIC44L02 offers serial input interface to the microcontroller to transfer control data to the predriver and fault data back to the controller. The serial input interface consists of: SCLK - Serial Clock CS - Chip Select SDI - Serial Data Input SDO - SeriaL Data Output Serial data is shifted into the least significant bit (LSB) of the SDI shift register on the rising edge of the first SCLK after CS has transitated from 1 to 0. The CS must be transitated from 1 to 0 before the falling edge of the first clock (see note 1). Four clock cycles must occur before CS transitates high for a proper control of the outputs. Less than four clock cycles result in fault data being latched into the output control buffer. Eight bits data can be shifted into the device, but the first 4 bits shifted out are always the fault data and the last 4 bits shifted in are always the output control data. A low-to-high transition on CS 10/21 latches the contents of the serial shift register into the output control register. A logic 0 input to SDI turns off the corresponding parallel output and a logic 1 input turns the output on (see figure 10). Data is shifted out of SDO on the falling edge of SCLK. The MSB of fault data is available after CS is transitated low. The remaining 3 bits of fault data are shifted out in the following three clock cycles. Fault data is latched into the serial register when CS is transitated low. A fault must be present on the high to low transition of CS to be captured by the device. The CS input must be transitated to a high state after the last bit of serial data has been clocked into the device. The rising edge of CS inhibit SDI puts SDO into a high impedance state, latches the 4 bits of serial data into the output control register, and clears and reenables the serial fault registers (see figure 11). When a shorted load condition occurs, the device automatically retries the output and the fault clears after the fault condition has been corrected. STPIC44L02 Figure 10 : Serial Programming Example Figure 11 : 8-Bit Serial Programming Example (single device) 11/21 STPIC44L02 Figure 12 : 8-Bit Serial Programming Example (two predrivers cascated) Figure 13 : Fault Reading Example PARALLEL INPUT DATA OPERATION In addition to the serial interface the STPIC44L02 also provides a parallel interface to the microcontroller. The output turns on when either the parallel or the serial interface make it turn on. The parallel data terminals are real time control inputs for the outputs drivers. SCLK and CS are not required to transfer parallel input data to the output buffer. Fault data must be read over the serial data bus as described in the serial data operation section of this datasheet (see figure 13). The parallel input must be transitated low and then high to clear and reenable a gate output after it has been disabled due to a shorted load fault condition. CHIPSET PERFORMANCE UNDER FAULT CONDITIONS The STPIC44L02 and power FET arrays are designed for normal operation over a battery 12/21 voltage range of 8V to 24V with load fault detection from 4.8V to 34V. It offers onboard fault detection to handle a variety of faults that may occur within a system. The circuits primary function is to prevent damage to the load and the power FETs in the event that a fault occurs. Note that unused DRAIN0-DRAIN3 inputs must be connected to VBAT through a pull-up resistor to prevent false reporting of open load fault conditions. The circuitry detects the fault, shuts off the output to the FET and reports the fault to the microcontroller. The primary faults under consideration are: 1) Shorted Load 2) Open Load 3) over battery voltage shutdown 4) Under battery voltage shutdown. SHORTED LOAD FAULT CONDITION STPIC44L02 The STPIC44L02 monitors the drain voltage of each channel to detect shorted load conditions. The onboard deglitch timer starts running when the gate output to the power FET transitates from the off state to the on state. The timer provides a 60µs deglitch time, t(STBFM), to allow the drain voltage to stabilize after the power FET has been turned on (see figure 16 and 17). The deglitch delay time is only enabled for the first 60µs after the FET has been turned on. After the deglitch delay time, the drain voltage is checked to verify that it is less than the fault reference voltage. When it is greater than the reference voltage for at least the short to battery deglitch time, t(STBDG) FLT flags the microcontroller that a fault condition exists and gate output is automatically shut off until the error condition has been corrected. An overheating condition on the FET occurs when the controller continually tries to reenable the output under shorted load fault conditions. When a shorted load fault is detected, the gate output is transitated into a low duty cycle PWM signal to protect the FET from overheating. The PWM rate is defined as t(SB) and the pulse width is defined as tW. The gate output remains in this state until the fault has been corrected or until the controller disables the gate output. The microcontroller can read the serial port on the predriver to isolate the channel that reported the fault condition. Fault bits 0-3 distinguish faults for each of the output channels. When a shorted load occurs, the STPIC44L02 automatically retries the output and the fault clears after the fault condition has been corrected. Figure 16 illustrates operation after a gate output has been turned on. The gate to the power FET is turned on and the deglitch timer starts running. Under normal operation, T1 turns on and the drain operates below the reference point set at U1. The output of U1 is low and a fault condition is not flagged. Figure 14 : Open Load Test Circuit 13/21 STPIC44L02 Figure 15 : Normal Operation Figure 16 : Shorted Load Condition (Deglitch Time) OPEN LOAD The STPiC44L02 monitors the drain of each power FET for open circuit conditions that may exist. The 60µA current source is provided to monitor open load fault conditions. Open-load faults are only detected when the power FET is turned off. When load impedance is open or substantially high, the 60µA current source has adequate drive to pull the drain of T1 below the fault reference threshold on the detection circuit. 14/21 Unused DRAIN0-DRAIN3 inputs must be connected to VBAT through a pull-up resistor to prevent false reporting of open-load fault conditions. The on-board deglitch timer starts running when the STPiC44L02, gate output to the power FET transitates to the off state. The timer provides a 60ms deglitch time, T(STBFM), to allow the drain voltage to stabilize after the powerFET has been turned off. The deglitch time is only enabled for the first 60ms after the FET has been STPIC44L02 turned off. After the deglitch delay time, the drain is checked to verify that it is greater than the fault reference voltage. When it is less than the reference voltage, a fault is flagged to the microcontroller through FLAT that an open-load fault condition exists. The microcontroller can then read the serial port on the STPiC44L02 to isolate the channel that reported the fault condition. Fault bits 0-3 distinguish faults for each of the output channels. Figures 18 and 19 illustrate the operation of the open-load detection circuit. This feature provides useful information to the microcontroller to isolate system failures and warn the operator that a problem exists. Examples of such applications would be a warning that a light bulb filament may be open, solenoid coils may be open, etc. Figure 17 : Open Load Short Circuit test Circuitry Figure 18 : Normal Condition Driving Load 15/21 STPIC44L02 Figure 19 : Open Load ConditionTime OVER-BATTERY-VOLTAGE SHUTDOWN The STPIC44L02 monitors the battery voltage to prevent the power FETs turning on in the event that the battery voltage is too high. This condition may occur due to voltage transients resulting from a loose battery connection. The TPIC44L02 turns the power FET off when the battery voltage is above 34V to prevent possible damage to the load and the FET. GATE(0-3) output goes back to normal operation after the overvoltage condition has been corrected. An over-battery-voltage fault is flagged to the controller through FLT. The over-battery-voltage fault is not reported in the serial fault word. When an over voltage condition occurs, the device reports the battery fault, but disables fault reporting for open and shorted-load conditions. Fault reporting for open and shorted-load conditions are re-enabled after the battery fault condition has been corrected. When the fault condition is removed before the CS signal transitates low, the fault condition is not captured in the serial fault register. The fault flag resets on a high-to-low transition of CS providing that no other faults are present in the device. Figure 21 illustrates the operation of the over-battery voltage detection circuit. Figure 20 : Under Battery Shutdown UNDER-BATTERY-VOLTAGE SHUTDOWN The STPIC44L02 monitors the battery voltage to prevent the power FETs from being turned on in the event that the battery voltage is too low. When the battery voltage is below 4.8V, then 16/21 GATE0-GATE3 may not provide sufficient gate voltage to the power FETs to minimize the on-resistance that could result in a thermal stress on the FET. The output goes back to normal operation after the under voltage condition has STPIC44L02 been corrected. An under-battery-voltage fault is flagged to the controller through FLT. The under-battery voltage fault is not reported in the serial fault word. When an under-battery-voltage condition occurs, the device reports the battery fault but disables fault reporting for open and shorted load conditions. When the fault condition is removed before the CS signal transitates low, the fault condition is not captured in the serial fault register. The fault flag resets on a high-to-low transition of CS providing that no other faults are present in the device. Figure 21 illustrates the operation of the under voltage detection circuit. Figure 21 : Over Battery Shutdown INDUCTIVE VOLTAGE TRANSIENTS A typical application for the pre driver/power FET circuit is to switch inductive loads. When an inductive load is switched off, a large voltage spike can occur. These spikes can exceed the maximum VDS rating for the external FET and damage the device when the proper protection is not in place. The FET can be protected from these transients through a variety of methods using external components. The STPIC44L02 offers that protection in the form of a zener diode stack connected between the DRAIN input and GATE output (see figure 22). Zener diode Z1 turns the FET on to dissipate the transient energy. GATE diode Z2 is provided to prevent the gate voltage from exceeding 13V during normal operation and transient protection. Figure 22 : Switching Time EXTERNAL FAULT REFERENCE INPUT The STPIC44L02 compares each channel drain voltage to a fault reference to detect shorted-load and open-load conditions. The user has the option of using the internal generated 1.25V fault reference or providing an external reference voltage through VCOMP. The internal reference is selected by connecting VCOMPEN to GND and VCOMP is selected by connecting VCOMPEN to VCC (see Figure 23). Proper layout techniques should be used in the grounding network for the VCOMP circuit on the STPIC44L02. The ground for the 17/21 STPIC44L02 predriver and VCOMP network should be connected to a Kelvin ground if available; otherwise, they should make single-point contact back to the power ground of the FET array. Improper grounding techniques can result in inaccuracies in detecting faults. Figure 23 : External Reference Selection VREF VCOMPEN 1.25V VCOMP 1 TYPICAL PERFORMANCE CHARACTERISTICS (unless otherwise specified Tj = 25°C) Figure 24 : Open Load Off State Detection Current 18/21 0 STPIC44L02 SSOP24 MECHANICAL DATA mm. inch DIM. MIN. TYP MAX. A MIN. TYP. MAX. 2 A1 0.05 A2 1.65 b 0.079 0.002 1.75 1.85 0.065 0.22 0.38 0.009 0.015 c 0.09 0.25 0.004 0.010 D 7.9 8.2 8.5 0.311 0.323 0.335 E 7.4 7.8 8.2 0.291 0.307 0.323 E1 5.00 5.3 5.6 0.197 0.209 0.220 e 0.069 0.65 BSC K 0˚ L 0.55 A 0.073 0.0256 BSC 0.75 8˚ 0˚ 8˚ 0.95 0.022 0.030 0.037 A2 A1 b K e L E c D E1 PIN 1 IDENTIFICATION 1 0053237/C 19/21 STPIC44L02 Tape & Reel SSOP24 MECHANICAL DATA mm. inch DIM. MIN. A MAX. MIN. 330 13.2 TYP. MAX. 12.992 C 12.8 D 20.2 0.795 N 60 2.362 T 20/21 TYP 0.504 22.4 0.519 0.882 Ao 8.4 8.6 0.331 0.339 Bo 8.7 8.9 0.343 0.351 Ko 2.9 3.1 0.114 0.122 Po 3.9 4.1 0.153 0.161 P 11.9 12.1 0.468 0.476 STPIC44L02 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. © The ST logo is a registered trademark of STMicroelectronics © 2003 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. © http://www.st.com 21/21