TI TPIC44L02

TPIC44L01, TPIC44L02, TPIC44L03
4-CHANNEL SERIAL AND PARALLEL LOW-SIDE PRE-FET DRIVER
SLIS062A – NOVEMBER 1996 – REVISED SEPTEMBER 1997
D
D
D
D
D
D
D
4-Channel Serial-in Parallel-in Low-Side
Pre-FET Driver
Devices Are Cascadable
Internal 55-V Inductive Load Clamp and
VGS Protection Clamp for External Power
FETs
Independent Shorted-Load/Short-toBattery Fault Detection on All Drain
Terminals
Independent OFF-State Open-Load Fault
Sense
Over-Battery-Voltage Lockout Protection
and Fault Reporting
Under-Battery Voltage Lockout Protection
for the TPIC44L01 and TPIC44L02
D
D
D
D
D
D
D
Asynchronous Open-Drain Fault Flag
Device Output Can be Wire ORed with
Multiple Devices
Fault Status Returned Through Serial
Output Terminal
Internal Global Power-On Reset of Device
and External RESET Terminal
High-Impedance CMOS-Compatible Inputs
With Hysteresis
TPIC44L01 and TPIC44L03 Disables the
Gate Output When a Shorted-Load Fault
Occurs
TPIC44L02 Transitions the Gate Output to a
Low-Duty-Cycle PWM Mode When a
Shorted-Load Fault Occurs
description
The TPIC44L01, TPIC44L02, and TPIC44L03 are
low-side predrivers that provide serial and parallel
input interfaces to control four external FET power
switches such as offered in the TI TPIC family of
power arrays. These devices are designed
primarily for low-frequency switching, inductive
load applications such as solenoids and relays.
Fault status for each channel is available in a
serial-data format. Each driver channel has
independent off-state open-load detection and
on-state shorted-load/short-to-battery detection.
Battery overvoltage and undervoltage detection
and shutdown is provided on the TPIC44L01/L02.
On the TPIC44L03 driver, only over-battery-voltage shutdown is provided Each channel also
provides inductive-voltage-transient protection
for the external FET.
DB PACKAGE
(TOP VIEW)
FLT
VCOMPEN
VCOMP
IN0
IN1
IN2
IN3
CS
SDO
SDI
SCLK
VCC
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
VBAT
N/C
RESET
DRAIN0
GATE0
DRAIN1
GATE1
GATE2
DRAIN2
GATE3
DRAIN3
GND
These devices provide control of output channels through a serial input interface or a parallel input interface.
A command to enable the output from either interface enables the respective channels gate output to the
external FET. The serial interface is recommended when the number of signals between the control device and
the predriver must be minimized and the speed of operation is not critical. In applications where the predriver
must respond very quickly or asynchronously, the parallel input interface is recommended.
For serial operation, the control device must transition CS from high to low to activate the serial input interface.
When this occurs, SDO is enabled, fault data is latched into the serial interface, and the fault flag is refreshed.
Data is clocked into the serial registers on low-to-high transitions of SCLK through SDI. Each string of data must
consist of at least four-bits of data. In applications where multiple devices are cascaded together, the string of
data must consist of4 bits for each device. A high data bit turns the respective output channel on and a low data
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TI is a trademark of Texas Instruments Incorporated.
Copyright  1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
TPIC44L01, TPIC44L02, TPIC44L03
4-CHANNEL SERIAL AND PARALLEL LOW-SIDE PRE-FET DRIVER
SLIS062A – NOVEMBER 1996 – REVISED SEPTEMBER 1997
bit turns it off. Fault data for the device is clocked out of SDO as serial input data is clocked into the device. Fault
data consists of fault flags for shorted-load and open-load flags (bits 0–3) for each of the four output channels.
A high bit in the fault data indicates a fault and a low bit indicates that no fault is present for that channel. Fault
register bits are set or cleared asynchronously to reflect the current state of the hardware. A fault must be
present when CS is transitioned from high to low to be captured and reported in the serial fault data. New faults
cannot be captured in the serial register when CS is low. CS must be transitioned high after all of the serial data
has been clocked into the device. A low-to-high transition of CS transfers the last four bits of serial data to the
output buffer puts SDO in a high-impedence state and clears and re-enables the fault register. The
TPIC44L01/L02/L03 was designed to allow the serial input interfaces of multiple devices to be cascaded
together to simplify the serial interface to the controller. Serial input data flows through the device and is
transferred out SDO following the fault data in cascaded configurations.
For parallel operation, data is transferred directly from the parallel input interface IN0-IN3 to the respective
GATE(0–3) output asynchronously. SCLK or CS is not required for parallel control. A 1 on the parallel input turns
the respective channel on, where a 0 turns it off. Note that either the serial input interface or the parallel input
interface can enable a channel. Under parallel operation, fault data must still be collected through the serial data
interface.
The predrivers monitor the drain voltage for each channel to detect shorted-load or open-load fault conditions
in the the on and off states respectively. These devices offer the option of using an internally generated
fault-reference voltage or an externally supplied fault-reference voltage through VCOMP for fault detection. The
internal fault reference is selected by connecting VCOMPEN to GND and the external reference is selected by
connecting VCOMPEN to VCC. The drain voltage is compared to the fault reference when the channel is turned
on to detect shorted-load conditions and when the channel is off to detect open-load conditions. When a shorted
fault occurs using the TPIC44L01 or the TPIC44L03, the channel is turned off and a fault flag is sent to the control
device as well as to the serial fault register bits. If a fault occurs while using the TPIC44L02, the channel
transitions into a low-duty-cycle, pulse-width-modulated (PWM) signal as long as the fault is present.
Shorted-load fault conditions must be present for at least the shorted-load deglitch time, t(STBDG), to be flagged
as a fault. A fault flag is sent to the control device as well as the serial fault register bits. More detail on fault
detection operation is presented in the device operation section of this data sheet.
These devices provide protection from over-battery voltage and under-battery voltage conditions irrespective
of the state of the output channels. When the battery voltage is greater than the overvoltage threshold or less
than the undervoltage threshold, all channels are disabled and a fault flag is generated. Battery-voltage faults
are not reported in the serial fault data. The outputs return to normal operation once the battery-voltage fault
has been corrected. When an over-battery/under-battery voltage condition occurs, the device reports the
battery fault, but disables fault reporting for open- and shorted-load conditions. Fault reporting for open- and
shorted-load conditions are re-enabled after the battery fault condition has been corrected.
These devices provide inductive transient protection on all channels. The drain voltage is clamped to protect
the FET. The clamp voltage is defined by the sum of VC and turn-on voltage of the external FET. The predriver
also provides a gate-to-source voltage (VGS) clamp to protect the gate-source terminals of the power FET from
exceeding their rated voltages. An external active low RESET is provided to clear all registers and flags in the
device. GATE(0–3) outputs are disabled after RESET has been pulled low.
These devices provide pulldown resistors on all inputs except CS and RESET. A pullup resistor is used on CS
and RESET.
2
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• DALLAS, TEXAS 75265
TPIC44L01, TPIC44L02, TPIC44L03
4-CHANNEL SERIAL AND PARALLEL LOW-SIDE PRE-FET DRIVER
SLIS062A – NOVEMBER 1996 – REVISED SEPTEMBER 1997
schematic diagram
4
Fault Logic
RST
SDI
SCLK
SDO
Serial Register
VCC
Parallel Register
CS
4
RST
IN 0
IN 1
IN 2
IN 3
FLT
PREZ
GND
D
Q
RST
DRAIN 0
DRAIN 1
DRAIN 2
DRAIN 3
4
STB and Open-Load Fault
Protection
VCOMPEN
OSC
S
BIAS
2
B
VCOMP
A
Gate
Drive Block
VBAT
Vbg
OVLO†
UVLO
GATE 0
GATE 1
GATE 2
GATE 3
VCC
RST
RESET
† OVLO not on TPIC44L03
RST
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
TPIC44L01, TPIC44L02, TPIC44L03
4-CHANNEL SERIAL AND PARALLEL LOW-SIDE PRE-FET DRIVER
SLIS062A – NOVEMBER 1996 – REVISED SEPTEMBER 1997
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
Chip select. A high to low transition on CS enables SDO, latches fault data into the serial interface, and
refreshes FLT. When CS is high, the fault registers can change fault status. On the falling edge of CS, fault data
is latched into the serial output register and transferred using SDO and SCLK. On a low to high transition of
CS, serial data is latched in to the output control register.
CS
8
I
DRAIN0
21
I
DRAIN1
19
DRAIN2
16
DRAIN3
14
FLT
1
I
GATE0
20
O
GATE1
18
GATE2
17
GATE3
15
GND
13
I
IN0
4
I
IN1
5
IN2
6
FET drain inputs. DRAIN0 through
g DRAIN3 are used for both open-load and short-circuit fault detection at the
drain of the external FETs. They are also used for inductive transient protection.
Fault flag. FLT is a logic level open-drain output that provides a real-time fault flag for shorted-load/
open-load/over-battery voltage/under-battery voltage faults. The device can be ORed with FLT terminals on
other devices for interrupt handling. FLT requires an external pullup resistor.
Gate drive output. GATE0 through
g GATE3 outputs are derived from the VBAT supplyy voltage.
g Internal clamps
prevent voltages on these nodes from exceeding the VGS rating on most FETs.
Ground and substrate
Parallel g
gate driver. IN0 through
gate predrive circuitry.
g IN3 are real-time controls for the g
y Theyy are CMOS
compatible with hysteresis.
IN3
7
RESET
22
I
Reset. A high-to-low transition of RESET clears all registers and flags. Gate outputs turn off and the FLT flag
is cleared.
SCLK
11
I
Serial clock. SCLK clocks the shift register. Serial data is clocked into SDI and serial fault data is clocked out
of SDO on the falling edge of the serial clock.
SDI
10
I
Serial data input. Output control data is clocked into the serial register through SDI. A 1 on SDI commands a
particular gate output on and a 0 turns it off.
SDO
9
O
Serial data output. SDO is a 3-state output that transfers fault data to the controlling device. It also passes serial
input data to the next stage for cascaded operation. SDO is taken to a high-impedance state when CS is in a
high state.
VBAT
VCC
24
I
Battery supply voltage
12
I
Logic supply voltage
VCOMPEN
2
I
Fault reference voltage select. VCOMPEN selects the internally generated fault reference voltage (0) or an
external fault reference (1) to be used in the shorted- and open-load fault detection circuitry.
VCOMP
3
I
Fault reference voltage. VCOMP provides an external fault reference voltage for the shorted-load and
open-load fault detection circuitry.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPIC44L01, TPIC44L02, TPIC44L03
4-CHANNEL SERIAL AND PARALLEL LOW-SIDE PRE-FET DRIVER
SLIS062A – NOVEMBER 1996 – REVISED SEPTEMBER 1997
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
Battery supply voltage range, VBAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 60 V
Input voltage range,VI (at any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
Output voltage range, VO (SDO and FLT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
Drain-to-source voltage, VDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 60 V
Output voltage, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 15 V
Operating case temperature range, TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to + 125°C
Thermal resistance, junction to ambient, RθJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135°C/W
Maximum junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to + 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND.
recommended operating conditions
Logic supply voltage, VCC
Battery supply voltage, VBAT
MIN
NOM
MAX
4.5
5
5.5
V
24
V
VCC
0.15 VCC
V
8
High-level input voltage, VIH
0.85 VCC
Low-level input voltage, VIL
0
Setup time, SDI high before SCLK rising edge, tsu (see Figure 5)
10
Hold time, SDI high after SCLK rising edge, th (see Figure 5)
10
Case temperature, TC
–40
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
UNIT
V
ns
ns
125
°C
5
TPIC44L01, TPIC44L02, TPIC44L03
4-CHANNEL SERIAL AND PARALLEL LOW-SIDE PRE-FET DRIVER
SLIS062A – NOVEMBER 1996 – REVISED SEPTEMBER 1997
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
IBAT
ICC
TEST CONDITIONS
Supply current, VBAT
All outputs off,
Supply current, VCC
All outputs off,
V(turnon)
Turn-on voltage, logic operational, VCC
Vbat = 5.5 V,
Check output functionality
V(ovsd)
Vhys(ov)
Over-battery-voltage shutdown
V(uvsd)
Over-battery-voltage reset hysteresis
Under-battery-voltage shutdown,
(TPIC44L01/L02 only)
VBAT = 12 V
VBAT = 5.5 V
Gate disabled,
disabled
See Figure 16
disabled
Gate disabled,
See Figure 17
MIN
TYP
MAX
UNIT
300
500
700
µA
1
2.6
4.2
mA
2.6
3.5
4.4
V
32
34
36
V
0.5
1
1.5
V
4.1
4.8
5.4
V
100
200
300
mV
7
13.5
V
5
7
V
Vhys(uv)
Under-battery-voltage reset hysteresis,
(TPIC44L01/L02 only)
VG
Gate drive voltage
IO(H)
Maximum current output for drive terminals,
pullup
VOUT = GND
0.5
1.2
2.5
mA
IO(L)
Maximum current output for drive terminals,
pulldown
VOUT = 7 V
0.5
1.2
2.5
mA
V(stb)
Short-to-battery/shorted-load/open-load
detection voltage
VCOMPEN = L
1.1
1.25
1.4
V
40
100
150
mV
VCOMPEN = L
1.1
1.25
1.4
V
40
100
150
mV
30
60
80
µA
8 V < VBAT < 24,
5.5 V < VBAT < 8 V,
IO = 100 µA
IO = 100 µA
Vhys(stb)
VD(open)
Short-to-battery hysteresis
Vhys(open)
II(open)
Open-load hysteresis
II(PU)
II(PD)
Input pullup current (CS)
Input pulldown current
VCC = 5 V,
VCC = 5 V,
Vhys
Input voltage hysteresis
VCC = 5 V
VO(SH)
VO(SL)
High-level serial output voltage
IO = 1 mA
IO = 1 mA
IOZ(SD)
VO(CFLT)
3-state current serial-data output
Fault-interrupt output voltage
VCC = 0 to 5.5V
IO = 1 mA
VI(COMP)
VC
Fault-external reference voltage
VCOMPEN = H
Output clamp voltage, (TPIC44L01/L02 only)
dc < 1%,
tw = 100 µs
47
VC
Output clamp voltage, (TPIC44L03 only)
dc < 1%,
tw = 100 µs
47
6
Open-load off-state detection voltage threshold
Open-load off-state detection current
Low-level serial output voltage
POST OFFICE BOX 655303
VIN = 0
VIN = 5 V
0.6
10
µA
10
µA
0.85
1.1
0.1
0.4
V
1
10
µA
0.1
0.5
V
3
V
55
63
V
53.5
60
V
0.8 VCC
-10
V
1
• DALLAS, TEXAS 75265
V
TPIC44L01, TPIC44L02, TPIC44L03
4-CHANNEL SERIAL AND PARALLEL LOW-SIDE PRE-FET DRIVER
SLIS062A – NOVEMBER 1996 – REVISED SEPTEMBER 1997
switching characteristics, VCC = 5 V, Vbat = 12 V, TC = 25°C
PARAMETER
TEST CONDITIONS
t(STBFM)
Short-to-battery/shorted-load/open-load
fault mask time
See Figures 14 and 15
t(STBDG)
Short-to-battery/shorted-load deglitch time
See Figure 14
tPLH
Propagation turn-on delay time, CS or
IN0-IN3 to GATE0-GATE3
C(gate) = 400 pF,
tPHL
Propagation turn-off delay time, CS or
IN0-IN3 to GATE0-GATE3
tr1
MIN
TYP
MAX
UNIT
60
µs
8
µs
See Figure 1
4
µs
C(gate) = 400 pF,
See Figure 2
3.5
µs
Rise time GATE0–GATE3
C(gate) = 400 pF,
See Figure 3
3.5
µs
tf1
Fall time, GATE0–GATE3
C(gate) = 400 pF,
See Figure 4
3
f(SCLK)
trf(SB)
Serial clock frequency
Refresh time, short-to-battery
TPIC46L01 only,
See Figure 14
10
ms
tw
Refresh pulse width, short-to-battery
TPIC46L01 only,
See Figure 14
68
µs
td1
Setup time, CS↓ to ↑SCLK
See Figure 5
10
ns
tpd1
Propagation delay time, CS↓ to SDO valid
RL = 10 kΩ,
See Figure 6
40
ns
tpd2
Propagation delay time, SCLK↓ to SDO
valid
See Figure 6
20
ns
tpd3
Propagation delay time, CS↑ to SDO
3-state
RL = 10 kΩ,
See Figure 7
CL = 50 pF,
2
µs
tr2
Rise time, SDO 3-state to SDO valid
RL = 10 kΩ to GND,
CL = 200 pF,
Over-battery fault,
See Figure 8
30
ns
tf2
Fall time, SDO 3-state to SDO valid
RL = 10 kΩ to VCC,
CL = 200 pF,
No faults,
See Figure 9
20
ns
tr3
Rise time, FLT
RL = 10 kΩ,
See Figure 10
CL = 50 pF,
1.2
µs
tf3
Fall time, FLT
RL = 10 kΩ,
See Figure 11
CL = 50 pF,
15
ns
µs
10
CL = 200 pF,
MHz
50%
IN0– IN3
or
CS or IN0–IN3
CS
50%
50%
tPLH
tPHL
90%
GATE0– GATE3
GATE0–GATE3
Figure 1
10%
Figure 2
tr1
90%
GATE0–GATE3
tf1
GATE0–GATE3
10%
90%
10%
Figure 3
Figure 4
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• DALLAS, TEXAS 75265
7
TPIC44L01, TPIC44L02, TPIC44L03
4-CHANNEL SERIAL AND PARALLEL LOW-SIDE PRE-FET DRIVER
SLIS062A – NOVEMBER 1996 – REVISED SEPTEMBER 1997
SCLK
SCLK
td1
CS
CS
th
tpd1
tsu
SDO
SDI
tpd2
3-State
Figure 5
Figure 6
50%
CS
SDO
90%
3-STATE
10%
tpd3
SDO
tr2
3-State
Figure 7
Figure 8
tf2
SDO
3-STATE
tr3
90%
10%
Figure 9
Figure 10
tf3
90%
FLT
10%
Figure 11
8
90%
FLT
10%
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TPIC44L01, TPIC44L02, TPIC44L03
4-CHANNEL SERIAL AND PARALLEL LOW-SIDE PRE-FET DRIVER
SLIS062A – NOVEMBER 1996 – REVISED SEPTEMBER 1997
PRINCIPLES OF OPERATION
serial data operation
The TPIC44L01, TPIC44L02, and TPIC44L03 offer serial input interface to the microcontroller to transfer control
data to the predriver and fault data back to the controller. The serial input interface consists of:
•
•
•
•
SCLK – Serial clock
CS
– Chip select
SDI
– Serial data input
SDO
– Serial data output
Serial data is shifted into the least significant bit (LSB) of the SDI shift register on the rising edge of the first SCLK
after CS has transitioned from 1 to 0. Four clock cycles are required to shift the first bit from the LSB to the most
significant bit (MSB) of the shift register. Four clock cycles must occur before CS transitions high for proper
control of the outputs. Less than four clock cycles result in fault data being latched into the output control buffer.
Eight bits of data can be shifted into the device, but the first 4 bits shifted out are always the fault data and the
last 4 bits shifted in are always the output control data. A low-to-high transition on CS latches the contents of
the serial shift register into the output control register. A logic 0 input to SDI turns the corresponding parallel
output off and a logic 1 input turns the output on (see Figure 12).
1
2
3
4
SCLK
CS
SDI
New Data
GATE3 ON
GATE2 ON
GATE1 OFF
GATE0 OFF
Output Control
Register Data
SDO
Present Output Data
3-State
FLT3
FLT2
FLT1
New Data
FLT0
IN3
3-State
(a) 4-Bit Serial Word Example
Figure 12
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• DALLAS, TEXAS 75265
9
TPIC44L01, TPIC44L02, TPIC44L03
4-CHANNEL SERIAL AND PARALLEL LOW-SIDE PRE-FET DRIVER
SLIS062A – NOVEMBER 1996 – REVISED SEPTEMBER 1997
PRINCIPLES OF OPERATION
1
2
3
4
5
6
7
8
SCLK
CS
SDI
Don’t Care
New Data
GATE3 ON
GATE2 ON
GATE1 OFF
GATE0 OFF
Output Control
Register Data
SDO 3-State
Present Output Data
FLT3
FLT2
FLT1
FLT0
NA
NA
New Data
NA
NA
IN3
3-State
(b) 8-Bit Serial Word Example (Single Predriver)
1
2
3
4
5
6
7
8
SCLK
CS
SDI
IN 7
IN 6
IN 5
IN 4
IN 3
IN 2
IN 1
IN 0
NA
FLT5
FLT4
FLT3
FLT2
FLT1
FLT0
IN7
New Data
GATE7–GATE4 (2nd stage)
GATE3–GATE0 (1st stage)
SDO 3-State
FLT7
FLT6
(c) 8-Bit Serial Word Example (Cascade: Two Predrivers)
Figure 12 (continued)
10
POST OFFICE BOX 655303
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3-State
TPIC44L01, TPIC44L02, TPIC44L03
4-CHANNEL SERIAL AND PARALLEL LOW-SIDE PRE-FET DRIVER
SLIS062A – NOVEMBER 1996 – REVISED SEPTEMBER 1997
PRINCIPLES OF OPERATION
serial data operation (continued)
Data is shifted out of SDO on the falling edge of SCLK. The MSB of fault data is available after CS is transitioned
low. The remaining 3 bits of fault data are shifted out in the following three clock cycles. Fault data is latched
into the serial register when CS is transitioned low. A fault must be present on the high to low transition of CS
to be captured by the device. The CS input must be transitioned to a high state after the last bit of serial data
has been clocked into the device. The rising edge of CS inhibits SDI, puts SDO into a high-impedance state,
latches the 4 bits of serial data into the output control register, and clears and re-enable the serial fault registers
(see Figure 13). When a shorted-load condition occurs with the TPIC44L01 or TPIC44L03, then the controller
must disable and re-enable the channel to clear the fault register and FLT. The TPIC44L02 automatically retries
the output and the fault clears after the fault condition has been corrected.
1
2
3
4
SCLK
CS
SDO
3-State
FLT3
FLT2
FLT1
FLT0
IN3
3-State
Figure 13
parallel input data operation
In addition to the serial interface, the TPIC44L01, TPIC44L02, and TPIC44L03 also provides a parallel interface
to the microcontroller. The output turns on when either the parallel or the serial interface commands it to turn
on. The parallel data terminals are real-time control inputs for the output drivers. SCLK and CS are not required
to transfer parallel input data to the output buffer. Fault data must be read over the serial data bus as described
in the serial data operation section of this data sheet. The parallel input must be transitioned low and then high
to clear and re-enable a gate output after it has been disabled due to a shorted-load fault condition.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
11
TPIC44L01, TPIC44L02, TPIC44L03
4-CHANNEL SERIAL AND PARALLEL LOW-SIDE PRE-FET DRIVER
SLIS062A – NOVEMBER 1996 – REVISED SEPTEMBER 1997
PRINCIPLES OF OPERATION
chipset performance under fault conditions
The TPIC44L01, TPIC44L02, TPIC44L03, and power FET arrays are designed for normal operation over a
battery-voltage range of 8 V to 24 V with load-fault detection from 4.8 V to 34 V. The TPIC44L01, TPIC44L02,
and TPIC44L03 offer on-board fault detection to handle a variety of faults that may occur within a system. The
circuits primary function is to prevent damage to the load and the power FETs in the event that a fault occurs.
Note that unused DRAIN0-DRAIN3 inputs must be connected to VBAT through a pullup resistor to prevent false
reporting of open-load fault conditions. The circuitry detects the fault, shuts off the output to the FET, and reports
the fault to the microcontroller. The primary faults under consideration are:
1.
2.
3.
4.
Shorted-load
Open-load
Over-battery voltage shutdown
Under-battery voltage shutdown (TPIC44L01 and TPIC44L02 only)
NOTE:
An undervoltage fault may be detected when VCC and VBAT are applied to the device. The controller
should initialize the fault register after power up to clear any false fault reports.
shorted-load fault condition
The TPIC44L01, TPIC44L02, and TPIC44L03 monitor the drain voltage of each channel to detect shorted-load
conditions. The onboard deglitch timer starts running when the gate output to the power FET transitions from
the off state to the on state. The timer provides a 60-µs deglitch time, t(STBFM), to allow the drain voltage to
stabilize after the power FET has been turned on. The deglitch time is only enabled for the first 60-µs after the
FET has been turned on. After the deglitch delay time, the drain voltage is checked to verify that it is less than
the fault reference voltage. When it is greater than the reference voltage for at least the short-to-battery deglitch
time, t(STBDG), FLT flags the microcontroller that a fault condition exists and the gate output is automatically shut
off (TPIC44L01 and TPIC44L03) until the error condition has been corrected.
An overheating condition on the FET occurs when the controller continually tries to re-enable the output under
shorted-load fault conditions. When a shorted-load fault is detected using the TPIC44L02, the gate output is
transitioned into a low-duty-cycle, PWM signal to to protect the FET from overheating. The PWM rate is defined
as t(SB) and the pulse width is defined as tw. The gate output remains in this state until the fault has been
corrected or until the controller disables the gate output.
The microcontroller can read the serial port on the predriver to isolate which channel reported the fault condition.
Fault bits 0-3 distinguish faults for each of the output channels. When a shorted-load condition occurs with the
TPIC44L01 or TPIC44L03, the controller must disable and re-enable the channel to clear the fault register and
FLT. The TPIC44L02 automatically retries the output and the fault clears after the fault condition has been
corrected. Figure 14 illustrates operation after a gate output has been turned on. The gate to the power FET
is turned on and the deglitch timer starts running. Under normal operation T1 turns on and the drain operates
below the reference point set at U1. The output of U1 is low and a fault condition is not flagged.
12
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPIC44L01, TPIC44L02, TPIC44L03
4-CHANNEL SERIAL AND PARALLEL LOW-SIDE PRE-FET DRIVER
SLIS062A – NOVEMBER 1996 – REVISED SEPTEMBER 1997
PRINCIPLES OF OPERATION
External
TPIC44L01/L02
VBAT
Load
T1
+
_
1.25 V
Input From
TPIC44L01/L02
N-Channel
U1
FLT
Deglitch
SHORTED-LOAD TPIC44L01 and TPIC44L03
NORMAL
Input
Input
GATE0–
GATE3
GATE0–
GATE3
Glitches
Glitches
DRAIN0–
DRAIN3
DRAIN0–
DRAIN3
t(STBFM)
FLT
FLT
t(STBDG)
t(STBFM)
SHORTED-LOAD TPIC44L02
Input
GATE0–
GATE3
Glitches
t(SB)
tw
DRAIN0–
DRAIN3
GATE0–
GATE3
FLT
t(STBDG)
t(STBFM)
Figure 14
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
13
TPIC44L01, TPIC44L02, TPIC44L03
4-CHANNEL SERIAL AND PARALLEL LOW-SIDE PRE-FET DRIVER
SLIS062A – NOVEMBER 1996 – REVISED SEPTEMBER 1997
PRINCIPLES OF OPERATION
open load
The TPIC44L01, TPIC44L02, and TPIC44L03 monitor the drain of each power FET for open circuit conditions
that may exist. The 60-µA current source is provided to monitor open load fault conditions. Open-load faults are
only detected when the power FET is turned off. When load impedance is open or substantially high, the 60-µA
current source has adequate drive to pull the drain of T1 below the fault reference threshold on the detection
circuit. Unused DRAIN0–DRAIN3 inputs must be connected to VBAT through a pull-up resistor to prevent false
reporting of open-load fault conditions. The on-board deglitch timer starts running when the TPIC44L01,
TPIC44L02, and TPIC44L03 gate output to the power FET transitions to the off state. The timer provides a 60-µs
deglitch time, t(STBFM) to allow the drain voltage to stabilize after the power FET has been turned off. The deglitch
time is only enabled for the first 60-µs after the FET has been turned off. After the deglitch delay time, the drain
is checked to verify that it is greater than the fault reference voltage. When it is less than the reference voltage,
a fault is flagged to the microcontroller through FLT that an open-load fault condition exists. The microcontroller
can then read the serial port on the TPIC44L01, TPIC44L02, and TPIC44L03 to isolate which channel reported
the fault condition. Fault bits 0–3 distinguish faults for each of the output channels. Figure 15 illustrates the
operation of the open-load detection circuit. This feature provides useful information to the microcontroller to
isolate system failures and warn the operator that a problem exists. Examples of such applications would be
a warning that a light bulb filament may be open, solenoid coils may be open, etc.
External
TPIC44L01/L02/L03
VBAT
Load
U1
60 µA
T1
Input From
TPIC44L01/L02/L03
1.25 V
N-Channel
GATE0–
GATE3
OPEN-LOAD
Input
NORMAL
GATE0–
GATE3
Glitches
DRAIN0–
DRAIN3
FLT
FLT
Deglitch
NORMAL
Input
+
_
DRAIN0–
DRAIN3
FLT
t(STBFM)
t(STBFM)
Figure 15
14
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPIC44L01, TPIC44L02, TPIC44L03
4-CHANNEL SERIAL AND PARALLEL LOW-SIDE PRE-FET DRIVER
SLIS062A – NOVEMBER 1996 – REVISED SEPTEMBER 1997
PRINCIPLES OF OPERATION
over-battery-voltage shutdown
The TPIC44L01,TPIC44L02, and TPIC44L03 monitor the battery voltage to prevent the power FETs turning on
in the event that the battery voltage is too high. This condition may occur due to voltage transients resulting from
a loose battery connection. The TPIC44L01, TPIC44L02, and TPIC44L03 turns the power FET off when the
battery voltage is above 34 volts to prevent possible damage to the load and the FET. GATE(0–3) output goes
back to normal operation after the overvoltage condition has been corrected. An over-battery-voltage fault is
flagged to the controller through FLT. The over-battery-voltage fault is not reported in the serial fault word. When
an overvoltage condition occurs, the device reports the battery fault, but disables fault reporting for open and
shorted-load conditions. Fault reporting for open and shorted-load conditions are re-enabled after the battery
fault condition has been corrected. When the fault condition is removed before the CS signal transitions low,
the fault condition is not captured in the serial fault register. The fault flag resets on a high-to-low transition of
CS provided no other faults are present in the device. Figure 16 illustrates the operation of the
over-battery-voltage detection circuit.
VBAT
34 V
VBAT
+
_
U1
Output Disable
34 V
12 V
33 V
GATE0–GATE3
Figure 16
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
15
TPIC44L01, TPIC44L02, TPIC44L03
4-CHANNEL SERIAL AND PARALLEL LOW-SIDE PRE-FET DRIVER
SLIS062A – NOVEMBER 1996 – REVISED SEPTEMBER 1997
PRINCIPLES OF OPERATION
under-battery-voltage shutdown (TPIC44L01 and TPIC44L02 only)
The TPIC44L01 and TPIC44L02 monitor the battery voltage to prevent the power FETs from being turned on
in the event that the battery voltage is too low. When the battery voltage is below 4.8 volts, then GATE0–GATE3
may not provide sufficient gate voltage to the power FETs to minimize the on-resistance that could result in a
thermal stress on the FET. The output goes back to normal operation after the undervoltage condition has been
corrected. An under-battery-voltage fault is flagged to the controller through FLT. The under-battery voltage fault
is not reported in the serial fault word. When an under-battery-voltage condition occurs, the device reports the
battery fault but disables fault reporting for open- and shorted-load conditions. When the fault condition is
removed before the CS signal transitions low, the fault condition is not captured in the serial fault register. The
fault flag resets on a high-to-low transition of CS provided no other faults are present in the device. Figure 17
illustrates the operation of the under-battery voltage-detection circuit.
VBAT
_
4.8 V
U1
Output Disable
+
12 V
VBAT
5V
4.8 V
GATE0–GATE3
Figure 17
16
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPIC44L01, TPIC44L02, TPIC44L03
4-CHANNEL SERIAL AND PARALLEL LOW-SIDE PRE-FET DRIVER
SLIS062A – NOVEMBER 1996 – REVISED SEPTEMBER 1997
PRINCIPLES OF OPERATION
inductive voltage transients
A typical application for the predriver/power FET circuit is to switch inductive loads. When an inductive load is
switched off, a large voltage spike can occur. These spikes can exceed the maximum VDS rating for the external
FET and damage the device when the proper protection is not in place. The FET can be protected from these
transients through a variety of methods using external components. The TPIC44L01, TPIC44L02, and
TPIC44L03 offer that protection in the form of a zener diode stack connected between the DRAIN input and
GATE output (seeFigure 18). Zener diode Z1 turns the FET on to dissipate the transient energy. GATE diode
Z2 is provided to prevent the gate voltage from exceeding 13 volts during normal operation and transient
protection.
TPIC44L01/L02/L03
External
DRAIN
Z1
LOAD
VBAT
55 V
T1
GATE
Z2
Power FET
13 V
Figure 18
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
17
TPIC44L01, TPIC44L02, TPIC44L03
4-CHANNEL SERIAL AND PARALLEL LOW-SIDE PRE-FET DRIVER
SLIS062A – NOVEMBER 1996 – REVISED SEPTEMBER 1997
PRINCIPLES OF OPERATION
external fault reference input
The TPIC44L01, TPIC44L02, and TPIC44L03 compare each channel drain voltage to a fault reference to detect
shorted-load and open-load conditions. The user has the option of using the internally generated 1.25-V fault
reference or providing an external reference voltage through VCOMP. The internal reference is selected by connecting VCOMPEN to GND and VCOMP is selected by connecting VCOMPEN to VCC (see Figure 19). Proper
layout techniques should be used in the grounding network for the VCOMP circuit on the TPIC44L01,
TPIC44L02, and TPIC44L03. The ground for the predriver and VCOMP network should be connected to a Kelvin ground if available; otherwise, they should make single-point contact back to the power ground of the FET
array. Improper grounding techniques can result in inaccuracies in detecting faults.
External
TPIC44L01/L02/L03
DRAIN3
+
_
DRAIN0
+
_
U1
1.25 V
VCOMP
A
M
U
X
VCOMPEN
Deglitch
VCOMPEN
1.25 V
VCOMP
0
1
Figure 19
18
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
FLT
TPIC44L01, TPIC44L02, TPIC44L03
4-CHANNEL SERIAL AND PARALLEL LOW-SIDE PRE-FET DRIVER
SLIS062A – NOVEMBER 1996 – REVISED SEPTEMBER 1997
MECHANICAL DATA
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
28 TERMINAL SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,15 NOM
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°– 8°
1,03
0,63
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
8
14
16
20
24
28
30
38
A MAX
3,30
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
2,70
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 / C 10/95
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
19
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