® STV6618 Video Switch Matrix for DVDs Main Features ■ I²C Bus Control ■ 5 Y/CVBS Inputs, 3 Y/CVBS Outputs ■ 3 C Inputs, 1 C Output ■ 2 RGB/YPrPb Inputs, 1 RGB/YPrPb Output ■ 6 dB Gain on all 150 Ω Buffer Outputs ■ Integrated 150 Ω Buffers ■ Video Muting on all Outputs ■ Bottom Clamp on all CVBS/Y, Average Clamp on C Inputs, Bottom Clamp on RGB, Sync-tip Clamp on PrPb signals ■ Bandwidth: 17 MHz ■ Crosstalk: 50 dB TQFP44 (10 x 10 x 1.4 mm) (Thin Full Plastic Quad Flat Pack) Description ORDER CODE: STV6618 The STV6618 is a highly integrated I²C buscontrolled video switch matrix, optimized for use in recordable Digital Video Disk applications or DVD players. It is adapted to video signals with 1H and 2H formats video routings. It provides required for connections to two external devices (Europe 2 SCARTs), internal tuners, digital encoders and recorders. September 2003 1/24 STV6618 Table of Contents Chapter 1 GENERAL OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.1 Pin Connections .................................................................................................................. 3 1.2 Pin Description ................................................................................................................... 4 Chapter 2 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2.1 Absolute Maximum Ratings ................................................................................................ 7 2.2 Thermal Data ...................................................................................................................... 7 2.3 Recommended Operating Conditions .................................................................................. 7 2.4 Video Section Characteristics .............................................................................................. 8 2.5 Fast Blanking Section Characteristics ................................................................................. 9 2.6 Chroma Section Characteristics ......................................................................................... 10 2.7 Digital Outputs .................................................................................................................... 10 2.8 I²C Bus Characteristics ...................................................................................................... 11 Chapter 3 I²C BUS SELECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 3.1 I²C Bus Addresses ............................................................................................................. 12 3.2 Power-on Reset: Bus Register Initial Conditions ............................................................... 15 Chapter 4 INPUT/OUTPUT GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Chapter 5 APPLICATION DIAGRAMS Chapter 6 PACKAGE MECHANICAL DATA Chapter 7 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 2/24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 STV6618 GENERAL OVERVIEW 1 GENERAL OVERVIEW 1.1 Pin Connections Y/CVBSOUT_TV VCCB3 R/PR/COUT_TV VCCB2 G/YOUT_TV C_GATE B/PBOUT_TV GNDB Y/CVBSOUT_AUX VCCB 1 COUT_AUX Figure 1: Pinout Diagram 33 32 31 30 29 28 27 26 25 24 23 34 35 36 37 38 39 40 41 42 43 44 22 21 20 19 18 17 16 15 14 13 12 GNDB_REC Y/CVBSOUT_REC VCCB_REC Y/CVBSIN_AUX DIGOUT6 R/PR/CIN_AUX DIGOUT5 G/YIN_AUX DIGOUT4 B/PBIN_AUX GND2 1 2 3 4 5 6 7 8 9 10 11 Y/CVBSIN_TUN DIGOUT3 GND1 CVBSIN_ENC DECV CIN_ENC YIN_ENC VCC R/PR/CIN_ENC G/YIN_ENC B/PBIN_ENC FBOUT_TV FBIN_AUX VDD SCL SDA GNDD CIN_TV Y/CVBSIN_TV DIGOUT1 CIN_TUN DIGOUT2 3/24 GENERAL OVERVIEW 1.2 STV6618 Pin Description Pin No. Symbol 1 Y/CVBSIN_TUN 2 DIGOUT3 3 GND1 4 CVBSIN_ENC CVBS Input from Encoder 5 DECV Video decoupling capacitor 6 CIN_ENC Chroma Input from Encoder 7 YIN_ENC Y Input from Encoder 8 VCC 9 R/PR/CIN_ENC 10 G/YIN_ENC Green or Y Input from Encoder 11 B/PBIN_ENC Blue or Pb Input from Encoder 12 GND2 13 B/PBIN_AUX 14 DIGOUT4 15 G/YIN_AUX 16 DIGOUT5 17 R/PR/CIN_AUX 18 DIGOUT6 19 Y/CVBSIN_AUX 20 VCCB_REC 21 Y/CVBSOUT_REC 22 GNDB_REC Ground Supply for Recorder Buffer 23 COUT_AUX Chroma Output to Auxiliary (SCART2 or external Cinch) 24 VCCB1 25 Y/CVBSOUT_AUX 26 GNDB 27 B/PBOUT_TV 28 C_GATE 29 G/YOUT_TV 30 VCCB2 31 R/PR/COUT_TV 32 VCCB3 33 Y/CVBSOUT_TV 34 FBOUT_TV Fast Blanking Output to TV (SCART1) 35 FBIN_AUX Fast Blanking Input from Auxiliary (SCART2) 4/24 Description Y/CVBS Input from Tuner Digital Output Pin 3 Ground Supply 1 for Video Inputs +5 V Power Supply for Video Inputs Red or Pr or Chroma Input from Encoder Ground Supply 2 for Video Inputs Blue or Pb Input from Auxiliary (SCART2 or external Cinch) Digital Output Pin 4 Green or Y Input from Auxiliary (SCART2 or external Cinch) Digital Output Pin 5 Red or Pr or Chroma input from Auxiliary (SCART2 or external Cinch) Digital Output Pin 6 Y/CVBS Input from Auxiliary (SCART2 or external Cinch) Video Output Recorder Buffer Supply Pin Y/CVBS Output to Recorder Video Output Buffer Supply Pin Y/CVBS Output to Auxiliary (SCART2 or external Cinch) Ground Supply for Video Buffer Blue or Pb Output to TV (SCART1 or external Cinch) External Transistor Command for Bidirectinnal B/C SCART I/O Green or Y Output to TV (SCART1 or external Cinch) Video Buffer Red or Pr or Chroma Output to TV (SCART1 or external Cinch) Video Output Buffer Supply Pin Y/CVBS Output to TV (SCART1 or external Cinch) STV6618 GENERAL OVERVIEW Pin No. Symbol Description 36 VDD +5 V Digital Power Supply 37 SCL I²C Bus Clock 38 SDA I²C Bus Data 39 GNDD 40 CIN_TV Chroma Input from TV (SCART1 or external Cinch) 41 Y/CVBSIN_TV Y/CVBS Input from TV (SCART1 or external Cinch) 42 DIGOUT1 Digital Output Pin 1 43 CIN_TUN Chroma Input from Tuner 44 DIGOUT2 Digital Output Pin 2 Digital Ground Supply Figure 2: STV6618 Input/Output Diagram R/PR/CIN_ENC R/PR/COUT_TV G/YIN_ENC G/YOUT_TV B/PBIN_ENC B/PBOUT_TV FBOUT_TV Encoder CVBSIN_ENC Y/CVBSOUT_TV CIN_ENC CIN_TV SCART1 TV YIN_ENC Y/CVBSIN_TV Y/CVBSIN_TUN Y/CVBS_REC Recorder COUT_REC STV6618 (TQFP 44) Tuner CIN_TUN C_GATE Transistor DIGOUT1 DIGOUT2 SCART2 (Auxiliary) COUT_AUX DIGOUT3 Y/CVBSOUT_AUX DIGOUT4 DIGOUT5 R/PR/CIN_AUX DIGOUT6 G/YIN_AUX B/PB_AUX FBIN_AUX Y/CVBSIN_AUX 5/24 6/24 Bo. Clamp Bo. Clamp Bo. Clamp Av. Clamp Av. Clamp Y/CVBSIN_AUX CVBSIN_ENC YIN_ENC CIN_TUN CIN_TV Sync Sep. Sync Sep. I²C Bus Bo. / Sync Bot/Sync/Av. Bo. Clamp Bo. / Sync Bot/Sync/Av. Bo. Clamp B/PbIN_ENC R/Pr/CIN_ENC G/YIN_ENC B/PbIN_AUX R/Pr/CIN_AUX G/YIN_AUX CIN_ENC CIN_TV CIN_TUN YIN_ENC CVBSIN_ENC Y/CVBS_AUX Y/CVBS_TV Y/CVBS_TUN SDA SCL FBIN_AUX B/PBIN_ENC R/PR/CIN_ENC G/YIN_ENC B/PBIN_AUX R/PR/CIN_AUX G/YIN_AUX Av. Clamp Bo. Clamp Y/CVBSIN_TV CIN_ENC Bo. Clamp Y/CVBSIN_TUN STV6618 5v 0v FBIN_AUX mute B/PbIN_AUX B/PbIN_ENC mute G/YIN_AUX G/YIN_ENC mute CIN_ENC R/Pr/CIN_AUX R/Pr/CIN_ENC mute CIN__TUN CIN__TV CIN_ENC mute CVBSIN_TUN Y/CVBSIN_TV CVBSIN_ENC YIN_ENC mute Y/CVBSIN_AUX CVBSIN_ENC YIN_ENC mute CVBSIN_TUN Y/CVBSIN_TV Y/CVBSIN_AUX CVBSIN_ENC YIN_ENC 6 dB 6 dB 6 dB 6 dB 6 dB 6 dB 0 dB FBOUT_TV SCART1 B/PbOUT_TV SCART1 G/YOUT_TV SCART1 R/Pr/COUT_TV COUT_AUX SCART2 Y/CVBSOUT_AUX SCART1 Y/CVBSOUT_TV Y/CVBSOUT_REC Recorder GENERAL OVERVIEW STV6618 Figure 3: STV6618 Block Diagram DIGOUT6 DIGOUT5 DIGOUT4 DIGOUT3 DIGOUT2 DIGOUT1 C_GATE STV6618 ELECTRICAL CHARACTERISTICS 2 ELECTRICAL CHARACTERISTICS 2.1 Absolute Maximum Ratings Symbol Unit Digital Section 6 V VCCV Video Section 6 V Voltage at Pin 1 to GND - Video pins - Bus pins, DIGOUT1,2,3 and C_GATE 0, 5.5 0, 5.5 V Voltage at pin DIGOUT4-5-6 0, 13 V ±4 kV 0, +70 °C -20, +150 °C Value Unit 70 °C/W VDIGOUT4-5-6 VESD Maximum ESD voltage allowed. 100 pF capacitor discharged through 1.5 kΩ serial resistor (Human Body Model) TOPER Operating Ambient Temperature TSTG Storage Temperature Thermal Data Symbol RthJA 2.3 Value VDD VI 2.2 Parameter Parameter Junction-ambient Thermal Resistance (Maximum) on a single-layer board Recommended Operating Conditions TAMB = 25 °C, VCCV = 5 V, VDD = 5 V, ROUT_VREC = 4.7 kΩ, ROUT_VBUF = 150 Ω, unless otherwise specified. Output impedances of sources: RGV = 75 Ω. Symbol Parameter Test Conditions Min. Typ. Max. Unit Supply Voltages VDD Digital Supply Voltage 4.75 5.00 5.25 V VCCV Video Operating Supply Voltage 4.75 5.00 5.25 V Active Mode (All channels ON) IDD Digital Supply Current VDD = 5 V, 3.5 5.0 6.5 mA ICCV Total Video Supply Current VCCV = 5 V, No Load 31 45 58 mA Digital Supply Current VDD = 5 V 3.0 4.5 6.0 mA Total Video Supply Current VCC = 5 V 0.5 1.0 mA Standby Mode (All channels OFF) IDD ICCVSTD 7/24 ELECTRICAL CHARACTERISTICS 2.4 STV6618 Video Section Characteristics TAMB = 25 °C, VCCV = 5 V, VDD = 5 V, ROUT_VREC = 4.7 kΩ, ROUT_VBUF = 150 Ω, unless otherwise specified. Output impedances of sources: RGV = 75 Ω. Symbol Parameter Test Conditions Min. Typ. Max. Unit VDCIN_BOT DC Input Level Bottom Sync Pulse 1.9 2.0 2.2 V ICLAMP_BOT Clamping Current, Bottom clamp at VDCIN - 400 mV 1 2 3 mA Input Leakage Current VIN = VDCIN + 1 V, Bottom clamp input 1 5 µA VDCIN_YSYNC DC Input Level Y input, YPrPb mode, Black Level 2.2 2.3 2.5 V VDCIN_SYNC DC Input Level Sync clamp input (Pr,Pb) Sync signal on Y input 2.9 3.0 3.1 V ICLAMP_SYNC Max. Clamping Current during Sync Clamp Sync clamp input (Pr,Pb) at VDCIN - 400 mV ILEAK µA 2 pF CIN Input Capacitance VIN Maximum Input Signal Y/CVBS, RGB Pr, Pb 1.5 1.0 VPP DYN Dynamic Output Signal Y/CVBS, RGB Pr, Pb 3 2 VPP BW Bandwidth at -3 dB Y/CVBS OUT RGB OUT Pr/Pb OUT VIN = 0.7 VIN = 0.7 VIN = 0.7 VPP VPP VPP Video Band Gain Spread (15 kHz to 5 MHz) Y/CVBS OUT RGB OUT Pr/Pb OUT VIN = 1 VIN = 1 VIN = 0.7 VPP VPP VPP Flatness 14 14 14 17 17 17 MHz ±0.5 ±0.5 ±0.5 dB CTi Crosstalk Isolation between Input Channel VIN = 1 VPP at 4.43 MHz on 1 point 541 60 dB CTo Crosstalk Isolation between Output Channel VIN = 1 VPP at 4.43 MHz on 1 point, RLOAD = 150 Ω 501 55 dB ROUT Output Resistance G0V Gain at video outputs (0 dB), recorder VIN = 1 VPP and Gain = 0 dB at output 1 MHz G6V Gain at video outputs (6 dB) Gain matching Between RGB outputs RGBmatch DCOUTZY/CVSS DC OUTREC 8/24 100 5 10 Ω -0.5 0.0 0.5 dB VIN = 1 VPP and Gain = 6 dB at 1 MHz 5.5 6.0 6.5 dB VIN = 0.7 VPP and Gain = 6 dB at 1 MHz -0.3 0.3 dB DC Output Voltage, TV and AUX Y/CVBS outputs Bottom Sync Pulse2 DC Output Voltage, Recorder Y/CVBS Output Bottom Sync Pulse2 Mute 2 Mute2 0.32 0.57 0.40 0.60 0.43 0.67 V 1.2 1.3 1.3 1.4 1.4 1.5 V STV6618 Symbol ELECTRICAL CHARACTERISTICS Parameter DCOUTRGB DC Output Voltage, RGB outputs DC OUTYOUT DC Output Voltage, TV Y Output (G/ YOUT_TV, YPrPb mode) DCOUTPrPb DC Output Voltage, PrPb outputs Test Conditions Black Level2 Mute 2 Bottom Sync Pulse2 Mute2 Black Level2 Mute2 Min. Typ. Max. Unit 0.45 0.50 0.60 0.60 0.70 0.70 V 0.50 0.45 0.60 0.60 0.70 0.70 V 1.4 1.4 1.5 1.5 1.6 1.6 V Differential Phase, Y/CVBS VIN = 1 VPP at 4.43 MHz 0.2 2.5 deg. Differential Gain, Y/CVBS VIN = 1 VPP at 4.43 MHz 0.3 5 % Mute Mute Suppression VIN = 1 VPP at 5 MHz on 1 point LNL Luminance non-linearity VSN Video Signal-to-Noise Ratio3 DPHI DG -55 dB 0.3 3 75 % dB 1. Minimum Crosstalk values estimated during Qualification phase, based on ST Evaluation Board measurement, TQFP44 package soldered on board. 2. Measured at IC output pin. 3. Signal-to-Noise = 20log (VOUTblack-to-white = 0.7 VPP / Vnoise(mVrms) weighted CCIR 567) 2.5 Fast Blanking Section Characteristics Symbol Parameter Test Conditions Min. Typ. Max. Unit 0.4 0.7 0.9 V 2 10 µA 0.5 V 3.8 V INPUT MODE FBLOW/HIGH IIN Input Low/High Level Threshold Input Current OUTPUT MODE FBLOW Output Low Level RLOAD = 150 Ω FBHIGH Output High Level RLOAD = 150 Ω Fast Blanking RGB delay At 50% on digital RGB transients, at 2 V on FB rise transient, at 1 V on FB fall, CLOAD = 10 pF maximum FB Transitions at FB output Rise Time Fall Time CLOAD = 10 pF maximum between 10% and 90% between 90% and 10% FBDEL FBTRANS 3.0 3.4 15 ns 10 10 ns 9/24 ELECTRICAL CHARACTERISTICS 2.6 STV6618 Chroma Section Characteristics TAMB = 25 °C, VCCV = 5 V, VDD = 5 V, ROUT_VREC = 4.7 kΩ, ROUT_VBUF = 150 Ω, unless otherwise specified. Output impedances of sources: RGV = 75 Ω. Symbol Min. Typ. Max. Unit DC Input Level 2.9 3.0 3.1 V RIN Input Resistance 30 50 kΩ CIN Input Capacitance 2 pF VIN Max Input Signal 1.0 VPP Dynamic Output Signal 2.0 VPP 1.6 V VDCIN DYN Parameter Test Conditions DC OUT DC Output Voltage AUX C Output No Chroma input signal1 1.4 1.5 CBW Chroma Bandwidth VIN = 1 VPP at -3 dB 10 15 MHz CTi Crosstalk Isolation between Input Channel VIN = 1 VPP at 4.43 MHz, on one input 542 60 dB CTo Crosstalk Isolation between Output Channel VIN = 1 VPP at 4.43 MHz, on one input, RLOAD = 150 Ω 50 2 55 dB ROUT Output Resistance G6C Gain at Chroma Outputs VIN = 1 Vpp and Gain = 6 dB at 1 MHz 5.5 Mute Mute Suppression VIN = 1 VPP at 4.43 MHz, on one input -55 Chroma to Luma Delay, Source Y/C VIN = VPP at 4.43 MHz CToYdel 5 10 Ω 6.0 6.5 dB dB 20 ns 1. Measured at IC output pin. 2. Minimum Crosstalk values estimated during Qualification phase, based on ST Evaluation Board measurement, TQFP44 package soldered on board. 2.7 Digital Outputs TAMB = 25 °C, VCCV = 5 V, VDD = 5 V. Symbol Parameter C_gate_H Pull-up resistor value to VccB3 C_gate_L Output Low level C_gate_H Output High level DIGOUT1-2-3 Load External pull-up resistor value to VDD DIGOUT1-2-3 Low Output low level, DIGOUT1-2-3 DIGOUT1-2-3 Middle Output middle level, DIGOUT1-2-3 Test Conditions Min. Typ. Max. Unit 16 20 24 kΩ 0.3 0.7 V VDD V IIN = 0 mA IIN = 1 mA RLOAD = 20 kΩ 10 RLOAD = 10 kΩ RLOAD = 10 kΩ kΩ 0.7 2.2 V V DIGOUT1-2-3 High Output high level,DIGOUT1-2-3 RLOAD = 10 kΩ, Opened collector output VDD V DIGOUT4-5-6 Low Output low level, DIGOUT4-5-6 ILOAD = 2 mA 0.7 V DIGOUT4-5-6 High Output high level, DIGOUT4-5-6 Opened Collector Output 13 V 10/24 STV6618 2.8 ELECTRICAL CHARACTERISTICS I²C Bus Characteristics TAMB = 25 °C, VCCV = 5 V, VDD = 5 V Symbol Parameter Test Conditions Min. Typ. Max. Unit SCL VIL Low Level Input Voltage -0.3 1.5 V VIH High Level Input Voltage 2.3 5.5 V ILI Input Leakage Current 10 µs VIL Low Level Input Voltage -0.3 1.5 V VIH High Level Input Voltage 2.3 5.5 V ILI Input Leakage Current 10 µs CI Input Capacitance 10 pF tR Input Rise Time 1.5 V to 3 V 1 µs tF Input Fall Time 3 V to 1.5 V 300 ns Low Level Output Voltage IOL = 3 mA 0.4 V tF Output Fall Time 3 V to 1.5 V 250 ns CL Load Capacitance 400 pF VIN = 0 to 5.5 V -10 0 SDA VOL VIN = 0 to 5.5 V -10 0 TIMING tLOW Clock Low Period 4.7 µs tHIGH Clock High Period 4 µs tSU,DAT Data Setup Time 250 ns tHD,DAT Data Hold Time 0 tSU,STO Setup Time from Clock High to Stop 4 µs 4.7 µs 4 µs 4.7 µs tBUF Start Setup Time following a Stop tHD,STA Start Hold Time tSU,STA Start Setup Time following Clock Low to High Transition Note: 340 ns The device can also operate at 400 kHz and can interface with +3.3 V or + 5 V logic levels. Figure 4: I²C Bus Timing SDA t BUF t LOW tSU,DAT SCL tHD,STA SDA tR t HD,DAT t HIGH tF tSU,STO tSU,STA 11/24 I²C BUS SELECTION 3 STV6618 I²C BUS SELECTION Data transfers follow the usual I²C format; i.e. after the start condition (S), a 7-bit slave address is sent, followed by an eight-bit data direction bit (W). An 8-bit sub-address is sent to select a register, followed by an 8-bit data word to be included in the register. The IC’s I²C bus decoder enables the automatic incrementation mode in write mode. String Format Write only mode (S = Start condition, P = Stop condition, A = Acknowledge) S Slave Address 0 A Sub-address A Data A P A Data A P Read only mode S Slave Address 1 Slave Address Address A7 A6 A5 A4 A3 A2 A1 Value 1 0 0 1 0 1 0 Auto Increment Mode S Slave Address 0 A Sub-address A DATA0 A Sub-Address 3.1 DATA1 A .... DATAn A P Sub-Address +1 Sub-Address + N I²C Bus Addresses Write Address: 1001 0100 = 94(hex) Input Signal Summary (Write Mode) Reg Addr (Hex) Data d7 d6 d5 d4 d3 d2 d1 d0 Y/CVBS and C Output Selection 00 DigOUT6 Not Used TV Y/CVBS Output Selection Recorder Y/CVBS Output Selection 01 DigOUT5 Not Used Auxiliary C Output Selection Auxiliary Y/CVBS Output Selection RGB/YPrPb & Fast Blanking Selection 02 RGB/YPrPb High Impedance State RGB or YPrPb or C mode Selection Auxiliary or Encoder Selection Fast Blanking Selection Digital Outputs 03 12/24 DIGOUT4 DIGOUT3 DIGOUT2 Control DIGOUT1 Control C_GATE Control STV6618 Reg Addr (Hex) I²C BUS SELECTION Data d7 d6 d5 d4 d3 d2 d1 d0 REC Output Standby AUX Input Disable TV Input Disable TUN Input Disable ENC Input Disable Standby 04 Note: Reg. Addr (Hex) TV Output Standby AUX Chroma AUX CVBS Output Output Standby Standby Unused data must be set to “0”. Data Description Bits Comments d7 d6 d5 d4 d3 d2 d1 d0 3 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Mute YIN_ENC CVBSIN_ENC Y/CVBSIN_AUX Y/CVBSIN_TV YCVBSIN_TUN Not allowed Not allowed TV Y/CVBS Output Selection 2 X X X X X X X X X X X X 0 0 1 1 0 1 0 1 X X X X X X X X X X X X Y/CVBS_AUX YIN_ENC CVBSIN_ENC Mute DigOUT6 Control 1 0 1 X X X X X X X X X X X X X X 0 = Low Level 1 = High Level 3 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Y/CVBSin_TV YIN_ENC CVBSIN_ENC YCVBSIN_TUN Mute Not allowed Not allowed Not allowed AUX (SCART2) Chroma Output Selection 2 X X X X X X X X X X X X 0 0 1 1 0 1 0 1 X X X X X X X X X X X X Mute CIN_ENC CIN_TV CIN_TUN DigOUT5 Control 1 0 1 X X X X X X X X X X X X X X 0 = Low Level 1 = High Level Recorder Y/CVBS Output Selection 00 AUX (SCART2) Y/CVBS Output Selection 01 13/24 I²C BUS SELECTION Reg. Addr (Hex) STV6618 Data Description Fast Blanking Output Control RGB/YPrPb Output Selection Bits 2 2 Comments d7 d6 d5 d4 d3 d2 d1 d0 X X X X X X X X X X X X X X X X X X X X X X X X 0 0 1 1 0 1 0 1 FBIN_AUX FB forced to Low Level FB forced to High Level Not allowed X X X X X X X X X X X X 0 0 1 0 1 0 X X X X X X X X X X 1 1 X X RGB/YPrPb_AUX RGB/YPrPb_ENC CIN_ENC (pin 6) at R/Pr/COUT_TV, B/PbOUT & G/YOUT muted RGB/YPrPb mute X X 0 0 0 0 X X RGB mode selection, bottom clamp at RGB inputs, AUX. input selected X X 0 0 0 1 X X RGB mode selection, bottom clamp at RGB inputs, ENC. input selected X X 0 1 0 0 X X CIN_AUX (pin 17)selected, average clamp at R/Pr/CIN_AUX input, GIN_AUX (bottom clamp) selected, BIN_AUX (bottom clamp) selected X X 0 1 0 1 X X CIN_ENC (pin 9)selected, average clamp at R/Pr/CIN_ENC input, GIN_ENC (bottom clamp) selected, BIN_ENC (bottom clamp) selected X X 1 0 0 0 X X YPrPb mode selection, sync pulse clamp at Pr Pb inputs, black clamp at Y input, AUX. input selected X X 1 0 0 1 X X YPrPb mode selection, sync pulse clamp at Pr Pb inputs, black clamp at Y input, ENC. input selected X X 1 1 0 0 X X YPrPb mode selection, delayed sync pulse clamp at Pr Pb inputs, black clamp at Y input, AUX. input select X X 1 1 0 1 X X YPrPb mode selection, delayed sync pulse clamp at Pr Pb inputs, black clamp at Y input, ENC. input select 0 0 1 0 1 X X X X X X X X X X X X X X X X X X X RGB/YPrPb outputs active RGB/YPrPb outputs high imp state Red output active, Green and Blue high imp. state 02 RGB or YPrPb or C Selection RGB/YPrPb Control 14/24 2 2 STV6618 Reg. Addr (Hex) 03 04 3.2 I²C BUS SELECTION Data Description Bits Comments d7 d6 d5 d4 d3 d2 d1 d0 C_Gate Output Control 1 X X X X X X X X X X X X X X 0 1 Low Level High Level DIGOUT1 2 X X X X X X X X X X X X X X X 0 1 1 X 0 1 X X X Low Level Mid Level High Level DIGOUT2 2 X X X X X X X X X 0 1 1 X 0 1 X X X X X X X X X Low Level Mid Level High Level DIGOUT3 2 X X X 0 1 1 X 0 1 X X X X X X X X X X X X X X X Low Level Mid Level High Level DIGOUT4 Control 1 0 1 X X X X X X X X X X X X X X 0 = Low Level 1 = High Level ENC Inputs 1 X X X X X X X X X X X X X X 0 1 Inputs Active Inputs Disabled TUN Inputs 1 X X X X X X X X X X X X 0 1 X X Inputs Active Inputs Disabled TV Inputs 1 X X X X X X X X X X 0 1 X X X X Inputs Active Inputs Disabled AUX Inputs 1 X X X X X X X X 0 1 X X X X X X Inputs Active Inputs Disabled REC Outputs 1 X X X X X X 0 1 X X X X X X X X Y/CVBSOUT_REC Outputs ON Y/CVBSOUT_REC Outputs OFF AUX Outputs 1 X X X X 0 1 X X X X X X X X X X Y/CVBSOUT_AUX Outputs ON Y/CVBSOUT_AUX Outputs OFF COUT_AUX Output 1 X X 0 1 X X X X X X X X X X X X COUT_AUX Outputs ON COUT_AUX Outputs OFF (high imped.) TV Outputs 1 0 1 X X X X X X X X X X X X X X TV Video Outputs ON TV Video Outputs OFF Full Stop 8 1 1 1 1 1 1 1 1 Only I²C bus supplied, and digital outputs Power-on Reset: Bus Register Initial Conditions Power-on Reset is active when supply VDD < 3.5 V. Non-significant bits (X) are pre-set to “0”. Reg. Addr (Hex) d7 d6 d5 d4 d3 d2 d1 d0 00 0 0 0 0 0 0 0 0 Rec. CVBS output muted, TV CVBS output to Aux. CVBS input, Digital output low level 01 0 0 0 0 0 0 0 0 Aux. CVBS output to TV CVBS input, Aux. Chroma output muted, Digital output low level 02 0 0 0 0 0 0 0 0 FB output to Aux. FB input, TV RGB output to Aux. RGB inputs, RGB outputs active 03 0 0 0 0 0 0 0 0 C_gate output low level, DIGOUT outputs low level 04 0 0 0 0 0 0 0 0 All inputs outputs active Data Comments 15/24 INPUT/OUTPUT GROUPS 4 STV6618 INPUT/OUTPUT GROUPS Figure 5: C_Gate Logic Output (Pin 28) V DD 5 V Figure 8: Fast Blanking Inputs (Pin 35) VCCB3 V DD 5 V VDD 5 V 18 kΩ 50 Ω tri Protected Pad Protected Pad Figure 6: Video Outputs (Pins 23, 25, 27, 29, 31 and 33) VCCB1,2,3 VCCB1,2,3 V CCB1,2,3 Figure 9: I²C Bus SCL I/O (Pin 37) VDD5 V VDD_FLOAT 10 kΩ ib Protected Pad Figure 7: YCVBSOUT_REC Recorder Output (Pin 21) V CCB_REC 5 V V CCB_REC 5 V Protected Pad Figure 10: Fast Blanking Output (Pin 34) VDD V CCB3 VCCB3 Protected Pad 16/24 Protected Pad STV6618 INPUT/OUTPUT GROUPS Figure 11: Bottom Clamped Video Inputs (Pins 1, 4, 7, 19 and 41) Figure 14: Average Clamped Video Inputs (Pins 6, 40 and 43) VCC 5 V VCC 5 V VCC 5 V VCC 5 V 2V + VBE 5 kΩ 15 kΩ 5 kΩ 25 kΩ tri tri 25 kΩ Protected Pad Protected Pad Figure 12: DIGOUT 1, 2 and 3 (Pins 42, 44 and 2) VDD 5 V Float_Bus Figure 15: DECV (Pin 5) VCC 5 V VCC 5 V 10 kΩ 40 kΩ Protected Pad Figure 13: DIGOUT 4, 5 and 6 (Pins 14, 16 and 18) V DD 5 V Float_DigOUT Figure 16: I²C Bus SDA I/O (Pin 38) VDD5 V VDD_FLOAT Acknowledge 10 kΩ Protected Pad 17/24 INPUT/OUTPUT GROUPS STV6618 Figure 17: R/Pr/C Inputs (Pins 9 and 17) VCC 5 V V CC 5 V Botclamp 5 kΩ 50 kΩ Protected Pad Figure 18: G/Y Inputs (Pins 10 and 15) VCC 5 V Botclamp VCC 5 V 2V + VBE sepsel 5 kΩ 15 kΩ 20 kΩ tri Protected Pad Figure 19: B/Pb Inputs (Pins 11 and 13) VCC 5 V V CC 5 V Botclamp 2V + VBE 5 kΩ 15 kΩ tri Protected Pad 18/24 STV6618 INPUT/OUTPUT GROUPS Figure 20: Power Supply Connection VCCB3 VCCB2 32 30 VCCB1 VCCB_REC 24 20 26 22 GNDB GNDB_REC Float_VidOUTs 5V VCC 8 3 GND1 VDD 5V 12 36 Float_VDD 5V Float_DigOUTs 12 V 39 GND2 GNDD These symbols represent some huge diode and Zener-like components used for ESD protection of the device. They are not supposed to be paths for any current in normal operation mode. 19/24 APPLICATION DIAGRAMS 5 STV6618 APPLICATION DIAGRAMS Figure 21: YPrPb Application TV INPUTS J1 Y/CVBS J2 C TV OUTPUTS J3 Y/CVBS S-VHS AUX OUTPUTS J5 Y J6 Pb J7 Y/CVBS AUX INPUTS J8 C J9 Y/CVBS J10 Pr J11 Y J12 Pb R39 75 R40 75 . Y . C J4 Pr VCCB R30 75 R31 75 R32 75 R33 75 R34 75 R35 75 R36 75 T2 NPN R37 75 R38 75 R41 75 R42 470 VCCB C25 C26 C27 100n 100n 100n R43 75 C28 24 25 26 27 28 29 30 31 32 33 23 COUT_AUX VCCB1 Y/CVBSOUT_AUX GNDB B/Pb_OUT_TV C_GATE G/YOUT_TV VCCB2 R/Pr/COUT_TV VCCB3 GND2 C30 100n 21 20 12V VCCB R45 10K R46 10K R47 10K 19 18 DOut 6 C33 17 100n 16 DOut 5 C36 15 1µ 14 DOut 4 C38 13 100n 12 G/YIN_ENC 11 1 100n 10 C39 22 B/PbIN_ENC DigOUT2 Tuner Y/CVBS R/Pr/CIN_ENC B/PbIN_AUX 9 44 DigOUT4 CIN_TUN VCC 100n DigOUT1 8 43 G/YIN_AUX YIN8ENC 42 DigOUT5 Y/CVBSIN_TV 7 C37 R/Pr/CIN_AUX CIN_TV CIN8ENC 100n Tuner C 41 6 40 100n STV6618 GNDD DECV C34 C35 DigOUT6 SDA 5 39 VCCB_REC Y/CVBSIN_AUX CVBSIN_ENC 100n 38 GNDB_REC SCL 4 10µ SDA REC Y/CVBS C29 100n VDD GND1 37 3 C32 36 C31 SCL R44 75 Y/CVBSOUT_REC FBIN_AUX DigOUT3 VDD FBOUT_TV Y/CVBSIN_TUN 35 2 34 REC C Y/CVBSOUT_TV U3 10µ VCC VCC C40 C47 47n C41 C42 100n 10µ R48 R49 R50 C43 C44 C45 C46 1µ C48 100n 100n100n 100n 100n 10K 10K 10K DOut 1 DOut 2 DOut 3 R51 R52 R53 R54 R55 R56 R30 to R35: expected loads on Decoder outputs 20/24 ENC Pb ENC Y ENC Pr ENC Y ENC C ENC CVBS All grounds must be linked un der the IC STV6618 APPLICATION DIAGRAMS Figure 22: 2 SCART / RGB Signal Application R1 75 R2 75 R3 75 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 AUX1 SCART 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 TV1 SCART R4 75 R5 75 R9 75 R6 75 R7 75 R8 75 Q1 JFET N R10 75 R11 75 R12 75 Q2 JFET N VCCB C1 C2 C3 100n 100n 100n 24 25 26 27 23 COUT_AUX VCCB1 Y/CVBSOUT_AUX GNDB 28 C_GATE B/Pb_OUT_TV 30 31 29 G/YOUT_TV VCCB2 32 VCCB3 R/Pr/COUT_TV Y/CVBSOUT_TV C6 100n 21 20 12V VCCB R18 10K R19 10K R20 10K 19 18 DOut 6 C9 17 100n 16 DOut 5 C12 15 100n 14 DOut 4 C14 13 100n 12 11 1 100n 10 C15 22 B/PbIN_ENC GND2 G/YIN_ENC DigOUT2 Tuner Y/CVBS R/Pr/CIN_ENC B/PbIN_AUX 9 44 DigOUT4 CIN_TUN VCC 100n DigOUT1 8 43 G/YIN_AUX Y/CVBSIN_TV YIN8ENC 42 DigOUT5 CIN_TV CIN8ENC C13 R/Pr/CIN_AUX 7 100n Tuner C 41 STV6618 GNDD 6 40 100n DigOUT6 SDA DECV C10 C11 VCCB_REC Y/CVBSIN_AUX 5 39 GNDB_REC SCL CVBSIN_ENC 100n 38 10µ SDA R17 4K7 100n VDD 4 37 DigOUT3 36 GND1 C8 C7 SCL REC Y/CVBS C5 Y/CVBSOUT_REC FBIN_AUX 3 VDD FBOUT_TV 2 35 Y/CVBSIN_TUN 34 33 C4 U1 10µ VCC VCC C16 47n C17 C18 100n 10µ R21 R22 R23 C19 C20 C21 C22 C23 C24 100n 100n100n 100n100n100n 10K 10K 10K DOut 1 DOut 2 DOut 3 R24 R25 R26 R27 R28 R29 ENC B ENC G ENC R ENC Y ENC C All grounds must be linked un der the IC ENC CVBS R13 to R18: expected loads on Decoder outputs 21/24 PACKAGE MECHANICAL DATA 6 STV6618 PACKAGE MECHANICAL DATA Figure 23: 44-Pin Thin Quad Flat Package 0.10m m .004 seating plane A b 1.60 A1 0.05 A2 1.35 1.40 b 0.30 0.37 c 0.09 0.006 0.45 0.012 0.015 0.018 0.20 0.004 0.008 10.00 0.394 D3 8.00 0.315 0.472 0.472 E 12.00 E1 10.00 0.394 E3 8.00 0.315 0.80 0.031 K 0° 3.5° 7° L 0.45 0.60 0.75 0.018 0.024 0.030 1.00 0.039 Number of Pins N 22/24 0.053 0.055 0.057 D1 c K 1.45 12.00 L1 L 0.002 D e L1 0.063 0.15 44 STV6618 7 REVISION HISTORY REVISION HISTORY The following table summarizes the modifications applied to this document. Revision 1.0 Description Date First Issue 24 April 2001 New pinout proposal, to improve connection to TV SCART. Slight correction of electrical parameters (changed value in Bold). Correction of DigOUT1-2-3 I²C control specification (changed value in bold) 27 April 2001 New pinout proposal, To improve connection to SCARTs. Application layout hypothesis: 1 layer PCB, IC on lower side (copper side), SCART on upper side 7 May 2001 Application diagrams added. VDCin chroma section: 3.0V instead of 2.3V previously. VDCin , video section, PrPb: 3.0V instead of 2.3V previously 11 May 2001 Add Fast Blanking Section Electrical Characteristics. Update Application Schematic Diagrams 7 June 2001 1.1 Addition of Section 4: INPUT/OUTPUT GROUPS on page 16. 21 June 2001 1.2 Document reformatted. Replaced Figure 22: 2 SCART / RGB Signal Application on page 21. 6 July 2001 1.3 CIN = 1 VPP changed to "VIN = 1 VPP in CBW Parameter in Section 2.6. Symbols for a PNP, NPN and current source as well as their connections added to Figure 17. 2 Oct 2001 1.4 Update of Crosstalk and DC Output voltage data in Section 2.4 and Section 2.6. Modification of Register 2 data in Section 3.1. Replaced Figure 21 and Figure 22. 10 Oct 2001 1.5 Update of Crosstalk data and Output Voltage values in Section 2.4 and Section 2.6. Updated Figure 3 and Figure 22. 26 Oct 2001 1.6 Chroma Output Gain (G6C) parameters updated in Section 2.6. 14 Jan 2002 1.7 Addition of minimum/maximum values for certain parameters in Section 2: ELECTRICAL CHARACTERISTICS. Document upgraded to Datasheet status. 24 May 2002 1.8 Modification of Bandwidth parameter (17 MHz) and Figure 3. 24 Sept. 2002 23/24 REVISION HISTORY STV6618 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. 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