STV8162 - STV8162D ® +5 V, +5 V and +8 V Triple-Voltage Regulator with Disable and Reset Functions DATASHEET Key Features ■ Input Voltage range between 7 V and 18 V ■ Output Currents up to 600 mA ■ Fixed Precision Output 1 voltage of 5 V ± 2% ■ Fixed Precision Output 2 voltage of 5 V ± 2% ■ Fixed Precision Output 3 voltage of 8 V ± 2% ■ Output 1 with Reset facility ■ Outputs 2 and 3 can be disabled by digital input Clipwatt 11 Order Code: STV8162 ■ Short Circuit Protection on each output ■ Thermal Protection ■ Low Dropout Voltages DESCRIPTION The STV8162 and STV8162D are monolithic triple positive voltage regulators designed to provide three fixed precision output voltages of 5 V, 5 V and 8 V for currents up to 0.6 A. An internal reset circuit generates a reset pulse when the voltage of Output 1 drops below the regulated voltage value. Power DIP 18 (9 + 9) Order Code: STV8162D Outputs 2 and 3 can be disabled by a digital input. Short-circuit and thermal protections are included in all versions. GROUND 10 9 DISABLE GROUND 11 8 INPUT3 GROUND 12 7 OUTPUT3 GROUND 13 6 INPUT2 GROUND 14 5 OUTPUT2 GROUND 15 4 INPUT1 GROUND 16 3 OUTPUT1 GROUND 17 2 DELAY CAPACITOR GROUND 18 1 RESET February 2004 Top View 11 10 9 8 7 6 5 4 3 2 1 NC DISABLE INPUT3 OUTPUT3 INPUT2 GROUND OUTPUT2 INPUT1 OUTPUT1 DELAY CAPACITOR RESET 1/12 GENERAL INFORMATION 1 STV8162 - STV8162D GENERAL INFORMATION Figure 1: STV8162 Block Diagram DELAY CAPACITOR 2 1 RESET 3 OUTPUT1 5 OUTPUT2 8 OUTPUT3 Reference INPUT1 4 Regulator 1 Protections INPUT2 7 Regulator 2 INPUT3 9 Regulator 3 DISABLE 10 11 Not Connected 6 GROUND Figure 2: STV8162D Block Diagram DELAY CAPACITOR 2 1 RESET 3 OUTPUT1 5 OUTPUT2 7 OUTPUT3 Reference INPUT1 4 Regulator 1 Protections INPUT2 6 INPUT3 8 Regulator 2 Regulator 3 DISABLE 9 GROUND Pins 10 to 18 2/12 STV8162 - STV8162D Electrical Characteristics 2 Electrical Characteristics 2.1 Absolute Maximum Ratings Symbol Parameter Value Unit VIN DC Input Voltage at pins INPUT1, INPUT2 and INPUT3 20 V VDIS Disable Input Voltage at pin DISABLE 20 V VRST Output Voltage at pin RESET 20 V IOUTPUT Pt Output Currents Internally Limited Power Dissipation Internally Limited TSTG Storage Temperature -65 to +150 °C TJ Junction Temperature 0 to +150 °C Value Unit 2.2 Thermal Data Symbol Parameter RthJC Junction-to-Case Thermal Resistance STV8162 STV8162D 3 15 °C/W RthJA Junction-to-Ambient Thermal Resistance 1 STV8162 STV8162D ³10 56 °C/W 140 °C 0 to +70 °C Maximum Recommended Junction Temperature TJ TOPER Operating Free Air Temperature Range 1. Mounted on board. For more information, refer to Section 5. 2.3 Electrical Characteristics TAMB = 25° C, VIN1 = 7 V, VIN2 = 7 V and VIN3 = 10 V, unless otherwise specified. Symbol Parameter Test Conditions Min. Typ. Max. Unit VOUT1 Output Voltage IOUT1 = 10 mA 4.90 5.00 5.10 V VOUT2 Output Voltage IOUT2 = 10 mA 4.90 5.00 5.10 V VOUT3 Output Voltage IOUT3 = 10 mA 7.84 8.00 8.16 V VOUT1 Output Voltage 7 V < VIN1 < 12 V 5 mA < IOUT1 < 600 mA 4.80 5.20 V VOUT2 Output Voltage 7 V < VIN2 < 12 V 5 mA < IOUT2 < 600 mA 4.80 5.20 V VOUT3 Output Voltage 10 V < VIN3 < 15 V 5 mA < IOUT3 < 600 mA 7.68 8.32 V 3/12 Electrical Characteristics Symbol STV8162 - STV8162D Parameter Test Conditions Min. Typ. Max. Unit VIO1 Dropout Voltage IOUT1 = 0.6 A 1 1.4 V VIO2 Dropout Voltage IOUT2 = 0.6 A 1 1.4 V VIO3 Dropout Voltage IOUT3 = 0.6 A 1 1.4 V VOUT1LI Line Regulation 7 V < VIN1 < 12 V, IOUT1 = 200 mA 50 mV VOUT2LI Line Regulation 7 V < VIN2 < 12 V, IOUT2 = 200 mA 50 mV VOUT3LI Line Regulation 10 V < VIN3 < 15 V, IOUT3 = 200 mA 80 mV VOUT1LO Load Regulation 5 mA < IOUT1 < 600 mA 100 mV VOUT2LO Load Regulation 5 mA < IOUT2 < 600 mA 100 mV VOUT3LO Load Regulation 5 mA < IOUT3 < 600 mA 160 mV Quiescent Current IOUT1 = 10 mA Outputs 2 and 3 disabled 2.2 3.0 mA Reset Threshold Voltage K = VOUT1 K-0.4 K-0.25 K-0.10 V Reset Threshold Hysteresis See circuit description. 30 75 120 mV tRD Reset Pulse Delay Ce = 100 nF See circuit description. VRL Saturation Voltage in Reset Condition IRESET = 5 mA 0.4 V IRH Leakage Current in Normal Condition, at RESET pin VRESET = 10 V 10 mA IQ VO1RST VRTH 25 ms TJ = 0 to 125°C KOUT1 KOUT2 KOUT3 Output Voltage Thermal Drift DVOUT × 10 K OUT = -------------------------------DT × V OUT IOUT1SC Short Circuit Output Current VIN1 = 7 V 0.8 1.3 1.8 A IOUT2SC Short Circuit Output Current VIN1 = 7 V 0.8 1.3 1.8 A IOUT3SC Short Circuit Output Current VIN3 = 10 V 0.8 1.3 1.8 A 6 VDISH Voltage High Level at DISABLE pin (Outputs 2 and 3 active) VDISL Voltage Low Level at DISABLE pin (Outputs 2 and 3 disabled) 100 ppm/°C 2 V 0.8 V 2 mA IDIS Bias Current at DISABLE pin TJSD Junction Temperature for Thermal Shutdown 150 °C TSDH Thermal Shutdown Temperature Hysteresis 15 °C 4/12 0 V < VDISABLE < 7 V -100 STV8162 - STV8162D 3 Circuit Description Circuit Description The STV8162 and STV8162D are triple-voltage regulators with Reset and Disable functions. The three regulation parts are supplied from a single voltage reference circuit trimmed by zener zapping during EWS testing. Since the supply voltage of this voltage reference is connected to pin INPUT1 (VIN1), the second and third regulators will not work if pin INPUT1 is not supplied. The output stages are designed using a Darlington configuration with a typical dropout voltage of 1.0 V. IMPORTANT: In all applications, all three inputs must be polarized. If Outputs 2 or 3 are not used, the corresponding inputs must be connected to Input 1. The Disable circuit will switch off pins OUTPUT2 and OUTPUT3 if a voltage less than 0.8 V is applied to pin DISABLE. The Reset circuit checks the voltage at pin OUTPUT1. If this voltage drops below VOUT1-0.25 V (4.75 V Typ.), the "a" comparator (Figure 3) rapidly discharges the external capacitor (Ce) and the reset output immediately switches to low. When the voltage at pin OUTPUT1 exceeds VOUT1-0.175 V (4.825 V Typ.), the VCe voltage increases linearly to the reference voltage (VREF = 2.5 V) corresponding to a Reset Pulse Delay (tRD) as shown in Figure 4. C e ´ 2.5V tRD = -------------------------10mA Afterwards, the reset output returns to high. To avoid glitches in the reset output, the second comparator "b" has a large hysteresis (1.9 V). 5/12 Application Diagrams 4 STV8162 - STV8162D Application Diagrams Figure 3: Reset Diagram 10 µA VREF OUTPUT1 + a - + b RESET 3 REG Ce VREF = 2.5 V VREF 0.6V Figure 4: Internal Reset Voltage VOUT1 K VO1RST VRTH RESET K = Actual Value of VOUT1 6/12 Power On tRD tRD Power Off STV8162 - STV8162D Application Diagrams Figure 5: STV8162 Typical Application C1 to C6 = 10 µF 0.1 µF Ce 1 RESET 2 DELAY CAPACITOR VIN1 4 INPUT1 OUTPUT1 3 VOUT1 VIN2 7 INPUT2 OUTPUT2 5 VOUT2 VIN3 9 INPUT3 OUTPUT3 8 VOUT3 C1 C2 C3 GROUND DISABLE 6 10 NC 11 C4 C5 C6 Figure 6: STV8162D Typical Application C1 to C6 = 10 µF Ce 1 RESET 0.1 µF 2 DELAY CAPACITOR VIN1 4 INPUT1 OUTPUT1 3 VOUT1 VIN2 6 INPUT2 OUTPUT2 5 VOUT2 VIN3 8 INPUT3 OUTPUT3 7 VOUT3 C1 C2 C3 GROUND DISABLE 9 Pins 10 to 18 C4 C5 C6 7/12 Power Dissipation and Layout Indications 5 STV8162 - STV8162D Power Dissipation and Layout Indications The power is mainly dissipated by the three device buffers. It can be calculated by the equation: P = (VIN1-VOUT1) x IOUT1 + (VIN2-VOUT2) x IOUT2 + (VIN3-VOUT3) x IOUT3 The following table lists the different RthJA values of these packages with or without a heat sink and the corresponding maximum power dissipation assuming: ● Maximum Ambient Temperature = 70° C ● Maximum Junction Temperature = 140° C Device Heat Sink RthJA in °C/W PMAX in W No 50 1.4 Yes 15 4.6 No 56 to 40 1.25 to 1.75 Yes 32 2.2 STV8162 STV8162D Figure 7: Thermal Resistance (Junction-to-Ambient) of DIP18 Package without Heat Sink To optimize the thermal conductivity of the copper layer and the exchanges with the air, the solder must cover the maximum amount of this area. RthJA °C/W 60 55 Test Board with “On Board” square heat sink area. 50 45 40 6 0 2 4 8 10 12 Copper area (cm²) (35 µm plus solder) Board is face-down Figure 8: Metal plate mounted near the STV8162D for heat sinking Top View Bottom View 8/12 STV8162 - STV8162D 6 Package Mechanical Data Package Mechanical Data Figure 9: 11-pin Plastic Clipwatt Package H3 C A D L B L1 L2 H1 E G F G1 M1 M mm Inches Dim. Min. Typ. Max. Min. Typ. Max. A 3.20 0.126 B 1.05 0.041 C 0.15 D 0.006 1.50 E 0.49 F 0.80 G 1.57 0.059 0.55 1.70 0.019 0.91 0.031 1.83 0.062 0.002 0.036 0.067 H1 12.00 0.480 H2 18.60 0.732 H3 19.85 L L2 0.781 17.90 L1 0.700 14.45 10.70 0.072 11.00 0.569 11.20 0.421 0.433 L3 5.50 0.217 M 2.54 0.100 M1 2.54 0.441 0.100 Number of Pins N 11 9/12 Package Mechanical Data STV8162 - STV8162D Figure 10: 18-pin Plastic Dual In-line Power Package E A2 A A1 L b2 b e c eB D1 b3 D 18 10 E1 9 1 mm Inches Dim. Min. Typ. A Min. Typ. 5.33 Max. 0.210 A1 0.38 A2 2.92 3.30 4.95 0.115 0.130 0.195 b 0.36 0.46 0.56 0.014 0.018 0.022 b2 1.14 1.52 1.78 0.045 0.060 0.070 b3 0.76 0.99 1.14 0.030 0.039 0.045 c 0.20 0.25 0.36 0.008 0.010 0.014 D 22.35 22.86 23.37 0.880 0.900 0.920 D1 0.13 e 0.015 0.005 2.54 eB 10/12 Max. 0.100 10.92 0.430 E 7.62 7.87 8.26 0.300 0.310 0.325 E1 6.10 6.35 7.11 0.240 0.250 0.280 L 2.92 3.30 3.81 0.115 0.130 0.150 STV8162 - STV8162D 7 Revision History Revision History Table 1: Summary of Modifications Version Date 0.2 January 2000 0.3 November 2002 Main Changes First Edition Addition of PDIP18 package. 11/12 Revision History STV8162 - STV8162D NOTES: Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners © 2004 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States www.st.com 12/12