STV9212 ® Video Processor for CRT Monitors with PictureBooST Main Features ■ General ● I²C-Bus Controlled ● Supports AC- and DC-coupled applications ● 5V to 8V Power Supply ● Matches to virtually any video amplifier ■ PictureBooST ● PictureBooST insertion input ● Full-screen PictureBooST via I²C-bus ● Context-sensitive Picture Enhancement ■ Video Clamping ● Input and Output Video Clamp ● Sync Pulse Polarity Auto-rectification ● Clamp Pulse Generation timed either by sync or video blanking pulse ■ Video Processing ● Contrast Adjustment with excellent channel matching ● Gain stages for control of white ● Two DC-mode cut-off ranges ● Output DC offset control ● Automatic Beam Limiter (ABL) ● Video Insertion Pulse (VIP), 2 levels ● Amplifier Control (Blanking and Stand-by) ■ OSD Insertion with Contrast Control ■ Control Output ● Amplifier Standby and Blanking Control ● 3 DAC for control of DC Restore Amplifier or Brightness in DC-coupled system DIP24S:(Plastic Package) ORDER CODE: STV9212 General Description The STV9212 is an I²C-bus controlled color video processor designed for standard CRT monitor applications. It can drive systems where cathodes are either AC- or DC-coupled to the amplifier outputs. The three video channels provide contrast and white balance separate gain adjustments as well as one-per-channel DC cut-off control and common DC offset control functions. On top of these usual controls, it features context-sensitive picture enhancement circuitry to support the PictureBooST function that enhances the appearance of still pictures and moving video. In AC coupling applications, the device can pilot three cathode DC restore channels dedicated to set CRT cut-off bias voltages and to control brightness through cathodes. The RGB video outputs have a class A architecture and directly drive the amplifier channels without unnecessarily consuming current. Bandwidth limitation I²C-bus adjustments can contribute to keeping the application EMI under control. OSD (On-Screen Display) graphics are inserted by means of a Fast Blanking signal. Independent OSD contrast control facilitates adaptation to various OSD generators and provides system flexibility. The STV9212 is perfectly compatible with other ST components for CRT video boards, such as video amplifiers and OSD generators. October 2003 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 1/34 STV9212 Table of Contents Chapter 1 STV9212 Pin Allocation and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.1 Pinout .................................................................................................................................. 4 1.2 Pin Descriptions .................................................................................................................. 4 Chapter 2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 2.1 Video RGB Input Clamp ....................................................................................................... 6 2.2 Video Blanking ..................................................................................................................... 8 2.3 Contrast Control Stage and Automatic Beam Limiter .......................................................... 9 2.4 PictureBooST ..................................................................................................................... 10 2.5 OSD Insertion ..................................................................................................................... 11 2.6 Drive Stage ........................................................................................................................ 11 2.7 Video Insertion Pulse ......................................................................................................... 12 2.8 Output Stage ...................................................................................................................... 12 2.9 Output Infra-black Level, Cut-off and Brightness ............................................................... 15 2.10 Signal Waveforms .............................................................................................................. 18 2.11 Miscellaneous .................................................................................................................... 18 Chapter 3 I²C-Bus Interface Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 3.1 Chapter 4 I²C-bus Register Descriptions ............................................................................................ 21 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 4.1 Absolute Maximum Ratings ............................................................................................... 24 4.2 Thermal Data ..................................................................................................................... 24 4.3 Static Electrical Characteristics .......................................................................................... 24 4.4 Dynamic Electrical Characteristics ..................................................................................... 25 4.5 I²C-Bus Electrical Characteristics ....................................................................................... 27 4.6 I²C-Bus Interface Timing Requirements ........................................................................... 27 Chapter 5 Soldering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Chapter 6 Package Mechanical Data Chapter 7 Input/Output Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 2/34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 STV9212 Chapter 8 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 3/34 STV9212 Pin Allocation and Description STV9212 1 STV9212 Pin Allocation and Description 1.1 Pinout Figure 1: STV9212 Pinout 1.2 IN1 1 24 BLK HS 2 23 AMPCTL IN2 3 22 OUT1 ABL 4 21 VCCP IN3 5 20 OUT2 GNDA 6 19 GNDP VCCA 7 18 OUT3 PB 8 17 CO1 OSD1 9 16 CO2 OSD2 10 15 CO3 OSD3 11 14 SDA FBLK 12 13 SCL Pin Descriptions Table 1: STV9212 Pin Descriptions Pin Name 1 IN1 2 Pin Name Video Input, Channel 1 13 SCL I²C-bus Clock Input HS Video Clamp Sync Input 14 SDA I²C-bus Data Input/Output 3 IN2 Video Input, Channel 2 15 CO3 Cut-off / Brightness DAC 3 Output 4 ABL Automatic Beam Limiter Input 16 CO2 Cut-off DAC 2 Output 5 IN3 Video Input, Channel 3 17 CO1 Cut-off DAC 1 Output 6 GNDA Analog Ground 18 OUT3 Video Output, Channel 3 7 VCCA Analog Supply 19 GNDP Output Stage Ground 8 PB Picture Boost Input 20 OUT2 Video Output, Channel 2 9 OSD1 OSD Input, Channel 1 21 VCCP Output Stage Supply 10 OSD2 OSD Input, Channel 2 22 OUT1 Video Output, Channel 1 11 OSD3 OSD Input, Channel 3 23 AMPCTL 12 FBLK OSD Insertion Control Input 24 BLK 4/34 Function Function Output for Amplifier Control Blanking and Video Clamp Sync Input ABL 4 I²C-bus control path STV9212 SCL SDA Drive 10 OSD2 9 OSD1 OSD Contrast OSD + 7 VCCA PreAmplifier Stand-by video/control signal path 13 14 I²C-bus Decoder Channel 3 Channel 1 FBLK + IN3 5 I²C Contrast PictureBooST 8 PB Channel 2 ICP Vref Clamp ICP OCP BLKI 12 FBLK IN2 3 IN1 1 24 ICP, OCP BLKI BLK 2 11 I²C VIP level OSD3 BLKI + I²C 3V (DC) Output Stage OCP I²C Standby & Blanking BLKI VCCP GNDA 6 Infra-black level cut-off Brightness 21 VCCP GNDP DCIN1 CO1 23 AMPCTL 15 CO3 18 OUT3 16 CO2 20 OUT2 19 17 22 OUT1 GND STDB/ BLK GDC GV Amplifier DC or AC DCOUT1 VOUT1 EHT 2 HS STV9212 Functional Description Functional Description The functional blocks are described in the order they act on the signal. Figure 2: STV9212 Block Diagram 5/34 Functional Description 2.1 STV9212 Video RGB Input Clamp The three RGB inputs have to be supplied with a video signal through coupling capacitors playing the role of analog memories for internal video clamps. The input clamping level is approximately 0V. The clamp is gated by the Input Clamp Pulse (ICP) that is internally generated from a signal on either the HS or BLK pin. The selection is done via register 8 of the I²C-bus. For more information, refer to Figure 3: ICP, OCP and BLKI Generation and Table 2: ICP Timing. Provided with an automatic polarity rectification function, the HS input accepts horizontal synchronization signals of either polarity. The device can select either the leading or trailing edge of this signal to trigger the ICP generator. The BLK input is followed by an inverter stage that can be enabled or by-passed via the I²C-bus. This allows the use of a signal of either polarity, the control software taking care of the inverter position according to the signal applied. The BLKI signal found behind this inverter stage also drives the video blanking circuitry which requires a positive BLKI polarity for correct operation. Once bit BLKPOL has correctly been uploaded to ensure a positive BLKI polarity, the ICP triggering edge can be selected via control bit BCEDGE. A horizontal flyback pulse is generally expected to be applied on the BLK input. As the edges of horizontal flyback pulse can fall into the active video content (outside the video signal line blanking portion), the application must ensure that such an edge is never selected for triggering the ICP. The width of the internally generated ICP is controlled via the I²C-bus. The HS input can be used to pass a clamping pulse, if available in the application, directly to clamping stages, without any additional processing. In this case, the appropriate polarity (positive) is required. See Table 2: ICP Timing. The ICP timings triggered by the trailing edge of the BLK signal are not presented. The Output Clamp Pulse (OCP) is described in Section 2.8: Output Stage. Figure 3: ICP, OCP and BLKI Generation BCEDGE ICP width BCWDTH (Sad08/b0) (Sad08/b1) (Sad08/b2,b3) 2 Automatic Polarity -1 1 -1 BLK 1 BLKI 0 0 Pulse Generation on Pulse Generation on OCP (Internal) 0 BLKPOL OCPSC (Sad09/b0) (Sad08/b7) Video blanking ICP (Internal) 1 1 1 24 (Sad08/b4) 0 0 HS ICP trig/pulse mode BCSC1 BCSC0 BLKI (Internal) I²C-bus field Note: The I²C-bus switches are displayed in their default positions 6/34 STV9212 Functional Description Table 2: ICP Timing Trigger Source Trigger Event BCSC1 BCSC0 Timing Diagram BCEDGE BLKPOL negative or positive HS Trailing edge 0 0 0 Don’t care ICP 0.33µs...1.33µs HS pin negative or positive HS Leading edge 0 0 1 Don’t care ICP 0.33µs...1.33µs HS Pulse 1 Don’t care Don’t care (must be positive!) Don’t care ICP Rising edge 0 0 0 1 1 0 1 1 0 BLK 1 ICP 0.33µs...1.33µs BLK Falling edge 0 BLK 1 ICP 0.33µs...1.33µs Figure 4: Video Input Clamp VRef = Internal reference voltage (fixed) Input video VRef 0V IN1 0V DC signal from graphics card (can vary) 1 High Impedance stage To further processing ICP 0V clamped to GND Note: Identical for IN2 and IN3 inputs 7/34 Functional Description 2.2 STV9212 Video Blanking The three video channels are simultaneously blanked with the high level of either BLKI or FBLK signals. BLKI is an internal signal drawn from the signal applied on the BLK pin (H-flyback) as shown in Figure 3. The blanking consists in forcing a “black” level to the internal clamped video signal. BLK Input The BLK input receives an H-flyback pulse that drives: ● the video blanking circuitry during scan line retrace, ● the output clamping stage. A clipping circuit at the input allows the direct use of a high-voltage H-flyback pulse applied through a serial resistor as shown in Figure 5. A logic-level signal is also accepted but the serial resistor remains mandatory. In all cases, the value of this resistor must be such that the sinking and sourcing currents are limited to 1mA and 100µA, respectively. Figure 5: BLK Input Pin Typical H-Flyback signal 40 to 100V Rlim (*) GND 0 to -10V BLK 24 ~3V Signal at BLK pin (Pin 24) GND (*) Rlim is necessary to limit currents flowing through BLK pin (-100uA, +1mA max.) Permanent Blanking The entire TV screen can be blanked for an unlimited amount of time using the software blanking feature. Both bits SWBLK and TST1 must be set to 1. The three video outputs are forced to their infra-black levels as shown in Figure 6. Infra-black levels are defined in Section 2.9. Figure 6: Software Blanking Normal operation SWBLK=0, TST1=0 Software blanking in operation SWBLK=1, TST1=1 8/34 Video output channels 1,2,3 Black level Infra-black level STV9212 Functional Description The screen can also be blanked by permanently keeping the On-Screen Display FBLK input signal at high level. In this case, only the video contents of the three video channels are replaced by “black level” OSD content insertion (signals on pins OSD1 through OSD3 permanently at low level). Refer to Section 2.5: OSD Insertion on page 11. 2.3 Contrast Control Stage and Automatic Beam Limiter The contrast stages are simultaneously controlled on all three RGB channels with high attenuation matching precision. Refer to electrical specifications for values. See Figure 7: Contrast Control and Table 4: I²C-Bus Register Map. Figure 7: Contrast Control Before contrast stage Video Black Level VRef CRST=max After contrast stage CRST=mid Video Black Level CRST=min VRef Note: CRST I²C-bus field acts equally on all 3 video channels The Automatic Beam Limiter (ABL) is an attenuator controlled through the ABL input, independent of contrast stage attenuation. The operating range is about 2 V (from 3 V to 1 V). A typical characteristic is shown in Figure 8. Refer to Section 4: Electrical Specifications for specific values. When not used, the ABL pin is to be connected to VCCA. Figure 8: ABL Characteristics Attenuation (dB) 0 -2 -4 -6 -8 -10 -12 -14 -16 0 1 2 3 4 5 VABL (V) 9/34 Functional Description 2.4 STV9212 PictureBooST The PictureBooST function provides a picture enhancement effect for images with photographic or moving video contents. The function is activated whenever the level on pin PB is high (TTL) or the bit PBINS is at 1, if the general PictureBooST enable bit PBGEN is at 1. By means of PB input signal toggling, the function can take effect in a part of the screen, e.g. a window, or on the whole screen. The picture enhancement is achieved through combination of three actions, as shown in Figure 9: ● a content-sensitive peaking with slow restore (vivacity), ● a contrast addition, ● a brightness addition. The vivacity amplitude depends on the slope height and steepness and on the status of bits PBVIVAM[1:0]. The return to stabilized state is exponential with a time constant adjustable via bits PBVIVTC[2:0]. Any undershoot below the video black level is clipped to a level close to black. The PictureBooST brightness is a DC offset superimposed on the video signal in the boosted zone. Its value is selected by bits PBBRIG[1:0]. The vivacity and PictureBooST brightness are both enabled by bit PBVIVEN. The PictureBooST contrast component evenly increases the video amplitude in the boosted zone. Its value is controlled by bits PBCRST[1:0]. Refer to Section 4: Electrical Specifications for values. Figure 9: PictureBooST Action H-sync Video before PictureBooST stage A PB input Vviv τviv PB contrast Video after PictureBooST stage A PB brightness 10/34 clipping STV9212 2.5 Functional Description OSD Insertion The On-Screen Display (OSD) is inserted with a high level on the FBLK input (TTL). The device acts as follows: ● The three RGB video input signals (IN1, IN2, IN3) are internally blanked, i.e. put at the black level. ● Binary levels (TTL) on inputs OSD1, OSD2 and OSD3, after processing in the OSD contrast stage, are added to the corresponding blanked video channels. In this way, the OSD contents replace the video contents where the FBLK input is high. See Figure 2 and Figure 10. The OSD is inserted after the PictureBooST block and before the Drive block. As a consequence, OSD insertion overlaps all video contents, including the PictureBooST-ed zones. Color temperature adjustments by means of the I²C-bus Drive registers act in the OSD insets. The OSD contrast stage allows the adjustment of the level of OSD insets simultaneously on the three OSD channels and independently of the video contrast adjustment. Refer to Section 4: Electrical Specifications for values. Figure 10: OSD Insertion OSD Signals Video before OSD insertion Video Black Level VRef FBLK OSD1(2,3) max mid Video after OSD insertion VOSD Video Black Level min. VRef OSDCRST Note: The OSDCRST I²C-bus field acts equally on all 3 OSD channels. 2.6 Drive Stage The Drive stage is a set of three attenuators separately controlled via three I²C-bus registers, DRIVE1, DRIVE2 and DRIVE3. It affects all signals, ordinary video, PictureBooST processed video and OSD insets. It is designed to compensate for differences in gain of the three CRT cathodes. See Figure 11 and for values, refer to Section 4: Electrical Specifications. 11/34 Functional Description STV9212 Figure 11: Drive Control Before Drive Stage Video Black Level DRIVEx=max After Drive Stage VRef One I²C-bus register DRIVEx (x=1, 2 or 3) per video channel DRIVEx=mid DRIVEx=min 2.7 Video Black Level VRef Video Insertion Pulse The Video Insertion Pulse (VIP) creates an indent on the three video signals, timed with the positive part of the BLKI signal. (See Section 2.2: Video Blanking on page 8). As its level is below the video black level, it introduces a video “infra-black” level. The video infra-black level position versus ground is then controlled in subsequent stages. In the absence of the blanking pulse on pin BLK, the VIP is not inserted and the subsequent stages control the position of video black level. Figure 12 shows the signal before and after insertion of the VIP. Two different VIP values are programmable by bit VIP. Refer to Section 4: Electrical Specifications for values. Figure 12: VIP Insertion Video before VIP insertion Video Black Level VRef BLKI signal Video after VIP insertion Video Black Level VVIP Video Infra-black Level VRef+VVIP VRef Note: Identical for video channels 1, 2 and 3. 2.8 Output Stage The output stage consists of an output clamp and a buffer. If a reduced output video amplitude and/ or a reduced infra-black level range is sufficient in the application, the VCCP can be lowered to 5V. 12/34 STV9212 Functional Description Even at 8V of VCCP, care must be taken at device application level to ensure operation without signal top limitation. 2.8.1 Output Clamp The DC position of video infra-black and video black levels at the video outputs must be fixed regardless of video or OSD inset contents, especially in applications where the device’s output infra-black level determines directly the infra-black level on the CRT cathodes (DC-coupled applications). This fixing is achieved by means of a fully-integrated output clamp that brings the output video infra-black level (video black level, in absence of the BLK pulse) to the level of a variable reference (Vib) as shown in Figure 13. The Vib is described in detail in Section 2.9 on page 15. The clamp circuit is driven by the Output Clamp Pulse (OCP). For correct operation, this pulse must entirely fall into the VIP pulse if this is present (clamp of infra-black level) or onto the video black part (clamp of black level). In the former case, the OCP generator is to be triggered with the leading edge of the BLK pulse, in the latter case it must copy the ICP pulse. Refer to Figure 3 for the OCP generation block diagram. Table 3 shows possible OCP timings. Although possible, the OCP timings, triggered by the BLK trailing edge, are not shown as they have no practical use. 2.8.2 Bandwidth Control Controlled via bits BW[3:0], the output stage can limit the rise and fall time of the output signal. The optimum choice for this adjustment is highly application dependent. Refer to Section 4: Electrical Specifications for values and to Section 6: Application Hints for practical advice. 2.8.3 Output Buffer The output buffer provides enough current so that external buffers are not required and the power amplifier can interface directly to the device’s outputs. Figure 13: Output Stage OCP 15 VCCP BLKI OCP 22 OUT1 Video before output stage + VRef GND Clamp & Buffer Vib Vib Output Infra-black Level Note: Identical for video channels 2 and 3. 13/34 Functional Description STV9212 Table 3: OCP Timing Source Trigger Event OCPSC BLKPOL Timing Diagram ICP ICP Pulse 1 Don’t care OCP BLK Rising edge BLK OCP 0 Falling edge 14/34 0 BLK 1 OCP STV9212 2.9 Functional Description Output Infra-black Level, Cut-off and Brightness The schematic diagram of these functions is shown in Figure 14. Figure 14: Cut-off and Brightness Control Block Diagram I²C-bus field Output stage Vib 1 for 3 channels IBOF OUT1 OUT2 OUT3 Vib VRef Vibmin Video DC level DC VCOmax ViblDC MOD=1 MOD=0 IBLRG range 1 per channel DC:0 IBL3 IBL2 IBL1 MOD Cut-off Cut-off Cut-off AC:1 ViblAC range ~40kΩ ViblAC AC:1 BRIGRG 1 for 3 channels range BRIG VbriAC VCO DC:0 VbriDC DC Channel 3 Only CO1 CO2 CO3 VCOmin Brightness VbriDC VCO ~0V* VbriAC VCOmin GND Ch3 Ch1 Ch2 Note: Identical for CO1, CO2 and CO3 outputs except for “brightness” (VbriDC) that is only output at CO3 while MOD=0. The switches are drawn in their default positions. * ~0V when the output is left open 2.9.1 Output Infra-black Level The infra-black level of the video signal at the video outputs OUT1, OUT2 and OUT3 is positioned to the Vib reference by the output clamp circuit, thus defining the Output infra-black level. If the output clamp circuit is furnished with a correctly timed OCP (see corresponding sections), the output infra-black level equals Vib. Vib is composed of a fixed DC voltage (Vibmin), a variable DC voltage (Vibof) applied on all three channels and a per-channel variable DC voltage (Vibl (1,2,3)) as shown in Figure 15. In AC-coupling mode (bit MOD = 1), the Vibl part is suppressed and the Vib is therefore equal on all three channels, only varying with bits IBOF[5:0] acting on Vibof. This can be used to match the device’s outputs to the input of the video amplifier used (biasing). In DC-coupling mode (bit MOD = 0), Vibl (1,2,3) are separately set via bits IBL1[7:0], IBL2[7:0] and IBL3[7:0], respectively. This serves to adjust the cut-off points of the three CRT cathodes. In this case, Vibof can serve to pre-position the cut-off ranges in the factory adjustment procedure or/and to provide a rough brightness control. 15/34 Functional Description STV9212 Figure 15: Output Infra-black Level 19 22 GNDP OUT1 20 18 OUT2 OUT3 black infra-black Vibl(3) Vibl(1) Vibl(2) Vib(1) Vibof Vib(2) Vibmin Channel 1 2.9.2 Vib (3) DC: common cut-off/brightness AC: video amp. biasing I²C: IBOF Vibof Vibof Vibmin Vibmin Channel 2 DC: differential cut-off AC: Vibl(1,2,3) = 0V I²C: IBL1, IBL2, IBL3 fixed DC Channel 3 Cut-off and Brightness Control Outputs Outputs CO1, CO2 and CO3 provide a DC voltage controlled via bits BRIG[7:0], IBLx[7:0], IBLRG[7:0], BRIGRG[1:0] and MOD[7:0]. The principal of operation is shown in Figure 14. When bit MOD is in position AC (= 1), the output voltage is a sum of the “brightness” VbriAC, “cut-off” ViblAC and a fixed VCOmin providing a bottom limitation. The brightness adjustment is equally applied to all three CO1, CO2 and CO3 outputs. It varies depending on bits BRIG[7:0] and BRIGRG[1:0], with bits BRIGRG[1:0] controlling the range of BRIG adjustment. The cut-off adjustment is separate for each channel, having one I²C-bus field per channel: IBL1, IBL2 and IBL3. The ratio between the brightness and cut-off ranges depends on the brightness range selection. See Figure 16. Figure 16: CO1, CO2 and CO3 Outputs while MOD = 1 19 GNDP 17 16 15 CO1 CO2 CO3 ViblAC (3) ViblAC(1) ViblAC(2) VCO(1) VCO(3) cut-off I²C: IBL1, IBL2, IBL3 VbriAC VbriAC brightness through cathods I²C: BRIG VCOmin VCOmin VCOmin Channel 1 Channel 2 Channel 3 VbriAC VCO(2) fixed DC When bit MOD is in position DC (= 0), the output voltage on CO3 output is a sum of the “brightness” VbriDC and a fixed VCOmin providing a pedestal. Outputs CO1 and CO2 are floating with internal 16/34 STV9212 Functional Description resistors of approximately 40 kΩ to ground. The VbriDC varies with bits BRIG[7:0] and does not depend on bits BRIGRG[1:0]. See Figure 17. Figure 17: CO1, CO2 and CO3 Outputs while MOD = 0 19 GNDP 17 16 15 CO1 CO2 CO3 VCO(3) VbriDC VCOmin Channel 1 Channel 2 brightness through G1 I²C: BRIG fixed DC Channel 3 Note: Channels 1 and 2 shown with CO1 and CO2 outputs left open 17/34 Functional Description 2.10 STV9212 Signal Waveforms Figure 18 gives a summary of main signals waveforms. Clamp signals Control signals Figure 18: Signal Waveforms BLKI HS ICP OCP OSD signals Video input IN1 (2,3) FBLK OSD input OSD1 (2,3) Video output OUT1 (2,3) 2.11 Black-level Infra-black level Miscellaneous 2.11.1 Stand-by Mode The device is set in Stand-by mode either by means of bit PASTBY or by lowering the VCCP supply voltage below the VCCPS threshold. Once in Stand-by mode, the device does not process the video signal and its power consumption is significantly reduced. The I²C-bus interface remains operational. A low level is forced on the AMPCTL output. Refer to Section 4: Electrical Specifications for values. 2.11.2 AMPCTL Output The AMPCTL is designed to control a video power amplifier. It provides a three-level logical signal that depends on bits ASTBY and ABLEN, as well as on the operating mode (stand-by / normal) of the device. Figure 19 gives all possible states of the AMPCTL output. Refer to Section 4: Electrical Specifications for electrical parameter values. Pin AMPCTL is of push-pull type. It must not directly 18/34 STV9212 Functional Description be grounded in the application and it can be left floating. Only video amplifiers provided with an appropriate control input can take advantage of the signal on the AMPCTL output. Figure 19: AMPCTL Output States BLKI signal VAMPHI AMPCTL pin signal VAMPBL VAMPSB GND I²C-bus bits ASTBY PASTBY ABLEN VCCP X 1 0 0 X 1 X 0 0 X 1 >VSTBTH 0 >VSTBTH X <VSTBTH X X >VSTBTH Note: X stands for “don’t care” value 19/34 I²C-Bus Interface Specifications 3 STV9212 I²C-Bus Interface Specifications The device is compatible to general I²C-bus specification. Its slave write address is DCh. Subaddress (Sad) auto-incrementing is not available. Only Write mode is supported. The control register map is given in Table 4. Bold weight denotes default values assumed at power-on reset. The power-on reset is effected every time that the supply voltage on VCCA pin drops below VPORTH threshold (Refer to electrical specifications). In order to ensure compatibility with future devices, all “Reserved” bits are to be set to 0 once uploaded by the control software. Table 4: I²C-Bus Register Map Sad 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 20/34 b7 1 b6 0 b5 b4 b3 0 CRST 0 b2 b1 b0 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BRIG 1 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 DRIVE1 0 DRIVE2 0 DRIVE3 0 Reserved 0 OSDCRST Reserved 0 OCPTG 0:BLK 1:ICP ASTBY 0:Normal 1:Standby 0 0 TST1 TST0 0:Normal 0:Normal 1:Test 1:Test ABLEN Reserved 0:Bl. disable 0 1:Bl. enable 1 0 0 1 0 0 1 PASTBY 0:Normal 1:Standby VIP 0:0.2V 1:0.4V PBGEN 0:Disable 1:Enable PBVIVEN 0:Disable 1:Enable 0 Reserved 0 1 0 TST4 0:Normal 1:Test 0 PBINS Reserved 0:PB Pin 0 1:Perman. PBVIVAM 0 0 0 Reserved 0 Reserved 0 Reserved 0 BRIGRG 1 1 0 1 0 BCSC1 BCWDTH 0:Trig mode 0 1 1:HS pulse TST2 Reserved MOD 0:DC 0:Test 0 1:AC 1:Normal IBL1 0 0 0 IBL2 0 0 0 IBL3 0 0 0 TST3 0:Normal 1 0 1:Test IBOF 0 0 PBCRST 0 Reserved 1 0 1 0 1 BCSC0 0:HS trig 1:BLK trig BLKPOL 0:Non-inv. 1:Inverted 0 0 0 0 0 0 0 0 BW IBLRG 0:Wide 0 1:Narrow PBBRIG 0 PBVIVTC Reserved 0 0 0 BCEDGE 0:Rising 1:Falling SWBLK 0:Disable 1:Enable 1 Reserved 0 0 STV9212 3.1 I²C-Bus Interface Specifications I²C-bus Register Descriptions Bit 0 = Reserved Sad01 Read/Write Reset Value: 1000 0000 (80h) 7 Sad05 0 CRST[6:0] Values 00 and 7Fh in field CRST[6:0] are prohibited. Bits[7:1] = Contrast Adjustment (CRST) Bit 0 = Reserved 7 0 DRIVE3[6:0] Values 00 and 7Fh in field DRIVE3[6:0] are prohibited. Bits[7:1] = Gain Adjustment on Channel 3 (DRIVE3) Bit 0 = Reserved. Sad02 Read/Write Reset Value: 1000 0000 (80h) 7 Read/Write Reset Value: 1000 0000 (80h) 0 BRIG[7:0] Bits[7:0] = Brightness Adjustment (BRIG) In AC mode, this value is added to infrablack levels and output on pins CO1, CO2 and CO3. In DC mode, it is output all alone on pin CO3. Sad06 Read/Write Reset Value: 0000 0001 (01h) 7 0 BRIGRG [1:0] Sad03 Bits[7:2] = Reserved. Bits[1:0]= Brightness Adjustment Range (BRIGRG) Four positions. See Section 4.4: Dynamic Electrical Characteristics. Read/Write Reset Value: 1000 0000 (80h) Sad07 7 0 DRIVE1[6:0] Read/Write Reset Value: 0000 1001 (09h) Values 00 and 7Fh in field DRIVE1[6:0] are prohibited. Bits[7:1] = Gain Adjustment on Channel 1 (DRIVE1) Bit 0 = Reserved Bits[7:4] = Reserved. Bits[3:0]= OSD Contrast Adjustment Sad04 Sad08 Read/Write Reset Value: 1000 0000 (80h) Read/Write Reset Value: 0000 0100 (04h) 7 7 OSDCRST[3:0] 0 DRIVE2[6:0] Values 00 and 7Fh in field DRIVE2[6:0] are prohibited. Bits[7:1] = Gain Adjustment on Channel 2 (DRIVE2) 0 7 OCPT G 0 TST[1:0] BCED BCSC BCSC BCWDTH[1:0] GE 0 1 Bit 7 = Output clamping pulse selection 0: Pulse triggered by BLK input (default) 1: Internal ICP pulse 21/34 I²C-Bus Interface Specifications STV9212 Bits[6:5] = Test mode activation for device testing in fabrication. When performing software blanking through SWBLK bit, TST1 bit must be set to 1. 0: Normal operation mode (Default) 1: Test mode Bits[4,0] = Blanking and clamping pulse source. BCSC1 BCSC0 Selected Source 0 0 1 0 1 Don’t care HS pin trigger (Default) BLK pin trigger HS pin pulse Bit 1 = Bits[3:2] = Width of ICP pulse when bit BCSC1 is 0. BCWDTH 0 0 1 1 0 1 0 1 Bit 3 = Bit 2 = Bit 0 = BCPC Width 0.33 µs 0.66 µs (Default) 1 µs 1.33 µs 0: Test mode 1: Normal operation mode (Default) Reserved. Application mode selection. 0: Application with DC-coupled cathodes. (Default) 1: Application with AC-coupled cathodes. Permanent blanking of video channels through software. 0: Disable, blanking gated with signal on BLK pin. (Default) 1: Permanent blanking. Bit TST1 must also be set to 1. Blanking signal (H-fly back) polarity inversion. For correct operation, the internal BLKI pulse after this controlled inversion must be positive. 0: Non Inverted, good for positive blanking pulse (Default) 1: Inverted, good for negative blanking pulse Bit 1 = When HS pin is selected to trigger the ICP pulse generator. 0: Trailing edge of HS pulse (Default) 1: Leading edge of HS pulse Sad0A, Sad0B and Sad0C When BLK pin is selected to trigger the ICP pulse generator: Read/Write Reset Value: 1000 0000 (80h) BCEDGE BLKPOL Trigger on BLK 0 0 1 1 0 1 0 1 Rising edge (default) Falling edge Falling edge Rising edge 7 IBL1[7:0] IBL2[7:0] IBL3[7:0] Bits[7:0] = Infra-black (Cut-off) Level Control, Channels 1 to 3 (IBLx) In DC-coupling mode, the register controls the pedestal of corresponding video channel signal. In AC-coupling mode, the register controls the level on outputs CO1, CO2 or CO3, respectively. Refer to BLKPOL bit description. Sad09 Read/Write Reset Value: 0001 0000 (10h) 7 ASTB ABLE Y N 0 TST2 MOD SWBL BLKP K OL Bit 7 = Amplifier standby selection. 0: Normal (default) 1: Standby Bit 6 = Amplifier blanking enable. The bit is “don’t care” whenever bit ASTBY is in Standby position. 0: Blanking pulse not generated (default) 1: Blanking pulse generated Bit 5 = Reserved. Bit 4 = Test mode activation for device testing in fabrication. 22/34 0 Sad0D Read/Write Reset Value: 0000 1000 (08h) 7 PAST BY 0 TST[4:3] BW[3:0] Bit 7 = Preamplifier and Amplifier STandBY selection 0: Normal (default) 1: Standby Bit 6 = Reserved. STV9212 I²C-Bus Interface Specifications Bits[5:4] = Test mode activation bits for device testing in fabrication. 0: Normal operation mode (Default) 1: Test mode Bits[3:0] = Internal band width limitation control. Refer to electrical characteristics. Sad0E Read/Write Reset Value: 1100 0001 (C1h) 7 VIP 0 IBOF[5:0] Bit 7 = PictureBooST General Enable. (PBGEN) 0: Disable, function inhibited (Default) 1: Enable, function active Bit 6 = PictureBooST Insertion Control. (PBINS) 0: PB pin insertion (Default) 1: Permanent insertion regardless of signal on PB pin Bit 5 = Reserved. Bits[4:3] = PictureBooST Contrast Control (PBCRST) Bit 2 = Reserved. Bits[1:0] = PictureBooST Brightness Control (PBBRIG) IBLR G Sad10 Bit 7 = Video Insertion Pulse depth. 0: 0.2V 1: 0.4V (default) Bits[6:1] = Infra-black level offset control simultaneously on all three video channels. Bit 0 = Control range of infra-black level adjustments via IBL1, IBL2 and IBL3 registers. Acts either on video signal channels or CO1, CO2, CO3 outputs. Refer to electrical characteristics. 0: Wide 1: Narrow (default) Read/Write Reset Value: 0010 1000 (28h) 7 PBVIV PBVIVAM[1:0] EN Read/Write Reset Value: 0000 1001 (09h) PBGE PBIN N S PBVIVTC[2:0] Bit 7 = PictureBooST vivacity and brightness enable. 0: Disable (default) 1: Enable Bits[6:5] = PictureBooST Vivacity Amplitude Control. Bit 4 = Reserved. Bits[3:1] = PictureBooST Vivacity Time Constant Control. Bit 0 = Reserved. Sad0F 7 0 0 PBCRST[1:0] PBBRIG[1:0] 23/34 Electrical Specifications STV9212 4 Electrical Specifications 4.1 Absolute Maximum Ratings All voltages refer to the GNDA pin. Symbol Parameter Min. Max. Units VCCA Supply voltage on VCCA (Pin 7) TBD 5.5 V VCCP Supply voltage on VCCP (Pin 21) TBD 8.8 V VIN Voltage at any pin except video inputs and supply pins TBD 5.5 V VI Voltage at video inputs (Pins 1,3 and 5) TBD 1.4 V VESD ESD susceptibility Human Body Model (100 pF discharge through 1.5 kΩ) TBD ±2 kV TSTG Storage Temperature -40 +150 °C TOPER Operating Junction Temperature -40 +150 °C 4.2 Thermal Data Symbol Parameter Min. RthJA Junction-to-Ambient Thermal Resistance TAMB Operating Ambient Temperature 4.3 Typ. Max. 60 Units °C/W 0 70 °C/W Static Electrical Characteristics TAMB = 25°C, VCCA = 5V, and VCCP = 8V, unless otherwise specified. All voltages refer to the GNDA pin. Symbol Parameter Test Conditions Min. Typ. Max. Units Supply VCCA Supply Voltage Pin 7 4.5 5 5.5 V VCCP Power Stage Supply Voltage Pin 21 4.5 8 8.8 V VCCPS Power Supply Voltage Stand-by Threshold Pin 21 2.5 3.0 3.5 V ICCA VCCA Supply Current VCCA = 5V (PBGEN Disable) VCCA = 5V (PBGEN Enable) 65 85 mA mA ICCP VCCP Supply Current VCCP = 8V 50 mA Total Supply Current in Stand-by Mode Pin 21 and pin 7 IS 6 mA 1 V VCCP -0.5V V 0.8 V Inputs and Outputs 24/34 VI Video Input voltage amplitude VO Output voltage swing VIL Low level input voltage (TTL) OSD, FBLK, PB, HS,BLK VIH High level input voltage (TTL) OSD, FBLK, PB, HS,BLK 2.4 IIL BLK input current BLK -0.1 +1.0 mA IIN Input current OSD, FBLK, PB -1 1 µA 0.7 0.5(1) V STV9212 Electrical Specifications Symbol RHS Parameter Test Conditions Min. Typ. Max. Units kΩ Input resistance HS 40 VAMPSB Output voltage at AMPCTL pin, standby (Figure 18) I²C-bus bit ASTBY = 1 or/and VCCP < VCCPS Sink current 200µA 80 200 mV VAMPBL Output voltage at AMPCTL pin, blanking (Figure 18) I²C-bus bit ASTBY = 1 I²C-bus bit ABLEN = 1 Sink current 0µA BLKI at high level 1.6 TBD V VAMPHI Output voltage at AMPCTL pin, no standby, no blanking (Figure 18) I²C-bus bit ASTBY = 0 and VCCP > VCCPS Sink current 0µA 4.4 TBD 3.1 V Dynamic Electrical Characteristics TAMB = 25°C, VCCA = 5 V, VCCP = 8 V, Vi = 0.7 VPP, C LOAD = 5 pF, RS = 100 Ω serial resistor between output pin and CLOAD, unless otherwise specified. “x” denotes channel number and can assume values of 1, 2 and/or 3. All voltages refer to the GNDA pin. Symbol Parameter Test Conditions Min. Typ. Max. Units Video Output Signal (Pins 18, 20 and 22) - Contrast and Drive Maximum total gain for video path with PictureBooST off I²C-bus fields CRST = 7Eh, DRIVEx = 7Eh PBGEN = 0 VOM Maximum video output voltage(2) I²C-bus fields CRST = 7Eh, DRIVEx = 7Eh PBGEN = 0 PBGEN = 1 VON Nominal video output voltage I²C-bus fields CRST = 40h, DRIVEx = 40h (POR state) CAR Contrast control range DAR GM G 12 dB 2.8 4.0 V V TBD V Max. to min. contrast (CRST = 7Eh to CRST = 01h) 28 dB Drive control range Max. to min. drive (DRIVEx = 7Eh to DRIVEx = 01h) 13 dB Gain matching (3) I²C-bus fields CRST = 40h, DRIVEx = 40h (POR state) ±0.1 dB 4.9 0 V V 0.4 0.2 Vpp Vpp 0.4 V 2.1 0 V V 0 V 1.3 1.8 V V Video Output Signal - OSD VOSD OSD insertion output level referenced to output black level DRIVEx = 7Eh OSDCRST = 0Fh OSDCRST = 0h Video Output Signal - VIP VVIP Video Insertion Pulse level From Infrablack level to black level VIP = 1 VIP = 0 (4) Video Output Signal - Infra Black Level (Figure 15) Vibmin Vibof Vibl[x] Infra black level pedestal Infra black offset component IBOF = 3Fh IBOF = 0h Infra black level component IBLx = 0h or MOD = 1 (AC mode) IBLx = FFh, MOD = 0 (DC mode) IBLRG = 1 IBLRG = 0 25/34 Electrical Specifications Symbol STV9212 Parameter Test Conditions Min. Typ. Max. Units Cut-off Output (Pins CO1, CO2 and CO3) VCOmin Pedestal level on COx outputs VCOmax Upper limitation on COx outputs Sum of VbriAC+ViblAC or VbriDC exceeding the limit Brightness component in AC mode (Figure 16) MOD = 1 (AC mode) BRIG = 0h BRIG = FFh: BRIGRG = 00b BRIGRG = 01b BRIGRG = 10b BRIGRG = 11b MOD = 0 (DC mode) BRIG = 0h BRIG = FFh VbriAC VbriDC Brightness component in DC mode on CO3 pin(6) (Figure 17) 0.5 V VCCA -0.5V V 0 V 0.4 0.8 1.25 1.9 V V V V 0 4 V V 0 V MOD = 0 (DC mode) MOD = 1 (AC mode) IBLx = 0h IBLx = FFh: IBLRG = 0 IBLRG = 1 0 V 3.7 1.85 V V Maximum gain PBGEN = 1 PBCRST = 00b PBCRST = 01b PBCRST = 10b PBCRST = 11b 0.8 1.6 2.3 3 dB dB dB dB VBriPB PictureBooST brightness expressed in equivalent input level PBGEN = 1 and PBVIVEN = 1 PBBRIG = 00b PBBRIG = 01b PBBRIG = 10b PBBRIG = 11b 64 48 32 16 mV mV mV mV Vviv/A Vivacity amplitude as percentage of its host square pulse level before PictureBooST(“A” in Figure 9) PBGEN = 1 and PBVIVEN = 1 PBVIVAM = 00b PBVIVAM = 01b PBVIVAM = 10b PBVIVAM = 11b 12.5 25 37.5 50 % % % % Vivacity time constant PBGEN = 1 and PBVIVEN = 1 PBVIVTC = 000b PBVIVTC = 001b PBVIVTC = 111b 0 35 245 ns ns ns VABL>3.2 V VABL = 1 V 0 -15 dB dB 3 V 0 -2 µA µA VOUT = 2VPP (VIP exclusive) BW = 0Fh BW = 00h 3.5 7 ns ns VOUT = 2VPP, sinus wave, -3dB BW = 0Fh BW = 00h TBD TBD MHz MHz ViblAC(x) Cut-off component PictureBooST Block (Figure 9) GPB τviv ABL (Figure 9) GABL VThABL IABL ABL gain ABL threshold voltage VABL = 3.2V VABL = 1V ABL input current Video Output Signal - Dynamic Performances (Figure 15) (5 ) tr, tf Rise Time, Fall Time BW Large signal bandwidth 26/34 STV9212 Symbol CT Electrical Specifications Parameter Test Conditions Crosstalk between Video Outputs 4.5 Min. VOUT = 2VPP f = 10 MHz f = 50 MHz Typ. Max. TBD TBD Units dB dB I²C-Bus Electrical Characteristics Tamb = 25° C, VCCA = 5 V, VCCP = 8 V, Vi = 0.7 VPP, CLOAD = 5 pF Symbol Parameter Test Conditions VIL Low Level Input Voltage VIH High Level Input Voltage IIN Input Current (Pins SDA, SCL) fSCL(Max.) VOL Typ. Max. Unit s 1.5 V On Pins SDA, SCL 3 0.4 V < VIN < 4.5 V V -10 SCL Maximum Clock Frequency +10 200 µA kHz SDA pin when ACK Sink Current = 6 mA Low Level Output Voltage 4.6 Min. 0.6 V I²C-Bus Interface Timing Requirements Symbol Parameter Min. Typ. Max. Units tBUF Time the bus must be free between two accesses 1300 ns tHDS Hold Time for Start Condition 600 ns tSUP Set-up Time for Stop Condition 600 ns tLOW The Low Period of Clock 1300 ns tHIGH The High Period of Clock 600 ns tHDAT Hold Time Data 300 ns tSUDAT Set-up Time Data 250 ns tr Rise Time of both SDA and SCL 1 µs tf Fall Time of both SDA and SCL 300 ns Figure 20: I²C-Bus Timing Diagram tBUF tHDAT SDA tHDS tSUDAT tSUP SCL tHIGH tLOW Notes on Electrical Characteristics Note 1. The video on the preamplifier output must remain above 0.5V even for high frequency signals. 2. Assuming that the video output signal remains inside the linear area of the preamplifier output (between 0.5V and VCCP - 0.5V). 27/34 Electrical Specifications STV9212 3. Matching measured between the different outputs. 4. When the Blanking signal is present on the BLK input, the VIP insertion pulse is always generated. Only its amplitude changes (see Figure 12). 5. tR, tF are simulated values, assuming an ideal input signal with rise/fall time = 0.1 ns. Measured between 10% and 90% of the pulse height. 6. When MOD = 0, the CO1 and CO2 are internally grounded through resistors. 28/34 STV9212 5 Soldering Information Soldering Information The device can be soldered by wave, dipping or manually. Wave soldering is the preferred method for mounting through-hole mount IC packages on a printed-circuit board. Soldering by dipping or by solder wave The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact with the joints for more than 5 seconds.The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (TSTG[max]). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. Manual soldering Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 °C, contact may last up to 5 seconds. 29/34 Package Mechanical Data 6 STV9212 Package Mechanical Data Figure 21: 24-Pin Plastic Dual In-Line Package, Shrink 300-mil Width E E1 A1 A2 A L Stand-off b b2 0.015 in. e eA eB c D E 24 13 0.015 in. 0.38 mm. Gage Plane E1 1 12 eC eB Table 5: Package Dimensions Millimeters Dim. A A1 A2 b b2 c D E E1 e eA eB eC L N 30/34 Min. Typ. Inches Max. Min. Typ. 5.08 0.51 3.05 0.38 0.89 0.23 22.35 7.62 6.10 0.00 2.54 3.30 0.46 1.02 0.25 22.61 6.40 1.78 7.62 3.30 4.57 0.56 1.14 0.38 22.86 8.64 6.86 Max. 0.200 0.020 0.120 0.015 0.035 0.009 0.880 0.300 0.240 10.92 1.52 0.000 3.81 0.100 Number of Pins 24 0.130 0.018 0.040 0.010 0.890 0.252 0.070 0.300 0.130 0.180 0.022 0.045 0.015 0.900 0.340 0.270 0.430 0.060 0.150 STV9212 7 Input/Output Diagrams Input/Output Diagrams Figure 22: Video Inputs Figure 25: Hsync Input VCCA VCCA 30k HIGH IMPEDANCE IN1 1 2 GNDA GNDA Idem for pads IN2 (3) and IN3 (5) Figure 23: ABL Input GNDL Figure 26: PictureBooST and OSD Inputs VCCA VCCA 1k ABL OSD1 9 4 GNDA GNDA Figure 24: Amplifier Control Output Idem for pads OSD2 (10), OSD3 (11) PB (8), FBLK (12) Figure 27: Analog Supplies VCCA VCCA GNDL 7 (8V) AMPCTL 23 GNDA LOGIC PART 100 GNDA 6 31/34 Input/Output Diagrams STV9212 Figure 28: I²C-Bus (8V) Figure 31: Output Stage Ground 30kΩ SCL 13 VCCA 4pF GNDL GNDA GNDP 19 30kΩ SDA 14 GNDA 4pF GNDL GNDA Figure 29: Output Stage Supply and Video Outputs Figure 32: Cut-off DAC Output Pins VCCA VCCP 19 (20V) OUT1 22 CO1 17 GNDA GNDA GNDP Idem for pads OUT2 (20) and OUT3 (18) Figure 30: Blanking / Video Clamping Sync Inputs VCCA BLK 24 GNDA 32/34 GNDL Idem for pads CO2 (16) and CO3 (15) STV9212 8 Revision History Revision History Table 6: Summary of Modifications Version Date Description 1.0 14 Nov 2002 First Issue 1.1 03 Jul 2003 Minor modifications. 33/34 STV9212 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. 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