STW18NK60Z N-CHANNEL 600V - 0.27Ω - 16A TO-247 Zener-Protected SuperMESH™ MOSFET TYPE STW18NK60Z ■ ■ ■ ■ ■ ■ VDSS RDS(on) ID Pw 600 V < 0.36 Ω 16 A 230 W TYPICAL RDS(on) = 0.27 Ω EXTREMELY HIGH dv/dt CAPABILITY 100% AVALANCHE TESTED GATE CHARGE MINIMIZED VERY LOW INTRINSIC CAPACITANCES VERY GOOD MANUFACTURING REPEATIBILITY DESCRIPTION The SuperMESH™ series is obtained through an extreme optimization of ST’s well established stripbased PowerMESH™ layout. In addition to pushing on-resistance significantly down, special care is taken to ensure a very good dv/dt capability for the most demanding applications. Such series complements ST full range of high voltage MOSFETs including revolutionary MDmesh™ products. 3 2 1 TO-247 INTERNAL SCHEMATIC DIAGRAM APPLICATIONS ■ HIGH CURRENT, HIGH SPEED SWITCHING ■ IDEAL FOR OFF-LINE POWER SUPPLIES ORDER CODES PART NUMBER MARKING PACKAGE PACKAGING STW18NK60Z W18NK60Z TO-247 TUBE April 2004 1/9 STW18NK60Z ABSOLUTE MAXIMUM RATINGS Symbol VDS VDGR VGS Parameter Value Unit Drain-source Voltage (VGS = 0) 600 V Drain-gate Voltage (RGS = 20 kΩ) 600 V Gate- source Voltage ± 30 V ID Drain Current (continuous) at TC = 25°C 16 A ID Drain Current (continuous) at TC = 100°C 10 A Drain Current (pulsed) 64 A IDM () PTOT VESD(G-S) dv/dt (1) Tj Tstg Total Dissipation at TC = 25°C 230 W Derating Factor 1.85 W/°C Gate source ESD(HBM-C=100pF, R=1.5KΩ) 6000 V 4.5 V/ns -55 to 150 °C Peak Diode Recovery voltage slope Operating Junction Temperature Storage Temperature ( ) Pulse width limited by safe operating area (1) ISD ≤16A, di/dt ≤ 200A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX. (*) Limited only by maximum temperature allowed THERMAL DATA Rthj-case Thermal Resistance Junction-case Max 0.54 °C/W Rthj-amb Tl Thermal Resistance Junction-ambient Max Maximum Lead Temperature For Soldering Purpose 50 300 °C/W °C Max Value Unit AVALANCHE CHARACTERISTICS Symbol Parameter IAR Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) 16 A EAS Single Pulse Avalanche Energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) 400 mJ GATE-SOURCE ZENER DIODE Symbol Parameter Test Conditions Min. BVGSO Gate-Source Breakdown Voltage Igs=± 1mA (Open Drain) 30 Typ. Max. Unit V PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the device’s integrity. These integrated Zener diodes thus avoid the usage of external components. 2/9 STW18NK60Z ELECTRICAL CHARACTERISTICS (TCASE =25°C UNLESS OTHERWISE SPECIFIED) ON/OFF Symbol Parameter Test Conditions Min. Typ. Max. Drain-source Breakdown Voltage ID = 1 mA, VGS = 0 IDSS Zero Gate Voltage Drain Current (VGS = 0) VDS = Max Rating VDS = Max Rating, TC = 125 °C 1 50 µA µA IGSS Gate-body Leakage Current (VDS = 0) VGS = ± 20V ±10 µA VGS(th) Gate Threshold Voltage VDS = VGS, ID = 100 µA RDS(on) Static Drain-source On Resistance VGS = 10V, ID = 8 A V(BR)DSS 600 Unit 3 V 3.75 4.5 V 0.27 0.36 Ω Typ. Max. Unit DYNAMIC Symbol gfs (1) Ciss Coss Crss Coss eq. (3) Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Test Conditions Min. VDS = 15 V, ID = 8 A VDS = 25V, f = 1 MHz, VGS = 0 13 S 3540 370 80 pF pF pF Equivalent Output Capacitance VGS = 0V, VDS = 0V to 420 V 220 pF td(on) tr td(off) tf Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time VDD = 300 V, ID = 8 A RG = 4.7Ω VGS = 10 V (Resistive Load see, Figure 3) 34 25.5 82 47 ns ns ns ns Qg Qgs Qgd Total Gate Charge Gate-Source Charge Gate-Drain Charge VDD = 480 V, ID = 16 A, VGS = 10V 106 21 55 170 nC nC nC Typ. Max. Unit 16 64 A A 1.6 V SOURCE DRAIN DIODE Symbol Parameter ISD ISDM (2) Source-drain Current Source-drain Current (pulsed) VSD (1) Forward On Voltage ISD = 16 A, VGS = 0 Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 18 A, di/dt = 100A/µs VDD = 100 V, Tj = 25°C (see test circuit, Figure 5) 500 5.6 22.6 ns µC A Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 16 A, di/dt = 100A/µs VDD = 100 V, Tj = 150°C (see test circuit, Figure 5) 650 8 24.2 ns µC A trr Qrr IRRM trr Qrr IRRM Test Conditions Min. Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. 2. Pulse width limited by safe operating area. 3. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS. 3/9 STW18NK60Z Safe Operating Area Thermal Impedance Output Characteristics Transfer Characteristics Transconductance 4/9 Static Drain-source On Resistance STW18NK60Z Gate Charge vs Gate-source Voltage Capacitance Variations Normalized Gate Thereshold Voltage vs Temp. Normalized On Resistance vs Temperature Source-drain Diode Forward Characteristics Normalized BVDSS vs Temperature 5/9 STW18NK60Z Maximum Avalanche Energy vs Temperature 6/9 STW18NK60Z Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuit For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 7/9 STW18NK60Z TO-247 MECHANICAL DATA DIM. mm. MIN. inch MAX. MIN. TYP. MAX. A 4.85 5.15 0.19 0.20 A1 2.20 2.60 0.086 0.102 b 1.0 1.40 0.039 0.055 b1 2.0 2.40 0.079 0.094 0.134 b2 3.0 3.40 0.118 c 0.40 0.80 0.015 0.03 D 19.85 20.15 0.781 0.793 E 15.45 15.75 0.608 e 5.45 0.620 0.214 L 14.20 14.80 0.560 L1 3.70 4.30 0.14 L2 18.50 0.582 0.17 0.728 øP 3.55 3.65 0.140 0.143 øR 4.50 5.50 0.177 0.216 S 8/9 TYP 5.50 0.216 STW18NK60Z Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners © 2004 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com 9/9