STMICROELECTRONICS TDA7411

TDA7411
ADVANCED CAR SIGNAL PROCESSOR
■
FULLY INTEGRATED SIGNAL PROCESSOR
OPTIMIZED FOR CAR RADIO
APPLICATIONS
■
FULY PROGRAMMABLE BY I2C BUS
INCLUDES AUDIOPROCESSOR, STEREODECODER WITH NOISE BLAMKER AND
MULTIPATH DETECTOR
SOFTMUTE FUNCTION
PROGRAMMABLE ROLL-OFF
COMPENSATION
NO EXTERNAL COMPONENTS
■
■
■
■
TQFP44
ORDERING NUMBER: TDA7411
DESCRIPTION
The TDA7411 is the successor of the TDA7407 in
the CSP family introduced by the TDA7460/61. It
uses the same innovative concepts and design
technologies allowing fully software programmability through I2C bus and overall cost optimization
for the system designer.
The device includes a three band audio processor
with extended configurable input and output stag-
es and absence of external components for filter
settings, a last generation stereo decoder with
multi path detector and a sophisticated stereo
blend, high cut control and noise cancellation circuitry.
Strength points of the CSP approach are flexibility
and overall cost/room saving in the application,
combined with high performances.
BLOCK DIAGRAM
October 2003
1/43
TDA7411
ABSOLUTE MAXIMUM RATINGS
Symbol
VS
Parameter
Value
Unit
10.5
V
Operating Supply Voltage
Tamb
Operating Ambient Temperature Range
-40 to 85
°C
Tstg
Operating Storage Temperature Range
-55 to 150
°C
SUPPLY
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
7.5
8
10
V
VS
Supply Voltage
IS
Supply Current
VS = 9V
45
mA
Ripple Rejection @ 1KHz
Audioprocessor (all filters flat)
60
dB
Stereodecoder + Audioprocessor
55
dB
Value
Unit
85
°C/W
SVRR
ESD
All pins are protected against ESD according to the MIL883 standard.
CDL
CDR
MDR
MDL
Cref
SubL
SubR
ACoutR
ACoutL
ACin0L
ACin0R
PIN CONNECTION (Top view)
44
43
42
41
40
39
38
37
36
35
34
AUXL
1
33
ACin1R
AUXC
2
32
ACin1L
AUXR
3
31
ACin2L
CDCHR+
4
30
ACin2R
CDCHR-
5
29
ACin3R
OutLF
10
24
OutRF
MPX
11
23
OutRR
Level
12
13
14
15
16
17
18
19
20
21
22
OutLR
25
AM
FreeL
NV-
SCL
GND
9
FreeR
26
SDA
8
AFS
VS
NV+
Mute
ACin3L
27
Qual
28
7
Mpin
6
MPout
CDCHLCDCHL+
PINCON-TDA7411
THERMAL DATA
Symbol
Rth-j pins
2/43
Parameter
Thermal Resistance Junction to pins
Max
TDA7411
PIN DESCRIPTION
Nr.
Name
1
AUXL
Quasi Differential Input Left
Function
Type
I
2
AUXC
Quasi Differential Input Common
I
3
AUXR
Quasi Differential Input Right
I
4
CDCHR+
Full Differential Input Right Plus
I
5
CDCHR-
Full Differential Input Right Minus (not used in quasi differential mode)
I
6
CDCHL-
Full Differential Input Left Minus (CDCHCom in Qdiff mode)
I
7
CDCHL+
Full Differential Input Left Plus
I
8
NV+
Mono Differential Input Plus
I
9
NV-
Mono Differential Input Minus
I
10
AM
AM Input
I
11
MPX
FM Stereo Decoder Input
I
12
Level
Level Input Stereo Decoder
I
13
MPin
Multi Path Input
I
14
MPout
Multi Path Output
O
15
Qual
Stereo Decoder Quality Output
O
16
AFS
Alternative Frequency Search Drive
I
17
Mute
Soft Mute Drive
18
SDA
I2C Data Line
I/O
I
19
SCL
I2C Clock Line
I
20
FreeR
Free Right Speaker Output
O
21
FreeL
Free Left Speaker Output
O
22
OutLR
Rear Left Speaker Output
O
23
OutRR
Rear Right Speaker Output
O
24
OutRF
Front Right Speaker Output
O
25
OutLF
Front Left Speaker Output
O
26
GND
Supply Ground
S
27
VS
Supply Voltage
S
28
ACin3L
Pre-speaker Input Three Left
I
29
ACin3R
Pre-speaker Input Three Right
I
30
ACin2R
Pre-speaker Input Two Right
I
31
ACin2L
Pre-speaker Input Two Left
I
32
ACin1L
Pre-speaker Input Three Left
I
33
ACin1R
Pre-speaker Input Three Right
I
34
ACin0R
Pre-speaker Input Zero Right
I
35
ACin0L
Pre-speaker Input Zero Left
I
36
ACoutL
Pre-speaker Output Left
O
37
ACoutR
Pre-speaker Output Right
O
38
SubR
Sub Channel Selector Output Right
O
39
SubL
Sub Channel Selector Output Left
O
40
Cref
Reference Capacitor Pin
O
41
MDL
Mini Disk Input Left
I
42
MDR
Mini Disk Input Right
I
43
CDR
Compact Disk Input Right (Test mode Output)
I
44
CDL
Compact Disk Input Left
I
Pin type legenda: I = Input ; O = Output; I/O = Input/Output; S = Supply; nc = not connected.
3/43
TDA7411
AUDIO PROCESSOR PART
Input Multiplexer
–
–
–
–
–
–
–
full differential stereo input configurable as quasi-differential input
quasi differential auxiliary stereo input
mini disk stereo input configurable as mono differential input
compact disk stereo input
mono differential navigation input
AM mono input
second multiplexer for sub channel output
Volume control
– 1dB attenuator
– Max. gain 15dB
– Max. attenuation 79dB
Bass Control
–
–
–
–
2nd order frequency response
Center frequency programmable in 4(5) steps
DC gain programmable
±15 x 1dB steps
Mid Control
–
–
–
–
2nd order frequency response
Center frequency programmable in 4 steps
Q-factor programmable in 2 steps
±15 x 1dB steps
Treble Control
– 2nd order frequency response
– Center frequency programmable in 4 steps
– ±15 x 1dB steps
Speaker Control
–
–
–
–
–
6 independent speaker controls in 1dB steps
max. gain 15dB
max. attenuation 79dB
implemented soft mute capability
speaker input multiplexer
Mute Functions
– independent direct fast mute controlled by I2C interface
– independent soft mute for Front L/R, Rear and Free controlled by I2C interface
– digitally controlled soft mute with 4 programmable mute-times
– pin controlled soft mute
soft mute monitor function @ Mute pin
4/43
TDA7411
ELECTRICAL CHARACTERISTICS
(VS = 8V; Tamb = 25°C; RL = 10KΩ; all gains = 0dB; f = 1KHz; unless otherwise specified)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
100
130
KΩ
INPUT SELECTOR
Rin
Input Resistance
all inputs except Phone
70
VCL
Clipping Level
THD < 0.3%
1.6
1.7
VRMS
SIN
Input Separation
80
100
dB
GIN MIN
Min. Input Gain
-0.5
0
0.5
dB
GIN MAX
Max. Input Gain
14
15
16
dB
GSTEP
Step Resolution
VDC
DC Steps
0.5
1
1.5
dB
Adjacent Gain Step
-5
0.5
5
mV
GMIN to GMAX
-10
5
10
mV
Differential
70
100
130
KΩ
Common Mode
70
100
130
KΩ
VCM = 1VRMS @ 1KHz
45
70
dB
VCM = 1VRMS @ 10KHz
45
60
dB
FULL AND QUASI DIFFERENTIAL STEREO INPUT
Rin
Input Resistance (see Figure 1)
CMRR
Common Mode Rejection Ratio
eN
Output Noise @ Speaker Outputs 20Hz to 20KHz flat; all stages 0dB
9
15
µV
MONO DIFFERENTIAL INPUT (NV and MD in differential mode)
Rin
CMRR
Input Resistance
Differential
40
56
KΩ
Common Mode Rejection Ratio
VCM = 1VRMS @ 1KHz
40
70
dB
VCM = 1VRMS @ 10KHz
40
60
dB
VOLUME CONTROL
GMAX
Max Gain
14
15
AMAX
Max Attenuation
74
79
ASTEP
Step Resolution
EA
ET
VDC
Attenuation Set Error
dB
dB
0.5
1
1.5
G = -20 to +20dB
-1.25
0
+1.25
dB
G = -60 to +20dB
-4
0
+3
dB
Tracking Error
DC Steps
16
dB
2
dB
Adjacent Attenuation Steps
0.1
3
mV
From 0dB to GMIN
0.5
5
mV
SOFT MUTE/AFS
AMUTE
TD
Mute Attenuation
80
Delay Time
100
dB
T1
0.24
ms
T2
0.48
ms
T3
10.1
ms
T4
20.2
ms
1
1
V
VTH low
Low Threshold for Mute/AFS-Pin
VTH high
High Threshold for SM -Pin
1.8
V
VTH high
High Threshold for AFS -Pin
2.4
V
VSMon
Monitor Voltage for SMon
2.4
V
RPD
Internal Pull-up Resistor
100
KΩ
BASS CONTROL
CRANGE
ASTEP
Control Range
±13
±15
±17
dB
Step Resolution
0.5
1
1.5
dB
5/43
TDA7411
ELECTRICAL CHARACTERISTICS (continued)
(VS = 8V; Tamb = 25°C; RL = 10KΩ; all gains = 0dB; f = 1KHz; unless otherwise specified)
Symbol
fC
QBASS
DCGAIN
Parameter
Center Frequency
Quality Factor
Bass-DC-Gain
Min.
Typ.
Max.
Unit
fC1
Test Condition
54
60
66
Hz
fC2
63
70
77
Hz
fC3
72
80
88
Hz
fC4
90
100
(150)(2)
110
Hz
Q1
0.9
1
1.1
Q2
1.1
1.25
1.4
Q3
1.3
1.5
1.7
Q4
1.8
2
2.2
DC = off
-1
0
1
dB
DC = on
3.5
4.4
5.5
dB
Control Range
±13
±15
±17
dB
Step Resolution
0.5
1
1.5
dB
MID CONTROL
CRANGE
ASTEP
fC
QBASS
Center Frequency
Quality Factor
fC1
450
500
550
Hz
fC2
0.9
1
1.1
kHz
fC3
1.35
1.5
1.65
kHz
fC4
1.8
2
2.2
kHz
Q1
0.9
1
1.1
Q2
1.8
2
2.2
TREBLE CONTROL
GMAX
Control Range
±13
±15
±17
dB
ASTEP
Step Resolution
0.5
1
1.5
dB
fC
Center Frequency
fC1
8
10
12
KHz
fC2
10
12.5
15
KHz
fC3
12
15
18
KHz
fC4
14
17.5
21
KHz
35
50
65
kΩ
SPEAKER ATTENUATORS
Rin
Impedance @ACin0,2,3
Rin
Impedance @ACin1
Rin1
35
50
65
kΩ
Rin2
28
40
52
kΩ
Rin3
21
30
39
kΩ
GMAX
Max. Gain
13
15
17
dB
1.5
dB
±2
dB
5
mV
AMAX
Max. Attenuation
-74
-79
ASTEP
Step Resolution
0.5
1
AMUTE
Output Mute Attenuation
80
90
EE
VDC
Attenuation Set Error
DC Steps
Adjacent Attenuation Steps
-5
0.1
d = 0.3%
1.6
1.8
dB
dB
AUDIO OUTPUTS
VCLIP
Clipping Level
RL
Output Load Resistance
CL
Output Load Capacitance
6/43
VRMS
2
kΩ
10
nF
TDA7411
ELECTRICAL CHARACTERISTICS (continued)
(VS = 8V; Tamb = 25°C; RL = 10KΩ; all gains = 0dB; f = 1KHz; unless otherwise specified)
Symbol
Parameter
ROUT
Output Impedance
VDC
DC Voltage Level
Test Condition
Min.
3.8
Typ.
Max.
Unit
30
120
Ω
4
4.2
V
3
6.5
10
15
µV
µV
GENERAL
eNO
Output Noise
BW = 20Hz - 20kHz
output muted
all gains = 0dB
6.5
S/N
d
Signal to Noise Ratio
Distortion
102
110
dB
bass, treble at +12dB;
a-weighted; VO = 2.6VRMS
96
100
dB
all stages 0dB
Mono Diff Inputs, Vout = 0.75VRMS
All other inputs, Vout = 1VRMS
VOUT=1VRMS ; Bass & Treble = 12dB
SC
Channel Separation L/R
ET
Total Tracking Error
VPOR
µV
all gains = 0dB;flat; VO = 2VRMS
0.04
0.1
0.05
0.15
%
%
80
100
AV = 0 to -20dB
-1
0
1
dB
AV = -20 to -60dB
-2
0
2
dB
Internal POR Voltage
dB
3
V
BUS INPUTS
VIL
Input Low Voltage
VIH
Input High Voltage
0.8
IIN
Input Current
VIN = 0.4V
VO
Output Voltage SDA
Acknowledge
VO = 1.6mA
2.5
-5
V
V
5
µA
0.4
V
1) The SM and AFS pin are active low (Mute = 0)
2) See description of Audio processor Part section 1.8.
7/43
TDA7411
DESCRIPTION OF THE AUDIOPROCESSOR PART
Input Multiplexer
– CDCH full differential input configurable as quasi-differential input
– auxiliary quasi-differential input
– CD stereo
– MD stereo configurable as mono-differential phone input
– mono-differential NV input
– AM mono
– and stereo decoder input.
Figure 1. Input Selectors TDA7411
8/43
TDA7411
Input stages
In the basic configuration one full differential, one quasi-differential, two single ended stereo, one monodifferential and two tuner (AM and MPX) inputs are available. In addition the ac coupling input Acin0 can
be used as single ended input for the input multiplexer.
The full-differential input can be switched into quasi-differential mode (see Fig. 2) and the MD single ended
input can be used as mono-differential input (see Fig.1).
Figure 2. Full differential input
AutoZero
In order to reduce the number of pins there is no AC coupling between the In-Gain and the following stage,
so that any offset generated by or before the In-Gain-stage would be transferred or even amplified to the
output. To avoid that effect a special Offset-cancellation-stage called AutoZero is implemented. This stage
is located after the In-Gain-stage to eliminate all offsets generated by the stereo decoder, the Input-Stages
and the In-Gain (Please notice that externally generated offsets, e.g. generated through the leakage current of the coupling capacitors, are not canceled).
The auto-zeroing is started every time the DATA-BYTE 0 is selected and takes a time of max. 0.3ms. To
avoid audible clicks the audio processor is muted before the tone control stage during this time.
AutoZero-Remain
In some cases, for example if the µP is executing a refresh cycle of the IIC-Bus-programming, it is not
useful to start a new AutoZero action because no new source is selected and an undesired mute would
appear at the outputs. For such applications the TDA7411 could be switched in the AutoZero-RemainMode (Bit 6 of the sub address byte). If this bit is set to high, the DATABYTE 0 could be loaded without
invoking the AutoZero and the old adjustment-value remains.
Sub Channel Multiplexer
All input stages are available as source in the sub channel multiplexer. The selected source is buffered
and available at the pins SubR, SubL.
9/43
TDA7411
Mute Capability of Audio Processor
The main channel and the sub channel of the TDA7411 can be muted after the Source selectors. This
mute (no soft mute!) must be started by I2C bus.
The digitally controlled SoftMute stages are placed in the speaker and allow muting/demuting of the signal
with an I2C-bus programmable slope. The mute process can either be activated by the SoftMute pin or by
the I2C-bus. The slope is realized in a special S-shaped curve to mute slowly in the critical regions (see
Figure 3).
Figure 3. Soft mute-Timing
Note: Please notice that a started Mute-action is always terminated and could not be interrupted by a
change of the mute -signal.
Using the IIC bus control the soft mute can be activated independently for FrontL, FrontR, Rear and Free.
For timing purposes the Bit 3 of the I2C-bus output register is set to 1 as soon as the soft mute of any
speaker is started until the end of demuting of all speakers. The Mute pin is able to work as monitor for
the same signal. The standard function of the pin is not influenced by the monitor function.
10/43
TDA7411
Bass
There are four parameters programmable in the bass stage:
Attenuation
Figure 4 shows the attenuation as a function of frequency at a center frequency of 80Hz.
Figure 4. Bass Control @ fC = 80Hz, Q = 1
15.0
10.0
5.0
0.0
-5.0
-10.0
-15.0
10.0
100.0
1.0K
10.0K
Center Frequency
Figure 5 shows the four possible center frequencies 60, 70, 80 and 100Hz.
Figure 5.
15.0
12.5
10.0
7.5
5.0
2.5
0.0
10.0
100.0
1.0K
10.0K
11/43
TDA7411
Quality Factors
Figure 6 shows the four possible quality factors 1, 1.25, 1.5 and 2.
Figure 6. Bass Quality factors @ Gain = 14dB, fC = 80Hz
15.0
12.5
10.0
7.5
5.0
2.5
0.0
10.0
100.0
1.0K
10.0K
DC Mode
In this mode the DC-gain is increased by 5.1dB. In addition the programmed center frequency and quality
factor is decreased by 25%, which can be used to reach alternative center frequencies or quality factors.
Figure 7. Bass normal and DC Mode @ Gain = 14dB, fC = 80Hz
15.0
12.5
10.0
7.5
5.0
2.5
0.0
10.0
100.0
1.0K
10.0K
Note: In general the center frequency, Q and DC-mode can be set independently. The exception from this
rule is the mode (5/xx1111xx) where the center frequency is set to 150Hz instead of 100Hz.
12/43
TDA7411
MID
There are 3 parameters programmable in the mid stage:
Attenuation
Figure 8 shows the attenuation as a function of frequency at a center frequency of 1kHz.
Figure 8. Mid Control @ fC = 1kHz, Q = 1
15.0
10.0
5.
0
0.
0
5.0
-10.
0
-15.
0
10.0
100.
0
1.0K
10.0K
Center Frequency
Figure 9 shows the four possible center frequencies 500Hz, 1kHz, 1.5kHz and 2kHz.
Figure 9.
15.0
12.5
10.0
7.
5
5.
0
2.
5
0.
0
10.0
100.
0
1.0K
10.0K
13/43
TDA7411
Quality Factor
Figure 10 shows the two possible quality factors 1 and 2 at a center frequency of 1kHz.
Figure 10. Mid Q-factor @ fC = 1kHz, Gain=14dB
15.0
12.5
10.0
7.
5
5.
0
2.
5
0.
0
10.0
100.
0
1.0K
10.0K
TREBLE
There are two parameters programmable in the treble stage:
Attenuation
Figure 11 shows the attenuation as a function of frequency at a center frequency of 17.5kHz.
Figure 11. Treble Control @ fC = 17.5kHz
15.0
10.0
5.0
0.0
-5.0
-10.0
-15.0
10.0
14/43
100.0
1.0K
10.0K
TDA7411
Center Frequency
Figure 12 shows the four possible center frequencies 10k, 12.5k, 15k and 17.5kHz.
Figure 12. Treble Center Frequencies @ Gain = 14dB
15.0
12.5
10.0
7.5
5.0
2.5
0.0
10.0
100.0
1.0K
10.0K
Speaker Coupling
In some applications additional signal manipulations are desired, for example surround-sound or moreband-equalizing. For this purpose an AC-Coupling with four different AC-Coupling inputs is placed before
the speaker-attenuators.
The input-impedance of the AC-Inputs is always 50kΩ with exception of AC input ACin1, which has programmable input impedance. For ACin3 exists an internal mixing stage and an internal mono low pass
filter, which is available as input only for the speaker FreeL/R.
There are two possibilities for internal DC Coupling:
– main channel after the bass filter
– main channel after the middle filter (same as at ACout pin)
The I2C bus programming tables shows the possible speaker sources.
15/43
TDA7411
Low Pass Filter
Figure 13 shows the five possible corner frequencies of the low pass filter:
Figure 13. Low Pass Corner Frequencies
0
-3
dB
-10
-20
-30
-40
10
100
Hz
100
0
Anti-Radiation-Filter
An Anti-Radiation-Filter is implemented to suppress the radiation at the SC-clock-frequency and its harmonics. This radiation is only present if the stereo decoder is selected and/or SC-Filters are active
(<>0dB). If not, the filter can be switched off in order to optimize the noise-performance.
Speaker Attenuator
The speaker-attenuators have exactly the same control range like the Volume-stage. Every stereo speaker stage has an implemented independently I2C controlled and Mute pin controlled SoftMute stage (see
section mute capability of AP).
16/43
TDA7411
STEREODECODER PART
Features:
– no external components necessary
– PLL with adjustment free, fully integrated VCO
– automatic pilot dependent MONO/STEREO switching
– very high suppression of intermodulation and interference
– programmable Roll-Off compensation
– dedicated RDS-Soft mute
– High cut- and Stereo blend-characteristics programmable in a wide range
– internal Noise blanker with several threshold controls
– alternative frequency search function
– Multipath-detector with programmable internal/external influence
– I2C-bus control of all necessary functions
.
ELECTRICAL CHARACTERISTICS
(VS = 8V; deemphasis time constant = 50µs,VMPX = 500mV(75KHz deviation), fm= 1KHz, Gv = 6dB,
Tamb = 27°C; unless otherwise specified)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
Vin
MPX Input Level
0.5
1.25
VRMS
Rin
Input Resistance
70
100
130
KΩ
GMIN
Min. Input Gain
1.5
3.5
4.5
dB
GMAX
Max. Input Gain
8.5
11
12.5
dB
GSTEP
Step Resolution
1.75
2.5
3.25
dB
35
60
SVRR
Supply Voltage Ripple Rejection
α
Max. channel Separation
THD
Total Harmonic Distortion
S+N
-------------N
Signal plus Noise to Noise Ratio
Gv = 3.5dB
Vripple = 100mV; f = 1KHz
30
dB
50
0.02
A-weighted, S = 2VRMS
80
91
15
dB
0.3
%
dB
MONO/STEREO-SWITCH
VPTHST1
Pilot Threshold Voltage
for Stereo, PTH = 1
10
VPTHST0
Pilot Threshold Voltage
25
mV
for Stereo, PTH = 0
15
25
35
mV
VPTHMO1 Pilot Threshold Voltage
for Mono, PTH = 1
7
12
17
mV
VPTHMO0 Pilot Threshold Voltage
for Mono, PTH = 1
10
19
25
mV
PLL
∆f/f
Capture Range
0.5
%
DEEMPHASIS and HIGHCUT
tHC50
Deemphasis Time Constant
Bit 7, Subadr, 10 = 0,
VLEVEL >> VHCH
25
50
75
µs
tHC75
Deemphasis Time Constant
Bit 7, Subadr, 10 = 1,
VLEVEL >> VHCH
50
75
100
µs
tHC50
Highcut Time Constant
Bit 7, Subadr, 10 = 0,
VLEVEL >> VHCL
100
150
200
µs
tHC75
Highcut Time Constant
Bit 7, Subadr, 10 = 1,
VLEVEL >> VHCL
150
225
300
µs
17/43
TDA7411
ELECTRICAL CHARACTERISTICS (continued)
(VS = 8V; deemphasis time constant = 50µs,VMPX = 500mV(75KHz deviation), fm= 1KHz, Gv = 6dB,
Tamb = 27°C; unless otherwise specified)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
5
5.3
Unit
STEREOBLEND-and HIGHCUT-CONTROL
REF5V
Internal Reference Voltage
TCREF5V
Temperature Coefficient
4.7
3300
V
ppm
LGmin
Min. LEVEL Gain
-1
0
1
dB
LGmax
Max. LEVEL Gain
8
10
12
dB
LGstep
LEVEL Gain Step Resolution
0.3
0.67
1
dB
VSBLmin Min. Voltage for Mono
25
29
33
%REF5V
VSBLmax Min. Voltage for Mono
54
58
62
%REF5V
VSBLstep Step Resolution
2.2
4.2
6.2
%REF5V
VHCHmin Min. Voltage for NO Highcut
38
42
46
%REF5V
VHCHmax Min. Voltage for NO Highcut
62
66
70
%REF5V
VHCHstep Step Resolution
5
8.4
12
%REF5V
VHCLmin Min. Voltage for FULL Highcut
12
17
22
%VHCH
VHCLmax Max. Voltage for FULL Highcut
28
33
38
%VHCH
VHCLstep Step Resolution
2.2
4.2
6.2
%VHCH
40
50
Carrier and harmonic suppression at the output
α19
Pilot Signal f = 19KHz
α38
Subcarrier f = 38KHz
75
dB
α57
Subcarrier f = 57KHz
62
dB
α76
Subcarrier f = 76KHz
90
dB
dB
Intermodulation (Note 1)
α2
fmod = 10KHz, fspur = 1KHz
65
dB
α3
fmod = 13KHz, fspur = 1KHz
75
dB
70
dB
75
dB
Traffic Ratio (Note 2)
α57
Signal f = 57KHz
SCA - Subsidiary Communications Authoorization (Note 3)
α67
Signal f = 67KHz
ACI - Adjacent Channel Interference (Note 4)
α114
Signal f = 114KHz
95
dB
α190
Signal f = 190KHz
84
dB
Notes to the characteristics:
1. Intermodulation Suppression:
V O ( sig na l ) ( at1 kHz )
α 2 = ----------------------------------------------------- ; fs = (2 x 10kHz) - 19kHz
V O ( s pu rious ) ( a t1kHz )
V O ( sig na l ) ( at1 kHz )
- ; fs = (3 x 13kHz) - 38kHz
α 3 = ----------------------------------------------------V O ( s pu rious ) ( a t1kHz )
measured with: 91% pilot signal; fm = 10kHz or 13kHz.
2. Traffic Radio (V.F.) Suppression: measured with: 91% stereo signal; 9% pilot signal; fm=1kHz; 5% sub-
18/43
TDA7411
carrier (f = 57kHz, fm = 23Hz AM, m = 60%)
V O ( sig nal ) ( at1 kHz )
α57 ( V.W > F. ) = ------------------------------------------------------------------------V O ( sp uriou s ) ( at1k Hz ± 23k Hz )
3. SCA ( Subsidiary Communications Authorization ) measured with: 81% mono signal; 9% pilot signal;
fm = 1kHz; 10%SCA - subcarrier ( fs = 67kHz, unmodulated ).
V O ( si gna l ) ( at1 kHz )
α 67 = ----------------------------------------------------- ; Fs =(2 x 38kHz) - 67kHz
V O ( spu riou s ) ( a t9k Hz )
4. ACI ( Adjacent Channel Interference ):
V O ( s igna l ) ( a t1kHz )
- ; Fs = 110kHz - (3 x 38kHz)
α 114 = ----------------------------------------------------V O ( sp uriou s ) ( at4k Hz )
V O ( s igna l ) ( a t1kHz )
α 114 = ----------------------------------------------------- ; Fs = 186kHz - (5 x 38kHz)
V O ( sp uriou s ) ( at4k Hz )
measured with: 90% mono signal; 9% pilot signal; fm =1kHz; 1% spurious signal( fs = 110kHz or 186kHz,
unmodulated).
NOISE BLANKER PART
Features:
– internal 2nd order 140kHz high-pass filter
– programmable trigger threshold
– trigger threshold dependent on high frequency noise with programmable gain
– additional circuits for deviation- and fieldstrength-dependent trigger adjustment
– very low offset current during hold time due to opamps with MOS inputs
– 4 selectable pulse suppression times
– programmable noise rectifier charge/discharge current
ELECTRICAL CHARACTERISTICS (continued)
Symbol
VTR
Parameter
Trigger Threshold
0) 1)
VTRNOISE Noise Controlled Trigger
Threshold 2)
VRECT
Rectifier Voltage
Test Condition
meas. with VPEAK = 0.9V
meas. with VPEAK = 1.5V
VMPX = 0mV
VMPX = 50mV; f = 150KHz
VMPX = 200mV; f = 150KHz
Min.
Typ.
Max.
Unit
NBT = 111
(c)
30
(c)
mVOP
NBT = 110
(c)
35
(c)
mVOP
NBT = 101
(c)
40
(c)
mVOP
NBT = 100
(c)
45
(c)
mVOP
NBT = 011
(c)
50
(c)
mVOP
NBT = 010
(c)
55
(c)
mVOP
NBT = 001
(c)
60
(c)
mVOP
NBT = 000
(c)
65
(c)
mVOP
NCT = 00
(c)
260
(c)
mVOP
NCT = 01
(c)
220
(c)
mVOP
NCT = 10
(c)
180
(c)
mVOP
NCT = 11
(c)
140
(c)
mVOP
NRD 6) = 00
0.5
0.9
1.3
V
1.5
1.7
2.1
V
3.5
V
19/43
TDA7411
ELECTRICAL CHARACTERISTICS (continued)
Symbol
Parameter
Test Condition
VRECT DEV deviation dependent
rectifier Voltage 3)
means. with
VMPX = 500mV
(75KHz dev.)
VRECT FS Fieldstrength Controlled
Rectifier Voltage 4)
TS
Suppression Pulse
Duration 5)
means. with
VMPX = 0mV
VLEVEL << VSBL
(fully mono)
Signal HOLDNin Testmode
Min.
Typ.
Max.
Unit
OVD = 11
0.5
0.9(off)
1.3
VOP
OVD = 10
0.9
1.2
1.5
VOP
OVD = 01
1.7
2.0
2.3
VOP
OVD = 00
2.5
2.8
3.1
VOP
FSC = 11
0.5
0.9(off)
1.3
V
FSC = 10
0.9
1.4
1.5
V
FSC = 01
1.7
1.9
2.3
V
FSC = 00
2.1
2.4
3.1
µs
BLT = 10
32
µs
BLT = 01
25.5
µs
BLT = 00
VRECTADJ Noise Rectifier discharge
adjustment 6)
SRPEAK
VADJMP
Noise Rectifier Charge
Noise Rectifier adjustment
through Multipath 8)
Signal PEAK in Testmode
Signal PEAK in Testmode
Signal PEAK in Testmode
V
38
BLT = 00
µs
22
6)
(c)
0.3
(c)
V/ms
NRD = 01 6)
(c)
0.8
(c)
V/ms
NRD = 10 6)
(c)
1.3
(c)
V/ms
NRD = 11 6)
(c)
2.0
(c)
V/ms
PCH = 0 7)
(c)
10
(c)
mV/µs
PCH = 1 7)
(c)
20
(c)
mV/µs
MPNB = 00 8)
(c)
0.3
(c)
V/ms
MPNB = 01 8)
(c)
0.5
(c)
V/ms
MPNB = 10 8)
(c)
0.7
(c)
V/ms
MPNB = 11 8)
(c)
0.9
(c)
V/ms
NRD = 00
(c) = by design/characterization functionally guaranteed through dedicated test mode structure
0) All Thresholds are measured using a pulse with TR =2µs, THIGH = 2µs and TF = 10µs. The repetition rate must not increase the PEAK
voltage.
Figure 14. Timing
VIN
VOP
DC
D97AU636
TR
THIGH
TF
Time
1) NBT represents the Noiseblanker Byte bits D2, D0 for the noise blanker trigger threshold
2) NAT represents the Noiseblanker Byte bit pair D 4, D3 for the noise controlled triggeradjustment
3) OVD represents the Noiseblanker Byte bit pair D7, D6 for the over deviation detector
4) FSC represents the Fieldstrength Byte bit pair D1, D0 for the fieldstrength control
5) BLT represents the Speaker RR Byte bit pair D7, D6 for the blanktime adjustment
6) NRD represents the Configuration-Byte bit pair D1, D0 for the noise rectifier discharge-adjustment
7) PCH represents the Stereodecoder-Byte bit D5 for the noise rectifier charge-current adjustment
8) MPNB represents the HighCut-Byte bit D7 and the Fieldstrength-Byte D 7 for the noise rectifier multipath adjustment
20/43
TDA7411
Figure 15. Trigger Threshold vs. VPEAK
VTH
260mV(00)
220mV(01)
180mV(10)
140mV(11)
MIN. TRIG. THRESHOLD
NOISE CONTROLLED
TRIG. THRESHOLD
65mV
8 STEPS
30mV
0.9V
D97AU648
VPEAK(V)
1.5V
Figure 16. Deviation Controlled Trigger Adjustment
VPEAK
(VOP)
00
2.8
01
2.0
10
1.2
0.9
DETECTOR OFF (11)
20
D97AU649
32.5
45
DEVIATION(KHz)
75
Figure 17. Field strength Controlled Trigger Adjustment
VPEAK
MONO
STEREO
»3V
2.4V(00)
1.9V(01)
1.4V(10)
NOISE
noisy signal
0.9V
ATC_SB OFF (11)
D97AU650
good signal
E'
21/43
TDA7411
MULTIPATH DETECTOR
Features:
– internal 19kHz band-pass filter
– programmable band-pass and rectifier gain
– two pin solution fully independent usable for external programming
– selectable internal influence on Stereoblend
ELECTRICAL CHARACTERISTICS (continued)
Symbol
fCMP
GBPMP
Parameter
Test Condition
Min.
Typ.
Max.
Unit
Center frequency of MultipathBandpass
stereo decoder locked on Pilot
tone
19
kHz
Band pass Gain
bits D2, D1 configuration byte = 00
6
dB
bits D2, D1 configuration byte = 01
12
dB
bits D2, D1 configuration byte = 10
16
dB
bits D2, D1 configuration byte = 11
18
dB
bits D7, D6 configuration byte = 00
7.6
dB
bits D7, D6 configuration byte = 01
4.6
dB
bits D7, D6 configuration byte = 10
0
dB
bits D7, D6 configuration byte = 11
off
bit D5, configuration byte = 0
bit D5, configuration byte = 1
0.2
0.4
GRECTMP Rectifier Gain
ICHMP
Rectifier Charge Current
IDISMP
Rectifier Discharge Current
0.5
1
µA
1.5
mA
Max.
Unit
QUALITY DETECTOR
ELECTRICAL CHARACTERISTICS (continued)
Symbol
Parameter
Test Conditions
Min.
Typ.
A
Multipath Influence
Factor
Addr12 / Bit 5+6
00
01
10
11
0.2
0.3
0.4
0.5
dB
dB
dB
dB
A
Noise Influence Factor
Addr16 / Bit 1+2
00
01
10
11
15
12
9
6
dB
dB
dB
dB
22/43
TDA7411
FUNCTIONAL DESCRIPTION OF STERO DECODER
Figure 18. Block diagram of the stereo decoder
The stereo decoder-part of the TDA7411 (see Fig. 18) contains all functions necessary to demodulate the
MPX-signal like pilot tone-dependent MONO/STEREO-switching as well as "stereoblend" and "highcut".
Adaptations like programmable input gain, roll-off compensation, selectable deemphasis time constant
and a programmable field strength input allow using different IF-devices.
InGain + Infilter
The InGain stage allows adjusting the MPX-signal to a magnitude of about 1Vrms internally, which is the
recommended value. The 4.th order input filter has a corner frequency of 80kHz and is used to attenuate
spikes and noise and acts as an anti-aliasing filter for the following switch capacitor filters.
Demodulator
In the demodulator block the left and the right channel are separated from the MPX-signal. In this stage
also the 19-kHz pilot tone is canceled. For reaching a high channel separation the TDA7411 offers an I2Cbus programmable roll-off adjustment, which is able to compensate the low pass behavior of the tuner section. If the tuner's attenuation at 38kHz is in a range from 13.8% to 24.6% the A673 needs no external
network in front of the MPX-pin. Within this range an adjustment to obtain at least 40dB channel separation
is possible. The bits for this adjustment are located together with the field strength adjustment in one byte.
This gives the possibility to perform an optimization step during the production of the car radio where the
channel separation and the field strength control are trimmed. The setup of the stereoblend characteristics, which is programmable in a wide range.
Deemphasis and Highcut
The deemphasis low pass allows to choose between a time constant of 50µs and 75µs (bit D7, stereo decoder byte). The highcut control range will be in both cases τHC = 2x τDeemp. Inside the highcut control
range (between VHCH and VHCL) the LEVEL signal is converted into a 5-bit word, which controls the low
pass time constant between τDeemp...3x τDeemp. Thereby the resolution will remain always 5 bits indepen-
23/43
TDA7411
dently of the absolute voltage range between the VHCH- and VHCL-values.
The highcut function can be switched off by I2C-bus (bit D7, Field strength byte set to "0").
The setup of the highcut characteristics is described in 2.9.
PLL and Pilot tone-Detector
The PLL has the task to lock on the 19kHz pilot tone during a stereo-transmission to allow a correct demodulation. The included pilot tone-detector enables the demodulation if the pilot tone reaches the selected pilot tone threshold VPTHST. Two different thresholds are available. By reading the status byte of the
A673 via I2C-bus the detector output (signal STEREO, see block diagram) can be checked.
Field Strength Control
The field strength input is used to control the highcut- and the stereoblend-function. In addition the signal
can be also used to control the noise blanker thresholds and as input for the multipath detector.
LEVEL-Input and -Gain
To suppress undesired high frequency modulation on the highcut- and stereoblend-function the LEVEL
signal is low pass filtered firstly. The filter is a combination of a 1.st-order RC-low pass at 53kHz (working
as anti-aliasing filter) and a 1.st-order switched capacitor low pass at 2.2kHz. The second stage is a programmable gain stage to adapt the LEVEL signal internally to different IF-devices (see test mode section
5: LEVELINTERN). The gain is widely programmable in 16 steps from 0dB to 10dB (step=0.67dB). These
4 bits are located together with the Roll-Off bits in the "Stereo decoder-Adjustment"-byte to simplify a possible adaptation during the production of the car radio.
Stereoblend Control
The stereoblend control block converts the internal LEVEL-voltage (LEVELINTERN) into a demodulator
compatible analog signal, which is used to control the channel separation between 0dB and the maximum
separation. Internally this control range has a fixed upper limit, which is the internal reference voltage
REF5V. The lower limit can be programmed between 29.2 and 58% of REF5V in 4.167% steps (see
figs.19, 20).
To adjust the external LEVEL-voltage to the internal range two values must be defined: the LEVEL gain
LG and VSBL (see fig. 20). To adjust the voltage where the full channel separation is reached (VST) the
LEVEL gain LG has to be defined. The following equation can be used to estimate the gain:
R EF5 V
L G = -------------------------------------------------------------------------------------Field strenght voltage [STEREO]
Figure 19. Internal stereo blend characteristics
24/43
TDA7411
The gain can be programmed through 4 bits in the "Stereo Decoder Adjustment"-byte. The MONO-voltage
VMO (0dB channel separation) can be chosen selecting VSBL.
All necessary internal reference voltages like REF5V are derived from a bandgap circuit. Therefore they
have a temperature coefficient near zero. This is useful if the fieldstrength signal is also temperature compensated. But most of the IF-devices are applying a LEVEL-voltage with a TC of 3300ppm. The A673 offers this TC for the reference voltages, too. The TC is selectable with bit D7 of the "stereo decoder
adjustment"-byte.
Figure 20. Relation Between Internal and External LEVEL Voltages and Setup of Stereoblend
INTERNAL
VOLTAGES
INTERNAL
VOLTAGES
SETUP OF VST
SETUP OF VMO
LEVEL INTERN
REF 5V
LEVEL INTERN
REF 5V
58%
LEVEL
VSBL
VSBL
VMO
VST
29%
t
FIELDSTRENGHT VOLTAGE
modAU639
VMO
VST
t
FIELDSTRENGHT VOLTAGE
Highcut Control
The highcut control set-up is similar to the stereoblend control set-up: the starting point VHCH can be set
with 2 bits to be 42, 50, 58 or 66% of REF5V whereas the range can be set to be 17, 22, 28 or 33% of
VHCH (see fig. 21).
Figure 21. High cut characteristics
LOWPASS
TIME CONSTANT
3•τDeemp
τDeemp
VHCL
VHCH
FIELDSTRENGHT
D97AU640
Functional Description of the Noise Blanker
In the automotive environment spikes produced by the ignition and for example the wiper-motor disturb
the MPX-signal. The aim of the noise blanker part is to cancel the audible influence of the spikes. Therefore the output of the stereo decoder is held at the actual voltage for a time between 22 and 38µs (programmable). The block diagram of the noise blanker is given in fig.22
25/43
TDA7411
Figure 22. Block diagram of the noise blanker
MPX
RECTIFIER
RECT
+
-
+
MPOUT
HOLDN
VTH
PEAK
LOWPASS
MONOFLOP
THRESHOLD
GENERATOR
+
CONTROL
ADDITIONAL
THRESHOLD
CONTROL
modAU856
In a first stage the spikes must be detected but to avoid a wrong triggering on high frequency (white) noise
a complex trigger control is implemented. Behind the trigger stage a pulse former generates the "blanking"-pulse. An own biasing circuit supplies the noise blanker in order to avoid any cross talk to the signal
path.
Trigger Path
The incoming MPX signal is high pass filtered, amplified and rectified. This second order high pass filter
has a corner-frequency of 140kHz. The rectified signal, RECT, is low pass filtered to generate a signal
called PEAK. Also noise with a frequency 140kHz increases the PEAK voltage. The resulting voltage can
be adjusted by use of the noise rectifier discharge current. The PEAK voltage is fed to a threshold generator, which adds to the PEAK-voltage a DC-dependent threshold VTH. Both signals, RECT and
PEAK+VTH are fed to a comparator, which triggers a re-triggerable monoflop. The monoflop's output activates the sample-and-hold circuits in the signal path for the selected duration.
Automatic Noise Controlled Threshold Adjustment (ATC)
There are mainly two independent possibilities for programming the trigger threshold:
1. the low threshold in 8 steps (bits D 0 to D2 of the noise blanker byte)
2. and the noise adjusted threshold in 4 steps (bits D3 and D4 of the noise blanker-byte, see fig. 15).
The low threshold is active in combination with a good MPX signal without any noise; the PEAK voltage
is less than 1V. The sensitivity in this operation is high.
If the MPX signal is noisy (low fieldstrength) the PEAK voltage increases due to the higher noise, which is
also rectified. With increasing of the PEAK voltage the trigger threshold increases, too. This particular gain
is programmable in 4 steps (see fig. 17).
26/43
TDA7411
ADDITIONAL THRESHOLD CONTROL MECHANISM
Automatic Threshold Control by the Stereoblend voltage
Besides the noise controlled threshold adjustment there is an additional possibility for influencing the trigger threshold. It is depending on the stereoblend control.
The point where the MPX signal starts to become noisy is fixed by the RF part. Therefore also the starting
point of the normal noise-controlled trigger adjustment is fixed (fig. 17). In some cases the behavior of the
noise blanker can be improved by increasing the threshold even in a region of higher fieldstrength. Sometimes a wrong triggering occurs for the MPX signal often shows distortion in this range, which can be
avoided even if using a low threshold. Because of the overlap of this range and the range of the stereo/
mono transition it can be controlled by stereoblend. This threshold increase is programmable in 3 steps
or switched off with bits D0 and D1 of the fieldstrength control-byte.
Over Deviation Detector
If the system is tuned to stations with a high deviation the noise blanker can trigger on the higher frequencies of the modulation. To avoid this wrong behavior, which causes noise in the output signal, the noise
blanker offers a deviation-dependent threshold adjustment. By rectifying the MPX signal a further signal
representing the actual deviation is obtained. It is used to increase the PEAK voltage. Offset and gain of
this circuit are programmable in 3 steps with the bits D6 and D7 of the stereo decoder-byte (the first step
turns off the detector, see fig. 16).
Multipath-Level
To react on high repetitive spikes caused by a Multipath-situation, the discharge-time of the PEAK voltage
can be decreased depending on the voltage-level at Pin MPout. There are two ways to do this. One way
is to switch on the linear influence of the Multipath-Level on the PEAK-signal (D7 of field strength control
byte). In this case the discharge slew rate is 1V/ms1. The second possibility is to activate a function, which
switches to the 18k discharge if the Multipath-Level is below 2.5V (D7 of High-Cut-Control-Byte).
1
The slew rate is measured with RDischarge = infinite and VMPout = 2.5V
Functional Description of the Multipath-Detector
Using the internal Multipath-Detector the audible effects of a multipath condition can be minimized. A multipath-condition is detected by rectifying the 19kHz spectrum in the fieldstrength signal. An external capacitor is used to define the attack- and decay-times (see block diagram, fig. 23). The MP_OUT-pin is
used as detector-output connected to a capacitor of about 47nF and additionally the MP_IN-pin is selected
to be the fieldstrength input. Using this configuration an external adaptation to the user's requirement is
possible without affecting the "normal" fieldstrength input (LEVEL) for the stereo decoder. This application
is given in fig. 29.
To keep the old value of the Multipath Detector during an AF-jump, the MP-Hold switch can disconnect
the external capacitor. This switch is controlled directly by the AFS-Pin.
Selecting the "internal influence" in the configuration byte the channel separation is automatically reduced
during a multipath condition according to the voltage appearing at the MP_OUT-pin. A possible application
is shown in fig. 29.
27/43
TDA7411
Figure 23. Block Diagram of Multi path Detector
Programming
To obtain a good multipath performance an adaptation is necessary. Therefore the gain of the 19kHzbandpass is programmable in four steps as well as the rectifier gain. The attack- and decay-times can be
set by the external capacitor value.
Quality Detector
The A673 offers a quality detector output, which gives a voltage representing the FM-reception conditions.
To calculate this voltage the MPX-noise and the multipath-detector output are summed according to the
following formula:
VQual = 1.6 (VNoise-0.8 V)+ a (REF5V-VMpout).
The noise-signal is the PEAK-signal without additional influences (see noise blanker description). The factor 'a' can by programmed from 0.6 to 1.05. The output is a low impedance output able to drive external
circuitry as well as simply fed to an AD-converter for RDS applications.
AF Search Control
The TDA7411 is supplied with several functionality to support AF-checks using the stereo decoder. As
mentioned already before the high impedance mute feature avoids any clicks during the jump condition.
It is possible at the same time to evaluate the noise- and multipath-content of the alternate frequency by
using the Quality detector output. Therefore the multipath-detector is switched automatically to a small
time-constant.
One additional pin (AFS) is implemented in order to separate the audio processor-mute and stereo decoder AF-functions. In Figure 24 the block diagram and control-functions of the complete AFS-functionality is
shown (please not the pins FAS and SM are active low as well as all control-bits indicated by an over bar).
28/43
TDA7411
Figure 24. Mute Control Logic
Test Mode
During the test mode which can be activated by setting bit D0 of the testing-byte and bit D5 of the sub
address byte to "1" several internal signals are available at the CDR pin. During this mode the input resistance of 100kOhm is disconnected from the pin. The internal signals available are shown in the data
byte specification.
29/43
TDA7411
I2C BUS INTERFACE DESCRIPTION
Interface Protocol
The interface protocol comprises:
-a start condition (S)
-a chip address byte (the LSB bit determines read / write transmission)
-a subaddress byte
-a sequence of data (N-bytes + acknowledge)
-a stop condition (P)
SUBADDRESS
CHIP ADDRESS
MSB
S
1
LSB
0
0
0
1
1
MSB
0 R/W ACK
DATA 1 to DATA n
LSB
A4 AZ T
I
A3 A2 A1 A0
MSB
LSB
DATA
ACK
ACK
P
D03AU1526
S = Start
ACK = Acknowledge
AZ = AutoZero-Remain
T = Testing
I = Autoincrement
P = Stop
MAX CLOCK SPEED 500kbits/s
Auto increment
If bit I in the subaddress byte is set to "1", the autoincrement of the subaddress is enabled.
TRANSMITTED DATA (send mode)
MSB
X
LSB
X
X
X
ST
SM
X
X
SM = Soft mute activated
ST = Stereo
X = Not Used
The transmitted data is automatically updated after each ACK.
Transmission can be repeated without new chip address.
Reset Condition
A power on reset is invoked if the supply voltage is below than 3.5V. After that the following data are written
automatically into the registers of all sub addresses:
MSB
1
LSB
1
1
1
1
1
1
0
The programming after POR is marked bold face / underlined in the programming tables. With that programming all the outputs are muted to Vref.
30/43
TDA7411
SUBADDRESS (receive mode)
MSB
LSB
FUNCTION
I3
I2
I1
I0
A3
A2
A1
A0
Auto Zero Remain 2
off
on
0
1
Test Mode 3
off
on
0
1
Auto Increment Mode 4
off
on
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
Byte
(dec)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Input Selector (main)
Volume
Treble
Bass
Speaker Attenuator Left Front
Speaker Attenuator Right Front
Speaker Attenuator Left Rear
Speaker Attenuator Right Rear
Soft Mute / Bass Programming
Stereo Decoder
Noise Blanker
High Cut Control
Field Strength. & Quality
Configuration
EEPROM
Testing
New Quality / Control
Middle Filter
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
New implemented sub addresses
1
1
1
1
1
1
1
0
0
0
0
0
0
1
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
Input Selector (sub)
Speaker Attenuator Left Free
Speaker Attenuator Right Free
Configuration Front
Configuration Rear
Configuration Free
Mute
18
19
20
21
22
23
24
31/43
TDA7411
DATA BYTE SPECIFICATION
The status after Power-On-Reset is marked bold face / underlined in the programming tables.
Input Selector (0)
MSB
D7
LSB
D6
0
0
:
1
1
D5
0
0
:
1
1
D4
0
0
:
1
1
D3
D2
D1
D0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
FUNCTION
Source Selector
CDCH
AUX
CD
MD/phone
NV
Acin0
AM
FM
In-Gain
15dB
14dB
:
1 dB
0 dB
0
1
:
0
1
CDCH Input Configuration
quasi differential
full differential
0
1
Volume and Speaker Attenuation (1, 4, 5, 6, 7, 19, 20)
MSB
LSB
FUNCTION
D7
D6
D5
D4
D3
D2
D1
D0
1
:
1
0
0
0
:
0
0
:
0
0
0
:
0
0
0
0
:
0
0
:
1
1
0
:
0
0
0
0
:
0
0
:
0
0
0
:
0
0
0
0
:
0
1
:
0
0
1
:
0
0
0
0
:
1
0
:
1
1
1
:
0
0
0
0
:
1
0
:
1
1
1
:
0
0
0
0
:
1
0
:
1
1
1
:
1
0
0
1
:
1
0
:
0
1
+15dB
:
+1dB
0dB
0dB
-1dB
:
-15dB
-16dB
:
-78dB
-79dB
X
1
1
X
X
X
X
X
Mute
32/43
TDA7411
Treble Filter (2)
MSB
D7
LSB
D6
D5
D4
D3
D2
D1
D0
0
0
:
1
1
0
0
:
1
1
0
0
:
1
1
0
1
:
0
1
Treble Steps
15dB
14dB
:
1 dB
0 dB
Boost / Cut
Cut
Boost
0
1
0
0
1
1
FUNCTION
Treble Center-frequency
10.0 kHz
12.5 kHz
15.0 kHz
17.5 kHz
0
1
0
1
unused
must be “1”
1
Bass Filter (3)
MSB
D7
LSB
D6
D5
D4
0
1
0
0
1
1
0
1
0
1
0
1
D3
D2
D1
D0
0
0
:
1
1
0
0
:
1
1
0
0
:
1
1
0
1
:
0
1
FUNCTION
Bass Steps
15dB
14dB
:
1 dB
0 dB
Boost / Cut
Cut
Boost
Bass Quality Factor
1.00
1.25
1.50
2.00
DC Mode
Off
On
33/43
TDA7411
Speaker Attenuators (4-7)
Please refer to Volume Programming.
Soft Mute and Bass Programming (8)
MSB
D7
LSB
D6
D5
D4
D3
D2
D1
0
0
0
1
1
0
0
1
1
Not used
Must be “0”
Mute Time
Mute Time = 0.24ms
Mute Time = 0.48ms
Mute Time = 10.1ms
Mute Time = 20.2ms
0
1
0
1
Not used
Must be “1”
1
0
0
1
1
1
FUNCTION
D0
Bass Center-Frequency
60 Hz
70 Hz
80 Hz
100 Hz
150 Hz (if Q =2)
0
1
0
1
1
Noise Blanker Time
38µs
25.5µs
32µs
22µs
0
1
0
1
Stereo Decoder (9)
MSB
D7
LSB
D6
D5
D4
D3
D2
D1
0
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
34/43
0
1
0
1
FUNCTION
D0
STD Unmuted
STD Muted
IN-Gain
IN-Gain
IN-Gain
IN-Gain
11 dB
8.5 dB
6 dB
3.5 dB
Stereo Decoder
Off
On
Forced MONO
MONO/STEREO switch automatically
Noise Blanker PEAK charge current low
Noise Blanker PEAK charge current high
Pilot Threshold HIGH
Pilot Threshold LOW
Deemphasis 50µs
Deemphasis 75µs
TDA7411
Noise Blanker (10)
MSB
D7
LSB
D6
D5
D4
0
0
1
1
D3
D2
D1
D0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
Low Threshold 65mV
Low Threshold 60mV
Low Threshold 55mV
Low Threshold 50mV
Low Threshold 45mV
Low Threshold 40mV
Low Threshold 35mV
Low Threshold 30mV
Noise Controlled Threshold 320mV
Noise Controlled Threshold 260mV
Noise Controlled Threshold 200mV
Noise Controlled Threshold 140mV
0
1
0
0
1
1
FUNCTION
Noise Blanker OFF
Noise Blanker ON
0
1
0
1
Over Deviation
Over Deviation
Over Deviation
Over Deviation
Adjust 2.8V
Adjust 2.0V
Adjust 1.2V
Detector OFF
High-Cut (11)
MSB
D7
LSB
D6
D5
D4
D3
D2
D1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
FUNCTION
D0
High-Cut OFF
High-Cut ON
max. High-Cut
max. High-Cut
max. High-Cut
max. High-Cut
2dB
5dB
7dB
10dB
VHCH at
VHCH at
VHCH at
VHCH at
42%
50%
58%
66%
REF5V
REF5V
REF5V
REF5V
VHCL at
VHCL at
VHCL at
VHCL at
16.7% VHCH
22.2% VHCH
27.8% VHCH
33.3% VHCH
Strong Multipath Influence on PEAK 18k
Off
On (18k discharge if VMPout< 2.5V)
35/43
TDA7411
Field Strength Control (12)
MSB
D7
LSB
D6
D5
D4
0
0
1
1
0
0
1
1
D3
D2
D1
D0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
FUNCTION
VSBL at
VSBL at
VSBL at
VSBL at
VSBL at
VSBL at
VSBL at
VSBL at
29%
33%
38%
42%
46%
50%
54%
58%
REF5V
REF5V
REF5V
REF5V
REF5V
REF5V
REF5V
REF5V
Noise Blanker Field Strength
Noise Blanker Field Strength
Noise Blanker Field Strength
Noise Blanker Field Strength
0
1
0
1
Quality
Quality
Quality
Quality
Adjust 2.3V
Adjust 1.8V
Adjust 1.3V
Adjust OFF
Detector Coefficient a=0.6
Detector Coefficient a=0.75
Detector Coefficient a=0.9
Detector Coefficient a=1.05
Multipath Influence on PEAK Discharge
Off
-1 V/ms
0
1
Configuration (13)
MSB
D7
LSB
D6
D5
D4
D3
0
1
0
1
0
1
0
1
0
0
1
1
36/43
0
1
0
1
D2
0
0
1
1
D1
D0
0
0
1
1
0
1
0
1
FUNCTION
Noise Rectifier Discharge Resistor
R = infinite
RDC = 56k
RDC = 33k
RDC = 18k
Multipath Detector Band pass Gain
6dB
12dB
16dB
18dB
Multipath Detector internal influence
ON
OFF
Multipath Detector Charge Current
0.2µA
0.4µA
Multipath Detector Rectifier Gain
Gain = 7.6dB
Gain = 4.6dB
Gain = 0dB
Disabled
TDA7411
Stereo Decoder Adjustment (14)
MSB
D7
D6
D5
D4
D3
D2
D1
LSB
D0
0
0
0
:
0
:
0
0
0
0
:
1
:
1
0
0
1
:
0
:
1
0
1
0
:
0
:
1
1
1
1
:
1
:
1
0
0
0
:
1
:
1
0
0
1
:
0
:
1
0
1
0
:
0
:
1
D2
1
D1
1
LSB
D0
0
0
0
0
:
1
0
0
0
:
1
0
0
1
:
1
0
1
0
:
1
D5
1
D4
1
D3
1
FUNCTION
Roll-Off Compensation
Not allowed
7.2%
9.4%
:
13.7%
:
20.2%
Not allowed
19.6%
21.5%
:
25.3%
:
31.0%
LEVEL Gain
0dB
0.66dB
1.33dB
:
10dB
Testing (15)
MSB
D7
1
D6
1
0
1
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
FUNCTION
default value, see note
Stereo Decoder Test Signals
OFF
Test Signals enabled if bit D5 of the sub
address (test mode-bit) is set to "1", too
External Clock
Internal Clock
Test Signals at CDR
VHCCH
Level intern
Pilot magnitude
VCOCON; VCO Control Voltage
Pilot threshold
HOLDN
NB threshold
F228
VHCCL
VSBL
Not used
Not used
PEAK
Not used
REF5V
Not used
VCO
OFF
ON
Audio Processor Test Mode
Enabled if bit D5 of the sub address (test
mode-bit) is set to "1", too
OFF
Note: This byte is used for testing or evaluation purposes only and must not set to other values than the default "11111110" in the application!
37/43
TDA7411
New Quality / Control (16)
MSB
D7
LSB
D6
D5
D4
D3
D2
D1
0
1
0
0
1
1
FUNCTION
D0
Reference Generation
Internal Reference-Divider
External Reference Force
Quality Noise-Gain
15 dB
12 dB
9 dB
6 dB
0
1
0
1
SC-Clock-Mode
Fast Mode
Normal Mode
0
1
AutoZero
Off
On
0
1
Smoothing Filter
On
Off
0
1
Enable AF-Pin
Enable Pin
Disable Pin
0
1
AF-Pin ST-Decoder-Mute-Influence
On
Off
0
1
Middle Filter (17)
MSB
D7
LSB
D6
0
0
1
1
0
1
38/43
D5
0
1
0
1
D4
D3
D2
D1
D0
0
0
:
0
0
1
1
:
1
1
0
0
:
1
1
1
1
:
0
0
0
0
:
1
1
1
1
:
0
0
0
0
:
1
1
1
1
:
0
0
0
1
:
0
1
1
0
:
1
0
FUNCTION
Attenuation
-15dB
-14dB
:
-1 dB
0 dB
0 dB
+1 dB
:
+14 dB
+15dB
Middle Center-frequency
500 Hz
1.0 kHz
1.5 kHz
2.0 kHz
Mid Q Factor
1.0
2.0
TDA7411
Input Selector Sub (18)
MSB
D7
LSB
D6
1
D5
1
D4
1
D3
D2
D1
D0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
FUNCTION
Source Selector
CDCH
AUX
CD
MD/phone
NV
Acin0
AM
FM
Unused
Must be “1”
1
MD Input Mode
Phone
MD
0
1
Configuration Front Speaker (21)
MSB
D7
LSB
D6
D5
D4
D3
0
1
0
1
0
1
0
1
1
D2
D1
D0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
FUNCTION
Source Selector
Middle filter output
Bass filter output
NV
Phone
ACin0
ACin1
ACin2
ACin3
Interrupt Left
Interrupt
No interrupt
Interrupt Right
Interrupt
No interrupt
Interrupt Source Left
Phone
NV
Interrupt Source Right
Phone
NV
Not used
Must be “1”
39/43
TDA7411
Configuration Rear Speaker (22)
MSB
LSB
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
1
1
1
1
FUNCTION
Source Selector
Middle filter output
Bass filter output
NV
Phone
ACin0
ACin1
ACin2
ACin3
ACin1 Input Resistor
Not allowed (50k)
50k
40k
30k
0
1
0
1
Unused
Must be “1”
1
Configuration Rear Speaker (23)
MSB
D7
LSB
D6
D5
D4
1
0
0
0
0
1
1
1
1
40/43
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
D3
1
D2
D1
D0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
FUNCTION
Source Selector
Middle filter output
Bass filter output
NV
Phone
ACin1
ACin2
ACin3
ACin3_lowpass
Unused
Must be “1”
Low Pass Corner Frequency
flat
50 Hz
60 Hz
80 Hz
100 Hz
120 Hz
not allowed (120 Hz)
not allowed (120 Hz)
TDA7411
Mute Configuration (24)
MSB
D7
LSB
D6
D5
D4
D3
D2
D1
FUNCTION
D0
0
1
0
1
Front Left Speaker
Muted
Unmuted
Front Right Speaker
Muted
Unmuted
Rear Speaker
Muted
Unmuted
0
1
Smoothing Bass
off
on
0
1
Free Speaker
Muted
Unmuted
0
1
Smoothing Low Pass
off
on
0
1
Main Channel
Muted
Unmuted
0
1
Sub Channel
Muted
Unmuted
0
1
APPLICATION CIRCUIT
Figure 25. Standard Application
TDA7411
41/43
TDA7411
mm
inch
DIM.
MIN.
TYP.
A
MAX.
MIN.
TYP.
1.60
A1
0.05
A2
1.35
B
0.30
C
0.09
D
11.80
D1
9.80
D3
0.063
0.15
0.002
1.40
1.45
0.053
0.055
0.057
0.37
0.45
0.012
0.015
0.018
0.20
0.004
12.00
12.20
0.464
0.472
0.480
10.00
10.20
0.386
0.394
0.401
8.00
0.006
0.008
0.315
E
11.80
12.00
12.20
0.464
0.472
0.480
E1
9.80
10.00
10.20
0.386
0.394
0.401
E3
8.00
0.315
e
0.80
0.031
L
0.45
0.60
L1
0.75
0.018
1.00
k
OUTLINE AND
MECHANICAL DATA
MAX.
0.024
0.030
TQFP44 (10 x 10 x 1.4mm)
0.039
0˚(min.), 3.5˚(typ.), 7˚(max.)
D
D1
A
A2
A1
33
23
34
22
0.10mm
.004
B
E
B
E1
Seating Plane
12
44
11
1
C
L
e
K
TQFP4410
0076922 D
42/43
TDA7411
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
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43/43