TDA7535 DELTA/SIGMA CASCADE 20 BIT STEREO DAC ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 20-bit resolution single ended output Analog reconstruction third order Chebyshev filter I2S input data format On chip PLL System clock: 64 Fs 2 output channels 0.9 VRMS single ended output dynamic 3.3V power supply Reset Sampling rate 36KHz to 48KHz DESCRIPTION The TDA7535 is a stereo, digital-to-analog converter designed for audio application, including digital interpolation filter, a third order multibit Delta-Sigma DAC, a third order Chebyshev's reconstruction filter and a differential to single ended output converter. This device is fabricated in highly advanced CMOS, where high speed precision analog circuits are combined with high density logic circuits. The TDA7535, according to standard audio converters, can accept any I2S data format. TSSOP-14 SO-14 ORDERING NUMBER: TDA7535 The TDA7535 is available in SO-14 and TSSOP-14 packages. The total power consumption is less than 75mW. TDA7535 is suitable for a wide variety of applications where high performance are required. Its low cost and single 3.3V power supply make it ideal for several applications, such as CD players, MPEG audio, MIDI applications, CD-ROM drives, CD-Interactive, digital radio applications and so on. An evaluation board is available to perform measurement and to make listening tests. BLOCK DIAGRAM I2S I2S DIGITAL INPUT 20 FIR1 FIR2 FS PLL CLKOUT ALU FIR3 20 S&H 8FS 23 Σ∆ MODULATOR 64FS 4 THERMO DECODER & RANDOMIZER 3rd CHEBYSHEV SC FILTER DIFF TO SINGLE CONVERTER ANALOG OUTPUT D02AU1417 July 2003 1/9 TDA7535 ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit -0.5 to +4.6 -0.5 to +4.6 V V VDD VCC Power supplies Vaio Analog Input and Output Voltage -0.5 to (VCC+0.5) V Vdio Digital Input and Output Voltage -0.5 to (VDD+0.5) V Vdi5 Digital Input Voltage (5V tolerant) -0.5 to 6.5 V Operating Junction Temperature Range -40 to 125 °C Storage Temperature -55 to 150 °C Tj Tstg Digital Analog Warning: Operation at or beyond these limit may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. THERMAL DATA Symbol Rth j-amb Parameter Thermal resistance junction to ambient (1) Value Unit 85 °C/W Note: 1. In still air PIN CONNECTIONS (Top views) N.C. 1 14 RESETN SDATA 2 13 FSYNC SCK 3 12 VDD_DIG N.C. 4 11 N.C. GND_DIG 5 10 VDD_ANA GND_ANA 6 9 VCM OUTSR 7 8 OUTSL D01AU1276A PIN FUNCTION (SO14/TSSOP14) Pin Number 2/9 Pin Name Input/Output Power Description 1 N.C. - - 2 SDATA I I2S Digital Data Input 3 SCK I I2S Clock Input 4 N.C. - - 5 GND_DIG P Digital Ground 6 GND_ANA P Analog Ground 7 OUTSR O Right Channel single ended Output 8 OUTSL O Left Channel single ended Output 9 VCM P Reference 1.65V externally filtered 10 VDD_ANA P Analog 3.3V-Supply 11 N.C. - - 12 VDD_DIG P Digital 3.3V-Supply 13 FSYNC I I2S Left-Right Channel selector 14 RESETN I Reset (active low) TDA7535 RECOMMENDED DC OPERATING CONDITIONS Symbol Parameter Test Condition Min. Typ. Max. Unit VDD 3.3V Digital Power Supply Voltage 3.15 3.3 3.45 V VCC 3.3V Analog Power Supply Voltage 3.15 3.3 3.45 V Min. Typ. Max. Unit 21.5 25 mA Typ. Max. Unit POWER CONSUMPTION Symbol Idd Parameter Test Condition Total Maximum Current power supply @ 3.3V and Tj = 125°C GENERAL INTERFACE ELECTRICAL CHARACTERISTICS Symbol Parameter Test Condition Min. lil Low Level Input Current without pullup device Vi = 0V (note 1) 1 µA lih High Level Input Current without pullup device Vi = Vdd (note 1) 1 µA I/O latch-up current V < 0V, V > Vdd 200 mA Electrostatic Protection Leakage , 1µA (note 2) 2000 V Ilatchup Vesd Note: 1. The leakage currents are generally very small, <1nA. The value given here, 1mA, is the maximum that can occur after an Electrostatic Stress on the pin. 2. Human Body Model. LOW VOLTAGE CMOS INTERFACE DC ELECTRICAL CHARACTERISTICS Symbol Parameter Test Condition Min. Typ. Max. Unit 0.2*Vdd V Vil Low Level Input Voltage Vih High Level Input Voltage 0.8*Vdd V Vhyst Schmitt trigger hysteresis 0.8 V DAC ELECTRICAL CHARACTERISTICS Vdd = 3.3V; Tamb = 25°C; Input signal frequency = sinus wave generated by Audio Precision Sys.2; Input Signal Amplitude = see notes; Noise Integration Bandwidth = 20Hz to 22KHz (A- weighted) Parameter Test Condition Min. Typ. Max. Unit Noise + Distortion (see note 1) @0dB @-6dBb @-40dB @-60dB 89 94 96 96 dB dB dB dB Total Harmonic Distortion see note 2 94 dB Dynamic range see note 3 96 dB Crosstalk see note 4 -95 dB Full Scale Output Voltage Vdd = 3.15 to 3.45V Full scale input Input Sampling Rate 0.8 36 0.9 1.0 Vrms 48 kHz 3/9 TDA7535 DAC ELECTRICAL CHARACTERISTICS (continued) Vdd = 3.3V; Tamb = 25°C; Input signal frequency = sinus wave generated by Audio Precision Sys.2; Input Signal Amplitude = see notes; Noise Integration Bandwidth = 20Hz to 22KHz (A- weighted) Parameter Test Condition Min. Typ. Passband Ripple 0.12 Stopband @ 3dB @ 90dB 44.1kHz Sampling Rate Note 2: Note 3: Note 4: kHz 24.80 0.05 0.1 dB It is the ratio between the maximum input signal and the integration of the in-band noise after deducing the power of signal fundamental. It depends on the input signal amplitude. In this case 0dB means full scale digital, 1kHz frequency used. It is the ratio of the rms value of the signal fundamental component at 0dB (full scale digital) to the rms value of all of the harmonic components in the band. measured using the SNR at -60dB input signal, with 60dB added to compensate for small input signal. Left channel on with 0dB/1kHz input signal, Right channel on with DC input signal. Figure 1. I2S interface Diagram Left Right FSYNC 32 * SCK 32 * SCK SCK 20 Bits 20 Bits SDATA MSB 4/9 Unit dB 21.53 Interchannel Gain Mismatch Note1: Max. LSB MSB LSB TDA7535 Figure 2. I2S Timings SDATA Valid FSYNC Valid tsckf tsckr SCK tlrw- tlrw+ tsds tsdh tsckpl tsckph tsck Timing tsck Description Clock Cycle(1) Minimum Maximum Unit 1/(64*Fs) 150psRMS 1/(64*Fs) + 150psRMS ns tsckpl SCK Phase Low 0.5*tsck - 1% 0.5*tsck +1% ns tsckph SCK Phase High 0.5*tsck - 1% 0.5*tsck +1% ns tlrw- FSYNC switching time window before SCK falling edge(2) 0 0.125*tsck-10 ns tlrw+ FSYNC switching time window after SCK falling edge(2) 0 0.125*tsck-10 ns tsds SDATA setup time 60 ns tsdh SDATA hold time 30 ns tsckr SCK rise time 1.5 ns tsckf SCK fall time 1.5 ns (1) SCK clock defines the Fs, being the Sample Rate. This input clock needs a jitter below ~212psRMS (2) FSYNC switches inside the time window as specified w.r.t. to falling edge of SCK Figure 3. Power Up & Reset Sequence VDD RESET TRES TRES Min 50ms D02AU1418 I2S bit clock (SCK) must be present 20ms before reset release to allow PLL locking. 5/9 TDA7535 Figure 4. Frequency response Figure 5. µP R2 10K +3.3 VDIG C7 10µF 10V U4 TP1 SDATA 2 +3.3VANA SW1 10µF RESETN 14 10 TP2 SCK 2 I S 3 TP3 FSYNC 12 100nF(*) VDD_ANA 10µH bead inductor VDD_DIG 100nF(*) 10µF 13 TP5 GND_DIG GND_ANA VCM C16 100nF (*) C15 47µF 10V (*) 5 8 OUTSL OUTSL TP6 6 TP7 9 7 OUTSR D02AU1419B J4 BNC OUTSR TP8 (*) AS CLOSE AS POSSIBLE TO THE PIN 6/9 J3 BNC TDA7535 mm DIM. MIN.. TYP. A a1 inch MAX.. MIN.. TYP.. MAX.. 1.75 0.1 0.25 a2 0.069 0.004 0.009 1.6 0.063 b 0.35 0.46 0.014 0.018 b1 0.19 0.25 0.007 0.010 C 0.5 c1 0.020 45˚ (typ.) D (1) 8.55 8.75 0.336 0.344 E 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 7.62 0.300 F (1) 3.8 4 0.150 0.157 G 4.6 5.3 0.181 0.209 L 0.4 1.27 0.016 0.050 M S OUTLINE AND MECHANICAL DATA 0.68 0.027 SO14 8˚ (max.) (1) D and F do not include mold flash or protrusions. Mold flash or potrusions shall not exceed 0.15mm (.006inch). 7/9 TDA7535 mm inch DIM. MIN. TYP. A MAX. MIN. TYP. 1.200 A1 0.050 A2 0.800 b MAX. 0.047 0.150 0.002 1.050 0.031 0.190 0.300 0.007 0.012 c 0.090 0.200 0.005 0.009 D (1) 4.900 5.000 5.100 0.114 0.118 0.122 E 6.200 6.400 6.600 0.244 0.252 0.260 E1 (1) 4.300 4.400 4.500 0.170 0.173 0.177 e L L1 k aaa Note: 1.000 0.650 0.450 0.600 OUTLINE AND MECHANICAL DATA 0.006 0.039 0.041 0.026 0.750 0.018 1.000 0.024 0.030 0.039 0˚ (min.) 8˚ (max.) 0.100 0.004 1. D and E1 does not include mold flash or protrusions. Mold flash or potrusions shall not exceed 0.15mm (.006inch) per side. TSSOP-14 (Body 4.4mm) 0080337 (Jedec MO-153-AA) 8/9 TDA7535 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 2003 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com 9/9