MAXIM MAX1161ACPI

19-1190; Rev 0; 3/97
KIT
ATION
EVALU
E
L
B
AVAILA
10-Bit, 40Msps, TTL-Output ADC
Inputs and outputs are TTL compatible. An overrange
output is provided to indicate overflow conditions.
Output data format is straight binary. Power dissipation
is low at only 1W with +5V and -5.2V power-supply voltages. The MAX1161 also accepts wide, ±2V input voltages.
The MAX1161 is available in 28-pin DIP and SO packages in the commercial temperature range.
________________________Applications
Medical Imaging
Professional Video
Monolithic 40Msps Converter
On-Chip Track/Hold
Bipolar, ±2V Analog Input
57dB SNR at 3.58MHz Input
5pF Input Capacitance
TTL Outputs
______________Ordering Information
PART
Radar Receivers
Instrumentation
Digital Communications
________________Functional Diagram
ANALOG
INPUT
____________________________Features
♦
♦
♦
♦
♦
♦
TEMP. RANGE
PIN-PACKAGE
MAX1161ACPI
0°C to +70°C
28 Wide Plastic DIP
MAX1161BCPI
MAX1161ACWI
MAX1161BCWI
0°C to +70°C
0°C to +70°C
0°C to +70°C
28 Wide Plastic DIP
28 SO
28 SO
__________________Pin Configuration
TOP VIEW
4
TOP VIEW
COARSE
ADC
28 DVCC
DGND
1
D0
2
27 VEE
D1
3
26 AGND
D2
4
25
VCC
D3
5
24
VFB
D4
6
23
VSB
D5
7
22 VRM
D6
8
21 VIN
D7
9
20 VST
SUCCESSIVE INTERPOLATION
STAGE i + 1
D8
10
19
VFT
D9
11
18
VCC
...
.
D10
12
17
AGND
DGND
13
16
VEE
DVCC
14
15
CLK
T/H
AMPLIFIER
BANK
SUCCESSIVE INTERPOLATION
STAGE i
SUCCESSIVE INTERPOLATION
STAGE N
DECODING NETWORK
ANALOG
PRESCALER
10
DIGITAL
OUTPUT
MAX1161
DIP/SO
________________________________________________________________ Maxim Integrated Products
For the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800
1
MAX1161
_______________General Description
The MAX1161 10-bit, monolithic analog-to-digital converter (ADC) is capable of 40Msps minimum word
rates. An on-board track/hold ensures excellent dynamic performance without the need for external components. A 5pF input capacitance minimizes drive
requirement problems.
MAX1161
10-Bit, 40Msps, TTL-Output ADC
ABSOLUTE MAXIMUM RATINGS
VCC ........................................................................................+6V
VEE ..........................................................................................-6V
Analog Input.......................................................VFB ≤ VIN ≤ VFT
VFT, VFB ...........................................................................3V, -3V
Reference-Ladder Current..................................................12mA
CLK Input...............................................................................VCC
Digital Outputs.....................................................30mA to -30mA
Continuous Power Dissipation (TA = +70°C)
Plastic DIP ........................................................................1.14W
SO .........................................................................................1W
Operating Temperature Range...............................0°C to +70°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10sec). ............................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = +5.0V, VEE = -5.2V, DVCC = +5.0V, VIN = ±2.0V, VSB = -2.0V, VST = +2.0V, fCLK = 40MHz, 50% clock duty cycle,
TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER
CONDITIONS
TEST
LEVEL
Resolution
MIN
MAX1161A
TYP
MAX
10
MIN
MAX1161B
TYP
MAX
10
UNITS
Bits
DC ACCURACY (±full scale, 250kHz sample rate, TA = +25°C)
Integral Nonlinearity
I
±1.0
±1.5
LSB
Differential Nonlinearity
I
±0.5
±0.75
LSB
Guaranteed
Guaranteed
No Missing Codes
ANALOG INPUT
Input Voltage Range
VI
±2.0
Input Bias Current
VIN = 0V
VI
30
Input Bias Current
TA = -55°C to +125°C
VI
Input Resistance
Input Resistance
TA = -55°C to +125°C
Input Capacitance
±2.0
60
30
75
V
60
µA
75
µA
VI
100
300
100
300
kΩ
VI
75
300
75
300
kΩ
VI
5
5
pF
V
120
120
MHz
Positive Full-Scale Error
V
±2.0
±2.0
LSB
Negative Full-Scale Error
V
±2.0
±2.0
LSB
800
Ω
Input Bandwidth
3dB small signal
REFERENCE INPUT
Reference-Ladder
Resistance
VI
Reference-Ladder
Tempco
V
500
800
500
0.8
0.8
Ω/°C
TIMING CHARACTERISTICS
Maximum Conversion Rate
VI
Overvoltage Recovery Time
V
Pipeline Delay (Latency)
VI
40
40
20
1
Output Delay
TA = +25°C
V
14
Aperture Delay Time
TA = +25°C
V
1
Aperture Jitter Time
TA = +25°C
V
Acquisition Time
TA = +25°C
V
2
MHz
20
18
14
ns
1
Clock
Cycle
18
ns
1
ns
5
5
ps-RMS
12
12
ns
_______________________________________________________________________________________
10-Bit, 40Msps, TTL-Output ADC
MAX1161
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +5.0V, VEE = -5.2V, DVCC = +5.0V, VIN = ±2.0V, VSB = -2.0V, VST = +2.0V, fCLK = 40MHz, 50% clock duty cycle,
TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER
CONDITIONS
TEST
LEVEL
MAX1161A
MIN TYP MAX
MAX1161B
MIN TYP MAX
UNITS
DYNAMIC PERFORMANCE
Effective Number of Bits
(ENOB)
fIN = 1MHz
8.7
8.2
fIN = 3.58MHz
8.7
8.2
fIN = 10.0MHz
7.3
TA = +25°C
fIN = 1MHz
Signal-to-Noise Ratio
(without harmonics)
(SNR)
TA = 0°C to +70°C,
TA = -25°C to +85°C
TA = +25°C
fIN = 3.58MHz
TA = 0°C to +70°C,
TA = -25°C to +85°C
TA = +25°C
fIN = 10.0MHz
TA = 0°C to +70°C,
TA = -25°C to +85°C
TA = +25°C
fIN = 1MHz
Total Harmonic Distortion
(THD)
TA = 0°C to +70°C,
TA = -25°C to +85°C
TA = +25°C
fIN = 3.58MHz
TA = 0°C to +70°C,
TA = -25°C to +85°C
TA = +25°C
fIN = 10.0MHz
TA = 0°C to +70°C,
TA = -25°C to +85°C
TA = +25°C
fIN = 1MHz
Signal-to-Noise and
Distortion Ratio
(SINAD)
TA = 0°C to +70°C,
TA = -25°C to +85°C
TA = +25°C
fIN = 3.58MHz
TA = 0°C to +70°C,
TA = -25°C to +85°C
TA = +25°C
Bits
6.9
I
55
57
52
54
IV
53
55
50
52
I
55
57
52
54
IV
53
55
50
52
I
48
50
46
48
IV
45
47
43
45
I
54
56
52
54
IV
51
53
49
51
I
54
56
52
54
IV
51
53
49
51
I
46
48
43
45
IV
45
47
41
44
I
52
54
49
51
IV
49
I
52
IV
49
dB
dB
46
54
49
51
dB
46
I
44
fIN = 10.0MHz
TA = 0°C to +70°C,
TA = -25°C to +85°C
46
41
43
IV
43
Spurious-Free
Dynamic Range (SFDR)
fIN = 1MHz
TA = +25°C
V
67
67
dB
Differential Phase
fIN = 3.58MHz,
4.35MHz
TA = +25°C
V
0.2
0.2
Degrees
Differential Gain
fIN = 3.58MHz,
4.35MHz
TA = +25°C
V
0.5
0.7
%
40
_______________________________________________________________________________________
3
MAX1161
10-Bit, 40Msps, TTL-Output ADC
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +5.0V, VEE = -5.2V, DVCC = +5.0V, VIN = ±2.0V, VSB = -2.0V, VST = +2.0V, fCLK = 40MHz, 50% clock duty cycle,
TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER
TEST
LEVEL
CONDITIONS
MAX1161A
MIN TYP MAX
MAX1161B
MIN TYP MAX
2.4
2.4
UNITS
DIGITAL INPUTS
Logic 1 Voltage
V
Logic 0 Voltage
V
4.5
0.8
4.0
V
0.8
V
Maximum Input
Current Low
TA = +25°C
IV
0
5
20
0
5
20
µA
Maximum Input
Current High
TA = +25°C
IV
0
5
20
0
5
20
µA
Pulse Width Low (CLK)
IV
10
Pulse Width High (CLK)
IV
10
Logic 1 Voltage
IV
2.4
Logic 0 Voltage
IV
10
300
ns
10
300
ns
DIGITAL OUTPUTS
2.4
V
0.6
0.6
V
POWER-SUPPLY REQUIREMENTS
Voltages
Currents
VCC
IV
4.75
DVCC
IV
4.75
-VEE
IV
-4.95 -5.2
ICC
VI
118
145
118
145
DICC
VI
40
55
40
55
-IEE
VI
40
57
40
57
VI
1.0
1.3
1.0
1.3
V
1.0
Power Dissipation
Power-Supply Rejection
VCC = 5V ±0.25V, VEE = -5.2V ±0.25V
TEST LEVEL CODES
All electrical characteristics are subject to the following conditions:
All parameters having min/max specifications are guaranteed. The
Test Level column indicates the specific device testing actually performed during production and Quality Assurance inspection. Any
blank section in the data column indicates that the specification is
not tested at the specified condition.
Unless otherwise noted, all tests are pulsed; therefore, Tj = TC = TA.
5.0
5.25
4.75
5.25
4.75
5.25
5.0
5.25
-5.45 -4.95 -5.2
-5.45
1.0
V
mA
W
LSB
TEST LEVEL TEST PROCEDURE
I
100% production tested at the specified temperature.
II
100% production tested at TA = +25°C, and sample tested at the specified
III
IV
V
VI
temperatures.
QA sample tested only at the specified temperatures.
Parameter is guaranteed (but not tested) by design and characterization data.
Parameter is a typical value for information purposes only.
100% production tested at TA = +25°C. Parameter is guaranteed over specified
temperature range.
______________________________________________________________Pin Description
4
PIN
NAME
1, 13
DGND
2
D0
3–10
D1–D8
FUNCTION
PIN
NAME
FUNCTION
Digital Ground
17, 26
AGND
TTL Output (LSB)
18, 25
VCC
+5V Supply (analog)
TTL Outputs
19
VFT
Force for Top of Reference Ladder
Analog Ground
11
D9
TTL Output (MSB)
20
VST
Sense for Top of Reference Ladder
12
D10
TTL Output Overrange
21
VIN
Analog Input
14, 28
DVCC
+5V Supply (digital)
22
VRM
Middle of Voltage Reference Ladder
15
CLK
Clock
23
VSB
Sense for Bottom of Reference Ladder
16, 27
VEE
-5.2V Supply (analog)
24
VFB
Force for Bottom of Reference Ladder
_______________________________________________________________________________________
10-Bit, 40Msps, TTL-Output ADC
(TA = +25°C, unless otherwise noted.)
70
fS = 40Msps
70
SINAD (dB)
50
fS = 40Msps
70
60
60
SNR (dB)
50
50
40
40
40
30
30
30
20
20
20
1
10
100
10
INPUT FREQUENCY (MHz)
SNR, THD, SINAD vs.
SAMPLE RATE
SNR, THD, SINAD vs.
TEMPERATURE
40
20
-30
55
SINAD
50
10
SAMPLE RATE (Msps)
100
-60
-90
fS = 40Msps
fIN = 1MHz
-120
40
1
fS = 40Msps
fIN = 1MHz
THD
45
30
SPECTRAL RESPONSE
AMPLITUDE (dB)
THD
SNR, THD, SINAD (dB)
SINAD
100
0
SNR
60
SNR
60
10
INPUT FREQUENCY (MHz)
65
MAX1161-04
fIN = 1MHz
70
1
100
INPUT FREQUENCY (MHz)
80
50
1
MAX1161-06
THD (dB)
60
80
MAX1161-05
fS = 40Msps
MAX1161-02
80
MAX1161-01
80
SNR, THD, SINAD (dB)
SIGNAL-TO-NOISE AND DISTORTION
vs. INPUT FREQUENCY
SIGNAL-TO-NOISE vs.
INPUT FREQUENCY
MAX1161-03
TOTAL HARMONIC DISTORTION vs.
INPUT FREQUENCY
-25
0
25
50
TEMPERATURE (°C)
_______________Detailed Description
The MAX1161 requires few external components to
achieve the stated operation and performance. Figure 2
shows the typical interface requirements when using the
MAX1161 in normal circuit operation. The following section provides a description of the pin functions, and outlines critical performance criteria to consider for
achieving optimal device performance.
Power Supplies and Grounding
The MAX1161 requires -5.2V and +5V analog supply
voltages. The +5V supply is common to analog VCC and
digital DVCC. A ferrite bead in series with each supply
line reduces the transient noise injected into the analog
75
0
2
4
6
8
10
INPUT FREQUENCY (MHz)
VCC. These beads should be connected as close to the
device as possible. The connection between the beads
and the MAX1161 should not be shared with any other
device. Bypass each power-supply pin as close to the
device as possible. Use 0.1µF for VEE and VCC, and
0.01µF for DVCC (chip capacitors are recommended).
The MAX1161 has two grounds: AGND and DGND.
These internal grounds are isolated on the device. Use
ground planes for optimum device performance.
Use DGND for the DVCC return path (typically 40mA)
and for the return path for all digital output logic interfaces. Separate AGND and DGND from each other,
connecting them together only through a ferrite bead at
the device.
_______________________________________________________________________________________
5
MAX1161
__________________________________________Typical Operating Characteristics
MAX1161
10-Bit, 40Msps, TTL-Output ADC
N+1
N
tpwH
N+2
tpwL
CLK
td
CLK
td
OUTPUT
DATA
N-2
N-1
DATA VALID
N
DATA VALID
N+1
Figure 1a. Timing Diagram
OUTPUT
DATA
DATA VALID
Figure 1b. Single-Event Clock
Table 1. Timing Parameters
PARAMETER
DESCRIPTION
td
CLK to Data Valid Propagation Delay
tpwH
CLK High Pulse Width
10
tpwL
CLK Low Pulse Width
10
Connect a Schottky or hot carrier diode between AGND
and VEE. The use of separate power supplies between
VCC and DVCC is not recommended due to potential
power-supply-sequencing latchup conditions. For optimum performance, use the recommended circuit
shown in Figure 2.
Voltage Reference
The MAX1161 requires the use of two voltage references: VFT and VFB. VFT is the force for the top of the
voltage-reference ladder (typically +2.5V); VFB (typically -2.5V) is the force for the bottom of the voltagereference ladder. Both voltages are applied across an
800Ω internal reference-ladder resistance. The +2.5V
voltage source for reference VFT must be current limited
to 20mA (max) if a different driving circuit is used in
place of the recommended reference circuit shown in
Figures 2 and 3. In addition, there are three referenceladder taps (VST, VRM, and VSB). VST is the sense for
the top of the reference ladder (+2V), VRM is the midpoint of the ladder (typically 0V), and VSB is the sense
for the bottom of the reference ladder (-2V). The voltages at VST and VSB are the device’s true full-scale
input voltages when VFT and VFB are driven to the recommended voltages (+2.5V and -2.5V, respectively).
These points should be used to monitor the device’s
actual full-scale input range. When not being used, a
decoupling capacitor of 0.01µF (chip carrier preferred)
connected to AGND from each tap is recommended to
minimize high-frequency noise injection.
6
MIN
TYP
MAX
UNITS
14
18
ns
300
ns
ns
Figure 2 shows an example of a recommended reference-driver circuit. IC1 (MAX6225) is a +2.5V reference
with 0.2% accuracy. Potentiometer R1 is 10kΩ and supports a minimum adjustable range of 0.6%. Use an
OP07 or equivalent device for IC2. R2 and R3 must be
matched to within 0.1% with good TC tracking to maintain 0.3LSB matching between VFT and VFB. If 0.1%
matching is not met, then R4 can be used to adjust the
VFB voltage to the desired level. Adjust VFT and VFB
such that VST and VSB are exactly +2V and -2V,
respectively.
The analog input range scales proportionally with respect
to the reference voltage if a different input range is
required. The maximum scaling factor for device operation is ±20% of the recommended reference voltages of
VFT and VFB. However, because the device is laser
trimmed to optimize performance with ±2.5V references,
its accuracy degrades if operated beyond a ±2% range.
The following errors are defined:
+FS error = top of ladder offset voltage
= ∆ (+FS - VST + 1LSB)
-FS error = bottom of ladder offset voltage
= ∆ (-FS - VSB - 1LSB)
where the +FS (full-scale) input voltage is defined as the
output transition between 11 1111 1110 and 11 1111 1111,
and the -FS input voltage is defined as the output transition between 00 0000 0000 and 00 0000 0001 (Table 2).
_______________________________________________________________________________________
10-Bit, 40Msps, TTL-Output ADC
MAX1161
R5
100Ω
VIN
5
+5V
0.01µF
4
7
C6
0.1µF
C8
0.1µF
C10
0.01µF
C7
0.1µF
C9
0.1µF
C11
0.01µF
FB
NOTES:
1) D1 = SCHOTTKY OR HOT CARRIER DIODE
2) FB = FERRITE BEAD, FAIR RITE #2743001111
TO BE MOUNTED AS CLOSELY TO THE DEVICE
AS POSSIBLE. THE FERRITE BEAD TO ADC
CONNECTION SHOULD NOT BE SHARED WITH
ANY OTHER DEVICE.
3) C1–C11 = CHIP CAPACITOR (RECOMMENDED)
MOUNTED AS CLOSE TO DEVICE'S PIN AS
POSSIBLE.
4) USE OF A SEPARATE SUPPLY FOR VCC AND DVCC
IS NOT RECOMMENDED.
5) R5 PROVIDES CURRENT LIMITING TO 45mA.
R
VFB
VEE
= AGND
DIGITAL
OUTPUTS
D3
D2
SUCCESSIVE
INTERPOLATION
STAGE N
C5
0.01µF
= DGND
D5
D4
D0 (LSB)
6
-2.5V
D8
D7
D6
D1
2R
VSB
1µF
SUCCESSIVE
INTERPOLATION
STAGE 1
2R
C4
0.01µF
0.01µF
8
2R
VRM
R3
30k
DECODING NETWORK
IC2
OP07
R4
10k
-5.2V
DGND
1
2
C3
0.01µF
DVCC
3
2R
DVCC
R2
30k
D9 (MSB)
ANALOG
PRESCALER
FB
FB
VTRIM
GND
1µF
R
VCC
MAX6225
D10 (OVERRANGE)
C2
0.01µF
C1
VST
0.01µF
VCC
4
R1
10k
AGND
1µF
VFT
2.5V
AGND
6
IC1 VOUT
2 VIN
4
COARSE
ADC
DGND
±2.5V MAX
VEE
VIN
(±2V)
+5V
MAX1161
CLK
CLK
(TTL)
D1
10µF
10µF
-5.2V
+5V
AGND
DGND
Figure 2. Typical Operating Circuit
Analog Input
VCC
ANALOG PRESCALER
VIN is the analog input. The full-scale input range will be
80% of the reference voltage, or ±2V with VFB =
-2.5V and VFT = +2.5V.
The analog input’s drive requirements are minimal
when compared to conventional flash converters. This
is due to the MAX1161’s extremely low (5pF) input
capacitance and very high (300kΩ) input resistance.
For example, for an input signal of ±2Vp-p with a
10MHz input frequency, the peak output current
required for the driving circuit is only 628µA.
VIN
VFT
VEE
Figure 3. Analog Equivalent Input Circuit
_______________________________________________________________________________________
7
Table 2. Output Data Information
ANALOG
INPUT
OVERRANGE
D10
OUTPUT CODE
D9–D0
> +2V + 1/2LSB
1
1 1 1 111 1111
+2V - 1LSB
0.0V
-2V + 1LSB
0
0
0
1 1 1 111 111Ø
ØØ ØØØØ ØØØØ
00 0000 000Ø
< 2V
0
00 0000 0000
(Ø indicates the flickering bit between logic 0 and 1.)
Clock Input
The MAX1161 is driven from a single-ended TTL input
(CLK). The CLK pulse width (t pwH ) must be kept
between 10ns and 300ns to ensure proper operation of
the internal track/hold amplifier (Figure 1a). When operating the MAX1161 at sampling rates above 3Msps, it is
recommended that the clock input duty cycle be kept
at 50% to optimize performance (Figure 4). The analog
input signal is latched on the rising edge of CLK.
The clock input must be driven from fast TTL logic (VIH
≤ 4.5V, tRISE <6ns). In the event the clock is driven from
a high current source, use a 100Ω resistor (R5) in
series to limit current to approximately 45mA.
Digital Outputs
The format of the output data (D0–D9) is straight binary
(Table 2). The outputs are latched on the rising edge of
CLK with a propagation delay typically at 14ns. There is
a one-clock-cycle latency between CLK and the valid
output data (Figure 1a).
The digital outputs’ rise and fall times are not symmetrical. Typical propagation delay is 14ns for the rise time
and 6ns for the fall time (Figure 5). The nonsymmetrical
rise and fall times create approximately 8ns of invalid
data.
Overrange Output
The overrange output (D10) is an indication that the
analog input signal has exceeded the positive full-scale
input voltage by 1LSB. When this condition occurs, D10
will switch to logic 1. All other data outputs (D0–D9) will
remain at logic 1 as long as D10 remains at logic 1.
This feature makes it possible to include the MAX1161
in higher-resolution systems.
Evaluation Board
The MAX1160 EV kit is available to help designers
demonstrate the MAX1160 or MAX1161’s full performance. This board includes a reference circuit, clockdriver circuit, output data latches, and an on-board
reconstruction of the digital data. A separate data sheet
describing the operation of this board is also available.
Contact the factory for price and availability.
N
59
57
SIGNAL-TO-NOISE-RATIO (dB)
MAX1161
10-Bit, 40Msps, TTL-Output ADC
N+1
CLK IN 2.4V
55
6ns
53
51
DUTY CYCLE =
49
tpwL
tpwH
tpwL
47
tpwH
tRISE
6ns
typ
3.5V
DATA 2.4V
OUT
(ACTUAL) 0.8V
0.5V
(N - 2)
INVALID
DATA
(N - 1)
INVALID
DATA
N
tpd1
45
14ns typ
43
25
30 35 40 45 50 55 60 65 70 75
DUTY CYCLE OF POSITIVE CLOCK PULSE (°C)
DATA OUT
(EQUIVALENT)
(N - 2)
INVALID
DATA
(N - 1)
INVALID
DATA
N
Figure 5. Digital Output Characteristics
Figure 4. SNR vs. Clock Duty Cycle
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
8 ___________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600
© 1997 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.