ST7536 POWER LINE MODEM . .. .. . .. . HALF DUPLEX SYNCHRONOUS FSK MODEM - TWO PROGRAMMABLE CHANNELS FOR 600BPS DATA RATE - TWO PROGRAMMABLE CHANNELS FOR 1200BPS DATA RATE AUTOMATICALLYTUNED Rx AND Tx FILTERS TX CARRIER FREQUENCIES SYNTHESIZED FROM EXTERNAL CRYSTAL LOW DISTORTION Tx SIGNAL (S/H2 ≥ 50dB) AUTOMATIC LEVELCONTROL ON Tx SIGNAL Rx SENSITIVITY : 2mVRMS (600bps) 3mVRMS (1200bps) Rx CLOCK RECOVERY POWER-DOWN MODE SUITABLE TO APPLICATION IN ACCORDANCE WITH DH028/29 ENEL, EN50065-1 CENELEC AND FCC SPECIFICATIONS PLCC28 (Plastic Leaded Chip Carrier Package) ORDER CODE : ST7536CFN November 1998 TEST 3 TEST 4 RESET Rx/Tx ATO ALCI TxFI 3 2 1 28 27 26 AGND 9 21 AVSS TEST 1 10 20 DEMI TEST 2 11 19 IFO 7536-01.EPS 8 DVDD 18 DGND DVSS AVD D 22 17 23 AFCF 7 16 RxDEM 15 RAI BRS 24 CHS 6 14 CLR/T XTAL 1 RxFO XTAL 2 25 13 5 12 The ST7536 is a half duplex synchronous FSK MODEM designed for power line communication network applications. It operates from a dual power supply +5V and -5V, and requires an external interface for the coupling to the power line. It offers two programmable data rate with two programmable channels each. RxD TxD DESCRIPTION 4 PIN CONNECTIONS 1/9 ST7536 PIN DESCRIPTION Pin Number Name Type 1 Rx/Tx Digital Rx or Tx mode selection input 2 RESET Digital Logic reset and power-down mode input. Active when low. 3 TEST4 Digital Test input which selects the Tx band-pass filter input (TxFI) when high. 4 TEST3 Digital Test input which gives an access to the clock recovery input stage. This input is selected when TEST1 is high. 5 RxD Digital Synchronous receive data output 6 CLR/T Digital Rx or Tx clock according to the functional mode 7 RxDEM Digital Demodulated data output 8 DGND Supply Digital ground 2/9 9 DVDD Supply Digital positive supply voltage : 5V ± 5% 10 TEST1 Digital Test input which cancels the Tx to Rx mode automatic switching and validates TEST3 input. Active when high. 11 TEST2 Digital Test input which reduces the Tx to Rx mode automatic switching time. Active when high. 12 TxD Digital Transmit data input 13 XTAL2 Digital Crystal oscillator output 14 XTAL1 Digital Crystal oscillator input 15 CHS Digital Channel selection input 16 BRS Digital Baud rate selection input 17 AFCF Analog Automatic frequency control output for connecting compensation network. 18 DVSS Supply Digital negative supply voltage : -5V ± 5% 19 IFO Analog Intermediate frequency filter output 20 DEMI Analog FSK demodulator input 21 AVSS Supply Analog negative supply voltage : -5V ± 5% 22 AGND Supply Analog ground : 0V 23 AVDD Supply Analog positive supply voltage : 5V ± 5% 24 RAI Analog Receive analog input 25 RxFO Analog Receive filter output 26 TxFI Analog Transmit filter input (selected when TEST4 is high) 27 ALCI Analog Automatic level control input 28 ATO Analog Analog transmit output 7536-01.TBL Description ST7536 BLOCK DIAGRAM RX BAND-PASS S.C. FILTER DVSS 18 DGND 8 AVSS 21 DVDD 9 20dB GAIN AGND 22 AVDD 23 SMT. FILTER SMT. FILTER RAI 24 A.A. FILTER 25 A.A. FILTER RxFO I.F. BAND-PASS S.C. FILTER 19 IFO 13 XTAL2 14 XTAL1 AFCF 17 1 Rx/Tx TIME BASE AND CONTROL LOGIC REFERENCE VOLTAGE AFC 2 RESET 16 BRS TX BAND-PASS S.C. FILTER A.A. FILTER ALC MUX ATO 28 A.A. FILTER 15 CHS FSK MODULATOR ALCI 27 12 TxD 26 TxFI CLOCK RECOVERY POST-DEMO S.C. FILTER 20 DEMI CORRELATOR FSK DEMODULATOR 3 4 TEST3 ST7536 7536-02.EPS 10 11 TEST4 TEST LOGIC TEST2 CLR/T 6 TEST1 RxD 5 MUX RxDEM 7 3/9 ST7536 FUNCTIONAL DESCRIPTION 1 - Transmit Section The transmit mode is set when Rx/Tx = 0, if Rx/Tx is held at 0 longer than 3s, thenthe device switches automatically in the Rx mode. A new activation of the Tx mode requires Rx/Tx to be returned to 1 for a minimum 2µs period before being set to 0. The Transmit Data (TxD) is sampled on a positive edge of CLR/T which delivers the transmit bit clock when the transmit mode is selected. This data enters a FSK modulator whose two basic frequencies are selected by the Baud Rate Selection pin (BRS) and the Channel Selection pin (CHS) according to the Table 1. Figure 1 : Tx Data Input Timing 7536-03.EPS CLR/T DATA VALID TxD Table 1 BRS CHS Baud Rate (Baud) Tx Frequencies (kHz) TxD=1 - TxD=0 0 0 600 81.75 - 82.35 0 1 600 67.2 - 67.8 1 0 1200 71.4 - 72.6 1 1 1200 85.95 - 87.15 These frequencies are synthesized from a 11.0592MHzcrystal oscillator ; theirprecision is the same as the crystal one’s (100 ppm). The modulatedsignal coming out of the FSK modulator is filtered by a switched-capacitor band-pass filter (Tx band-pass) in order to limit the output spectrum and to reduce the level of harmonic components. The output stage of the Tx path consists of an Automatic Level Control (ALC) systemwhich keeps the output signal (ATO) amplitude independant of the lineimpedancevariations. ThisALC isa variable gain system (with 32 discrete values) controlled by an analog feed-back signal ALCI (see Figure 2). The ALC gain range is 0dB to -26dB and gain change is clocked at 7200Hz. Gain steps are of magnitude 0.84dB typically. A period of this clock is decomposed into a 34.7µs gain settling latency and a 104.2µs peak detecting time. The gain change is related to the result of a peak detection obtained by making a direct comparison of ALCI maximum value (during detecting time) with two threshold voltages VT1 and VT2 (see Figure 2). - max (VALCI) < VT1 - The next gain is increased by 0.84dB, - VT1 ≤ max (VALCI) ≤ VT2 - No gain change, - VT2 < max (VALCI) - The next gain is decreased by 0.84dB. Figure 2 : Automatic Level Control Timing Chart Low Gain Correct Gain Amplitude modification due to an external cause High Gain Correct Gain VT2 VT1 4/9 7536-04.EPS ALC CLOCK Peak detecting time 104.2µs Gain setting latency 34.7µs ALCI SIGNAL ENVELOP ST7536 FUNCTIONAL DESCRIPTION (continued) (47nF ±10%, 10V) and R1 (1.5kΩ ±5%) connected to pin AFCF. 2 - Receive Section The receive section is active when Rx/Tx = 1. The baud rate and channel selection is also made according to Table 1. The Rx signal is applied on RAI with a common mode voltage of 0V and filtered by a band-pass switched capacitor filter (Rx band-pass) centered on the receivedcarrier frequencyand whose bandwidth is around 6kHz. The input voltage range on RAI is 2mVRMS - 2VRMS. The Rx filter outputis amplifiedby a 20dBgain stage whichprovidessymmetrical limitations forlarge voltage. The resulting signal is down-converted by a mixer which receives a local oscillator synthesized by the FSK modulatorblock. Finally an intermediate frequency band-pass filter (IF band-pass) whose central frequency is 2.7kHz when BRS = 0 and 5.4kHz when BRS = 1 improves the signal to noise ratio before entering the FSK demodulator. The coupling of the intermediate frequency filter output (IFO) to the FSKdemodulatorinput (DEMI) is made by an externalcapacitor C5 (1µF ±10%, 10V) which cancels the Rx path offset voltage. A clock recovery circuit extracts the receive clock (CLR/T) from the demodulated output (RxDEM) and delivers synchronous data (RxD) on the positive edge of CLR/T. Figure 4 : Automatic Frequency Loop Filter C2 17 3 - Additional Digital and Analog Functions A reset intput (RESET) initializes the device. When RESET = 0, the device is in power-down mode and all the internal logic is reset. When RESET = 1, the device is active. A time base section delivers all the internal clocks from a crystal oscillator (11.0592MHz). The crystal is connected between XTAL1 and XTAL2 pins and needs two external capacitors C3 and C4 depending o n t he cryst al ch ara cte ristic typically 22pF ±10% for proper operation. It is also possible to provide directly the clock on pin XTAL1 ; in this case C3 and C4 should be removed. An Automatic Frequency Control (AFC) Section adjusts the central frequency of Rx and Tx bandpass filter to the carrier central frequency. The stability of the AFC loop is ensured by an external compensationnetwork C1 (470nF ±10%, 10V), C2 7536-05.EPS CLR/T DATA VALID C1 R1 22 4 - Testing Features - An additionnalamplifier allows the observationof the Rx band-pass filter output on pin RxFO. - A direct input to the Tx band-pass filter (TxFI) is available and selected when TEST4 = 1. - The 3 second normal duration of the Tx to Rx mode automatic switching is reduced to 1.48ms when TEST2 = 1. - When TEST1 = 1 the Tx to Rx mode automatic switching is desactivated and the functional mode of the circuit is controlledby Rx/Tx as follow : when Rx/Tx = 0 the circuit is transmitting continuously, whenRx/Tx = 1 the clock recovery block is disconnected from the FSK demodulator for testing purpose, in this configurationTEST 3 is the data input of the clock recovery block, RxDEM follow TEST3 and RxD delivers the resynchronized data. Figure 3 : Rx Data Output Timing RxD AGND 7536-06.EPS AFCF 5 - Power Supplies Wiring and Decoupling Precautions The ST7536 has two positive power supply pins, two negative power supply pins and two ground pins in order to separate internal analog and digital supplies. The analog and digital terminals of each supply pair must be connected together externally and require special routing precautions in order to get the best receive sensitivity performances. The three major routing requirements are : - The ground impedance should be as low as possible, for this purpose the AGND an DGND terminals can be connected via a local plane. - The positive and negative power supplies (AVDD, DVDD, AVSS, DVSS) should be star-connected, avoiding common current path for the digital and analog power supplies terminals. - Five decoupling capacitors located as close as possible to the power supply terminals should be used. Two 2.2µF tantalum and two 100nF ceramic capacitors perform the main decoupling function in the vicinity of the analog power supplies and a 100nFceramiccapacitor in the vicinity of the positive digital power supply is used to reduce the high frequency perturbations generated by the logic part of the circuit. 5/9 ST7536 Symbol Parameter AVDD /DVDD Positive Supply Voltage (1) AVSS /DVSS Negative Supply Voltage (1) VAGND/DGND Voltage between AGND and DGND Value Unit -0.3, +7 V -7, +0.3 V -0.3, +0.3 V V VI Digital Input Voltage DGND-0.3, DVDD+0.3 VO Digital Output Voltage DGND-0.3, DVDD+0.3 V IO Digital Output Current -5, +5 mA Vi Analog Input Voltage AVSS-0.3, AVDD+0.3 V Vo Analog Output Voltage AVSS-0.3, AVDD+0.3 V Io Analog Output Current -5, +5 mA PD Power Dissipation 500 mW Toper Operating Temperature - 25, + 70 o C Tstg Storage Temperature - 65, + 150 o C 7536-02.TBL ABSOLUTE MAXIMUM RATINGS Notes : 1. The voltages are referenced to AGND and DGND. 2. Latch-up problems can be overcome with 2 reverse biased schottky diodes connected respectively between A/DVDD & A/DGND and A/DVSS & A/DGND. 3. Absolute maximum ratings are values beyond which damage to device may occur. Functional operation un der these conditions is not implied. GENERAL ELECTRICAL CHARACTERISTICS The test conditions are A/DVDD = +5V, A/DVSS = -5V, A/DGND = 0V, Tamb = -10 to 70oC unless otherwise specified Parameter AVDD/DVDD Positive Supply Voltage Test Conditions Min. Typ. Max. Unit 4.75 5 5.25 V AVSS/DVSS Negative Supply Voltage -5 -4.75 V AIDD + DIDD Positive Supply Current in Tx Mode RESET = 1, RX/Tx = 0 30 35 mA AIDD + DIDD Positive Supply Current in Rx Mode RESET = 1, RX/Tx = 1 29 34 mA AISS + DISS Negative Supply Current in Tx Mode RESET = 1, RX/Tx = 0 - 34 - 29 mA AISS + DISS Negative Supply Current in Rx Mode RESET = 1, RX/Tx = 1 - 33 - 28 mA AIDD + DIDD Positive Power-down Current AISS + DISS Negative Power-down Current RESET = 0, RX/Tx = 1 XTAL1 = 1 6/9 -5.25 1.2 mA - 1.2 mA 2.2 V VIH High Level Input Voltage Digital inputs except XTAL1 VIL Low Level Input Voltage Digital inputs VOH High Level Output Voltage Digital outputs, IOH = - 400µA VOL Low Level Output Voltage Digital outputs, IOL = 1.6mA VIH High Level Input Voltage XTAL1 input 3.6 DC XTAL1 Clock Duty Cycle External clock 40 0.8 2.4 V V 0.4 V V 60 % 7536-03.TBL Symbol ST7536 TRANSMITTER ELECTRICAL CHARACTERISTICS The test conditions are A/DVDD = +5V, A/DGND = 0V, A/DVSS = -5V, Tamb = -10 to +70oC unless othewise specified Parameter Test Conditions Min. Typ. Max. Unit 2.8 3.2 VTAC Max Carrier Output AC Voltage RL = 2kΩ, VALCI < VT1 HD2 Second Harmonic Distortion RL = 2kΩ, VALCI < VT1 FD FSK Peak-to-peak Deviation BRS = 0 BRS = 1 TRxTx Carrier Activation Time After Rx/Tx 1 → 0 transition 1 ms TALC Carrier Stabilisation Time ALC maximum settling time, 32 gain steps 5 ms DRNG ALC Dynamic Range 27 dB 0.32 600 1200 25 26 VT1 ALC Low Threshold Voltage VT2 ALC High Threshold Voltage 2.12 GST ALC Gain Step 0.84 PSRR1 PSRR2 1.81 Power supply rejection ratio on ATO (see Note 1) 3.7 VIN = 200mVPP, fIN = 50Hz on VDD or VSS VPP % Hz Hz 1.87 V 2.18 V dB 35 10 dB dB 7536-04.TBL Symbol Note 1 : This characteristic is guaranteed by correlation. RECEIVER ELECTRICAL CHARACTERISTICS The test conditions are A/DVDD = +5V, A/DGND = 0V, A/DVSS = -5V, Tamb = -10 to +70oC unless othewise specified Parameter VIN Maximum Input Signal RIN Input Impedance RCJ Recovered Clock Jitter PSRR1 PSRR2 BER1 BER2 Min. Typ. Max. Unit 2 VRMS 100 Percentage of the nominal clock Power supply rejection ratio on VIN = 200mVPP, fIN = 50Hz on VDD or VSS RxFO (see Note 1) Rx sensitivity (see Note 1) VIN0 VIN1 Test Conditions kΩ -5 +5 35 10 dB dB -5 Typical measured BER < 10 BRS = 0 BRS = 1 Bit error rate at minimum Rx White Noise, S/N = 15dB signal (see Note 1) RAI = 2mVRMS, BRS = 0 RAI = 3mVRMS, BRS = 1 mVRMS 2 3 2 ⋅ 10-5 -4 3 ⋅ 10 10-3 -3 10 BER3 Bit error rate at maximum Rx sig- RAI = 2VRMS, White Noise, S/N = 25dB nal (see Note 1) 10-7 10-3 BER4 Bit error rate at medium Rx signal RAI= 0.6VRMS, S/N= 15dB (see Note 1) 10-6 10-3 BER5 Bit error rate with impulsive noise RAI = 90mVRMS, N = 5VPP pulse wave, (see Note 1) f = 100Hz, duty cycle = 10% BER6 BER7 Bit error rate with modulated S+ Ns < 0.2VRMS, Ns = sine carrier with sinusoidal noise Ns (see Note 1) 80% AM modul., f m = 1kHz, See Figure 5 Smin = 2mVRMS, BRS = 0 Smin = 3mVRMS, BRS = 1 % 10-3 7536-05.TBL Symbol 10-3 10-3 Note 1 : This characteristic is guaranteed by correlation 7/9 ST7536 Figure 5 : S/N Mask for 80% AM Sine Noise 20 S/N S (dB) B 10 0 -10 -20 -30 -40 -50 0 0.5 1 1.5 2 B = 20kHz at 600 Bit/s (BRS = 0) B = 40kHz at 1200 Bit/s -BRS = 1) 7536-07.EPS Frequency (f/fc) fc : Central Carrier Frequency FILTER TEMPLATES Test Conditions Amplitude (dB) Min. Typ. Max. 8/9 BRS = 0, CHS = 0 -4 -4 BRS = 0, CHS = 1 -4 -4 BRS = 1, CHS = 0 -4 -4 BRS = 1, CHS = 1 -4 -4 Test Conditions Amplitude (dB) Min. Typ. Max. INTERMEDIATE FREQUENCY FILTER RECEIVE AND TRANSMIT FILTER 54 79.05 Ref 82.05 85.05 123 44.4 65 Ref 67.46 69.93 101.13 47.57 69.64 Ref 72.28 74.92 108.36 57.08 83.57 Ref 86.74 89.91 130.03 Frequency (kHz) -3 0 -3 -3 0 -3 -3 0 -3 -3 0 -3 - 35 -2 -2 - 35 - 35 -2 -2 - 35 - 35 -2 -2 - 35 - 35 -2 -2 - 35 1.2 2.15 Ref 2.7 3.25 5.8 2.4 4.3 Ref 5.4 6.5 11.6 -5 BRS = 0 -5 -5 BRS = 1 -5 -3 0 -3 -3 0 -3 - 35 -2 -2 - 35 - 35 -2 -2 - 35 7536-06.TBL Frequency (kHz) ST7536 PMPLCC28.EPS PACKAGE MECHANICAL DATA 28 PINS - PLASTIC LEADED CHIP CARRIER (PLCC) A B D D1 D2 E e e3 F F1 G M M1 Min. 12.32 11.43 4.2 2.29 0.51 9.91 Millimeters Typ. Max. 12.57 11.58 4.57 3.04 10.92 Min. 0.485 0.450 0.165 0.090 0.020 0.390 1.27 7.62 0.46 0.71 Inches Typ. Max. 0.495 0.456 0.180 0.120 0.430 0.050 0.300 0.018 0.028 0.101 1.24 1.143 0.004 PLCC28.TBL Dimensions 0.049 0.045 Information furnished is believed to be accurate and reliable. However, STMicroelectroni cs assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No licence is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical comp onents in lifesupport devicesor systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 1998 STMicroelectronics - All Rights Reserved 2 2 Purchase of I C Components of STMicroelectronics, conveys a license under the Philips I C Patent. 2 Rights to use these components in a I C system, is granted provided that the system conforms to 2 the I C Standard Specifications as defined by Philips. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http://www.st.com 9/9