INTEGRATED CIRCUITS DATA SHEET UDA1309H Low-power stereo bitstream ADC/DAC Product specification Supersedes data of 1996 Jul 18 File under Integrated Circuits, IC01 1998 Jan 06 Philips Semiconductors Product specification Low-power stereo bitstream ADC/DAC UDA1309H FEATURES • Low power • Integrated high-pass filter to cancel DC offset (ADC) • Analog loop-through function • Multiple digital input/output formats possible • 256fs system clock frequency • Several power-down modes • Digital de-emphasis (DAC) APPLICATION • Overload detector to enable automatic recording level adjustment (ADC) • Portable digital audio equipment. • High dynamic range • DAC requires only one capacitor for post-filtering GENERAL DESCRIPTION • Small 44-pin quad flat pack with 0.8 mm pitch The UDA1309H is a single chip stereo analog-to-digital and digital-to-analog converter employing bitstream conversion techniques. The device is eminently suitable for use in low-power portable digital audio equipment which incorporates recording and playback functions. • 256fs system clock frequency in Analog-to-Digital (AD) and Digital-to-Analog (DA) mode • Choice of three system clock frequencies (192fs, 256fs or 384fs) in DA mode. ORDERING INFORMATION TYPE NUMBER PACKAGE NAME DESCRIPTION VERSION UDA1309H QFP44 plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 × 10 × 1.75 mm SOT307-2 1998 Jan 06 2 Philips Semiconductors Product specification Low-power stereo bitstream ADC/DAC UDA1309H QUICK REFERENCE DATA VDDD = VDDA = VDDO = VDDD(F) = 5 V; VSSD = VSSA = VSSO = VSSD(F) = 0 V; Tamb = 25 °C; full scale sine wave input; mode 1; fi = 1 kHz; 16-bit input data; conversion rate = 44.1 kHz; measurement bandwidth = 10 Hz to 20 kHz; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT 4.5 5.0 Supply VDDA(AD) ADC analog supply voltage (pin 8) 5.5 V VDDA(DA) DAC analog supply voltage (pin 25) 4.5 5.0 5.5 V VDDO operational amplifiers supply voltage (pin 19) 4.5 5.0 5.5 V VDDD ADC and DAC digital supply voltage (pin 28) 4.5 5.0 5.5 V VDDD(F) digital filters supply voltage (pin 34) 4.5 5.0 5.5 V IDDA(AD) ADC analog supply current (pin 8) − 9 13.5 mA IDDA(DA) DAC analog supply current (pin 25) − 4.5 6.8 mA IDDO operational amplifiers supply current (pin 19) − 14 21 mA IDDD ADC and DAC digital supply current (pin 28) − 0.2 0.5 mA IDDD(F) digital filters supply current (pin 34) − 24 36 mA Tamb operating ambient temperature −20 − +75 °C 0.9 1.0 1.1 V Analog-to-digital converter VI(rms) input voltage (RMS value) note 1 (THD + N)/S total harmonic distortion plus noise-to-signal ratio at 0 dB − −85 tbf dB at −60 dB; A-weighted − −35 −30 dB S/N idle channel signal-to-noise ratio VI = 0 V; A-weighted tbf 95 − dB αcs channel separation − 90 − dB note 2 0.9 1.0 1.1 V at 0 dB − −90 −82 dB Digital-to-analog converter VO(rms) output voltage (RMS value) (THD + N)/S total harmonic distortion plus noise-to-signal ratio S/N idle channel signal-to-noise ratio αcs channel separation at −60 dB; A-weighted − −38 −34 dB at −60 dB; A-weighted; note 3 − −44 − dB code 0000H; A-weighted − 104 − dB 90 100 − dB Notes 1. VI for full scale digital output is a function of VDDA(AD) [1.0 V (RMS) at VDDA(AD) = 5.0 V is equivalent to −1.0 dB in the digital domain]. 2. At full scale digital input; no de-emphasis; VO(rms) is a function of VDDA(DA). 3. 18-bit input data. 1998 Jan 06 3 1998 Jan 06 4 16 47 µF 330 pF 4.7 kΩ BAIR 14 analog input VIR 4.7 kΩ 0.22 µF ADref BAIL 13 BAOR 15 ADC DIGITAL FILTER ADC 4 44 2 1 41 6 42 3 30 Fig.1 Block diagram. 34 33 UDA1309H DAC DIGITAL FILTER DAC 36 32 31 35 29 39 VSS(I/O) DIGITAL INTERFACE 43 DAPON ADENB DASDA ADWS DABCK ADBCK DAWS ADSDA OVLOAD ADPON ANLPTR 5 37 MODE SELECT 38 DIGITAL INTERFACE BAOL Vref(pos) Vref(neg) 12 11 40 9 CURRENT IDAC REFERENCE Vm 10 Vref 4.7 kΩ 0.22 µF 26 28 VDDD 25 24 VOR MBH527 0.22 µF 18 DAref VOL 21 analog output VOR DACR 1 nF VSSD 1.6 kΩ Vm 1.6 kΩ DACL 22 23 20 1 nF analog output VOL 27 19 VDDA(DA) CLKEDGE VSSD(F) VSSA(DA) DADEM TEST0 MODE2 VDDO MODE1 TEST1 VDDD(F) SYSCLK MODE0 VSSO 10 µF Low-power stereo bitstream ADC/DAC Supply decoupling on pins 19, 25, 28 and 34; 0.22 µF (ceramic), 47 µF (electrolytic). Capacitance at pin 11 should be close to pins 11 and 9. 47 kΩ Iref 17 VDDA(AD) 8 VSSA(AD) 7 0.22 µF 330 pF VDDA(AD) ook, full pagewidth 4.7 kΩ 47 µF analog input VIL Philips Semiconductors Product specification UDA1309H BLOCK DIAGRAM Philips Semiconductors Product specification Low-power stereo bitstream ADC/DAC UDA1309H PINNING SYMBOL PIN DESCRIPTION ADBCK 1 ADC input bit clock; 32fs or 64fs ADWS 2 ADC word select input at fs MODE0 3 ADC/DAC mode select input ADENB 4 ADC serial data enable input (active HIGH) OVLOAD 5 ADC output overload flag (active LOW) ADPON 6 ADC power-on-mode input (active HIGH) VSSA(AD) 7 ADC analog ground supply voltage VDDA(AD) 8 ADC analog supply voltage Vref(neg) 9 ADC negative reference voltage input (ground) Vref 10 ADC decoupling capacitor Vref(pos) 11 ADC positive reference voltage decoupling capacitor BAOL 12 ADC input amplifier output left BAIL 13 ADC input amplifier virtual ground left BAIR 14 ADC input amplifier virtual ground right BAOR 15 ADC input amplifier output right ADref 16 ADC decoupling capacitor Iref 17 ADC/DAC reference current resistor input DAref 18 DAC decoupling capacitor VDDO 19 ADC/DAC operational amplifier supply voltage VSSO 20 ADC/DAC operational amplifier ground supply voltage VOL 21 DAC output voltage left DACL 22 DAC output current left DACR 23 DAC output current right VOR 24 DAC output voltage right VDDA(DA) 25 DAC analog supply voltage VSSA(DA) 26 DAC analog ground supply voltage VSSD 27 ADC/DAC digital ground supply voltage VDDD 28 ADC/DAC digital supply voltage DAPON 29 DAC power-on-mode input (active HIGH) DADEM 30 DAC digital de-emphasis input (active HIGH) DABCK 31 DAC input bit clock; 32fs, 48fs or 64fs DAWS 32 DAC word select input at fs VSSD(F) 33 ADC/DAC digital filters ground supply voltage VDDD(F) 34 ADC/DAC digital filters supply voltage DASDA 35 DAC serial data input ANLPTR 36 ADC/DAC analog loop-through input (active HIGH) TEST0 37 ADC/DAC enable test mode 0 input (LOW is normal mode) TEST1 38 ADC/DAC enable test mode 1 input (LOW is normal mode) VSS(I/O) 39 ADC/DAC digital input/output ground supply voltage SYSCLK 40 ADC/DAC system clock input (fsys = 256fs; DAC also 192fs and 384fs) 1998 Jan 06 5 Philips Semiconductors Product specification Low-power stereo bitstream ADC/DAC PIN DESCRIPTION handbook, full pagewidth 35 DASDA ADC/DAC input bit clock rising/falling edge 36 ANLPTR 44 37 TEST0 CLKEDGE 38 TEST1 ADC/DAC mode 2 select input 39 VSS(I/O) ADC/DAC mode 1 select input 43 40 SYSCLK 42 MODE2 41 ADSDA MODE1 42 MODE1 ADC serial data output 43 MODE2 41 44 CLKEDGE ADSDA 34 VDDD(F) SYMBOL UDA1309H ADBCK 1 33 VSSD(F) ADWS 2 32 DAWS MODE0 3 31 DABCK ADENB 4 30 DADEM OVLOAD 5 29 DAPON 28 VDDD ADPON 6 VSSA(AD) 7 27 VSSD VDDA(AD) 8 26 VSSA(DA) Vref(neg) 9 25 VDDA(DA) UDA1309H 24 VOR Vref 10 Vref(pos) 11 Fig.2 Pin configuration. 1998 Jan 06 6 DACL 22 VOL 21 VSSO 20 DAref 18 VDDO 19 Iref 17 ADref 16 BAOR 15 BAIR 14 13 BAIL BAOL 12 23 DACR MBH526 Philips Semiconductors Product specification Low-power stereo bitstream ADC/DAC The digital interfaces accommodates, 16 and 18-bit, I2S-bus and LSB justified formats. The ADC digital output can be made 3-state by means of the ADENB signal, this enables the use of a digital bus. FUNCTIONAL DESCRIPTION Figure 1 illustrates the various components of the UDA1309H. The analog-to-digital converter is a bitstream type converter, both channels are sampled simultaneously. The digital-to-analog converter is a BCC (Bitstream Continuous Calibration) type converter. The digital filter for the ADC is a bit serial IIR filter that produces a fairly linear phase response up to 15 kHz. A high-pass filter is incorporated in the down-sampling path to remove DC offsets. An overload detection circuit is incorporated to facilitate automatic recording level adjustment. The UDA1309H interface accommodates slave mode only, therefore, the system ICs must provide the system clock, bit clock and word clock signals. For the DAC, the UDA1309H accepts the data together with these clocks, for the ADC it delivers the data in response to these clocks. Within one stereo frame, the first sample always represents the left channel. When sending data the unused bit positions are set to zero, when receiving data these bit positions are don't cares. The digital up-sample filter for the DAC is partly IIR, with virtual linear phase response up to 15 kHz, and partly FIR. A switchable digital de-emphasis circuit is also incorporated. Due to the BCC principle used, the DAC needs only single pole post-filtering (one external capacitor) to meet the out-of-band suppression requirement. To accommodate the various interface formats and system clock frequencies four control pins are provided, MODE0 to MODE2 for mode selection and CLKEDGE which selects the active edge of the BCK signal. Table 1 gives the interface mode selection, Fig.3 illustrates the ADC/DAC data formats and Fig.5 the operating modes. The section of the UDA1309H is designed to accommodate two main modes: The ADC and DAC channels have separate power-down modes, to reduce power if one of them is not in use. An analog loop-through function enables analog-input analog-output mode without using the ADC and DAC converters or filters, thereby switching them off to reduce power consumption. Table 1 UDA1309H 1. The 256fs mode in which analog-to-digital and digital-to-analog can be used. 2. The 192fs or 384fs mode (digital-to-analog only). Interface mode selection DEVICE PIN ADC/DAC FORMATS MODE 2 MODE 1 MODE 0 TYPE BITS BCK SYS; fsys FIGURE 0 0 0 LSB justified 16 32fs 256fs 3(a) 0 0 1 LSB justified 16 64fs 256fs 3(b) (1) 0 1 0 LSB justified 16 48fs 192fs 4(a) 0 1 1 LSB justified 18 64fs 256fs 3(c) 0 I2S-bus 16 32fs 256fs 3(d) 1 0 1 0 1 I2S-bus 16 64fs 256fs 3(e) 1 1 0 I2S-bus 16 48fs 384fs(1) 4(b) 1 I2S-bus 18 64fs 256fs 3(f) 1 1 Note 1. Only digital-to-analog. Table 2 Clock edge mode VALID EDGE OF BCK CLKEDGE 1998 Jan 06 ADC DAC 0 falling rising 1 rising falling 7 Philips Semiconductors Product specification Low-power stereo bitstream ADC/DAC UDA1309H LSB JUSTIFIED 32fs 16-BIT handbook, full pagewidth BCK WS RIGHT LEFT SDA LSB MSB LSB MSB LSB MSB (a) LSB JUSTIFIED 64fs 16-BIT BCK WS RIGHT LEFT SDA LSB MSB LSB MSB LSB (b) LSB JUSTIFIED 64fs 18-BIT BCK WS RIGHT LEFT SDA LSB MSB LSB LSB MSB (c) I2S 32fs 16-BIT BCK LEFT WS RIGHT SDA LSB MSB LSB MSB LSB (d) I2S 64fs 16-BIT BCK LEFT WS RIGHT SDA MSB MSB LSB LSB MSB (e) I2S 64fs 18-BIT BCK LEFT WS RIGHT SDA MSB MSB LSB (f) Fig.3 DAC and ADC data formats (continued in Fig.4). 1998 Jan 06 8 LSB MSB MGE767 Philips Semiconductors Product specification Low-power stereo bitstream ADC/DAC UDA1309H LSB JUSTIFIED 48fs 16-BIT handbook, full pagewidth BCK WS RIGHT LEFT SDA LSB MSB LSB MSB LSB (a) I2S 48fs 16-BIT BCK LEFT WS RIGHT SDA MSB LSB MSB LSB MSB MGE768 (b) Fig.4 DAC and ADC data formats (continued from Fig.3). There are different modes in which the UDA1309H can operate. These modes can be selected as shown in Table 3 and Fig.5. In mode a, the digital filters clock is switched off. Switching over to one of the ADC active modes (b, c or d) initiates a reset sequence of the digital filters. This mode should be activated immediately after power-on for at least 2 clock periods. Table 3 Operating mode selection DEVICE PIN LOGIC MODE DESCRIPTION ANLPTR ADPON DAPON a not used 0 0 0 b record and playback 0 1 1 c record only 0 1 0 d record and analog loop-through 1 1 0 e analog loop-through 1 0 0 f playback only 0 0 1 1 X(1) 1 g and h reserved Note 1. X = don’t care. 1998 Jan 06 9 Philips Semiconductors Product specification Low-power stereo bitstream ADC/DAC handbook, full pagewidth MODE b analog input ADC ANALOG UDA1309H DAC DIGITAL FILTER ADC DIGITAL FILTER digital output analog output digital input MODE c analog input ADC ANALOG ADC DIGITAL FILTER digital output MODE d analog input ADC ANALOG ADC DIGITAL FILTER digital output MODE e analog input MODE f DAC ANALOG analog output analog output DAC DIGITAL FILTER digital input DAC ANALOG analog output MGE771 Fig.5 Schematic diagram of operating modes. 1998 Jan 06 10 Philips Semiconductors Product specification Low-power stereo bitstream ADC/DAC UDA1309H LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDDA(AD) analog supply voltage (pin 8) − 6.5 V VDDA(DA) analog supply voltage (pin 25) − 6.5 V VDDO operational amplifiers supply voltage (pin 19) − 6.5 V VDDD digital supply voltage (pin 28) − 6.5 V VDDD(F) digital filters supply voltage (pin 34) − 6.5 V ∆VDD maximum supply voltage difference − 100 mV ∆VSS maximum ground supply voltage difference − 100 mV VI maximum input voltage −0.5 VDD + 0.5 V IIK DC clamp input diode current VI < −0.5 V or VI > VDD + 0.5 V − ±10 mA IOK DC output clamp diode current; (output type 2 mA) VO < −0.5 V or VO > VDD + 0.5 V − ±10 mA Tstg storage temperature −65 +150 °C Tamb operating ambient temperature −20 +75 °C Ves electrostatic handling note 1 −1500 +1500 V note 2 −300 +300 V Notes 1. Human body model: C = 100 pF; R = 1.5 kΩ; 3 zaps positive and 3 zaps negative. 2. Machine model: C = 200 pF; L = 0.5 µH; R = 10 Ω; 3 zaps positive and 3 zaps negative. THERMAL CHARACTERISTICS SYMBOL Rth j-a PARAMETER thermal resistance from junction to ambient in free air VALUE UNIT 60 K/W QUALITY SPECIFICATION In accordance with “SNW-FQ-611E”. The number of this quality specification can be found in the “Quality Reference Handbook”. The handbook can be ordered using the code 9397 750 00192. 1998 Jan 06 11 Philips Semiconductors Product specification Low-power stereo bitstream ADC/DAC UDA1309H CHARACTERISTICS VDDD = VDDA = VDDO = VDDD(F) = 5 V; VSSD = VSSA = VSSO = VSSD(F) = 0 V; Tamb = 25 °C; full scale sine wave input; mode 1; fi = 1 kHz; 16-bit input data; conversion rate = 44.1 kHz; measurement bandwidth = 10 Hz to 20 kHz; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supply VDDA(AD) ADC analog supply voltage (pin 8) 4.5 5.0 5.5 V VDDA(DA) DAC analog supply voltage (pin 25) 4.5 5.0 5.5 V VDDO operational amplifiers supply voltage (pin 19) 4.5 5.0 5.5 V VDDD ADC/DAC digital supply voltage (pin 28) 4.5 5.0 5.5 V VDDD(F) digital filters supply voltage (pin 34) 4.5 5.0 5.5 V IDDA(AD) ADC analog supply current (pin 8) − 9 13.5 mA ADC power-down − 0.8 1.2 mA DAC analog supply current (pin 25) − 4.5 6.8 mA DAC power-down − 1.1 2.0 mA − 14 21 mA DAC power-down − 5.5 8.3 mA ADC power-down − 7.5 11.3 mA ADC/DAC power-down − 0 − mA IDDA(DA) IDDO operational amplifiers supply current (pin 19) IDDD ADC/DAC digital supply current (pin 28) − 0.2 0.5 mA IDDD(F) digital filters supply current (pin 34) − 24 36 mA DAC power-down − 17 26 mA ADC power-down − 8 12 mA − − 100 µA IDDD(F)q 1998 Jan 06 digital filters quiescent current 12 Philips Semiconductors Product specification Low-power stereo bitstream ADC/DAC SYMBOL PARAMETER UDA1309H CONDITIONS MIN. TYP. MAX. UNIT Analog-to-digital converter VI(rms) input voltage (RMS value) 0.9 1.0 1.1 V II input current (pins 13 and 14) − − 10 nA ∆VO unbalance between channels − − tbf dB RES resolution (THD + N)/S total harmonic distortion plus noise-to-signal ratio note 1 16-bit format − 16 − bits 18-bit format − 18 − bits at 0 dB − −85 tbf dB at −20 dB − −75 − dB at −60 dB; A-weighted − −35 −30 dB Vi = 0 V; A-weighted tbf 95 − dB S/N idle channel signal-to-noise ratio αcs channel separation − 90 − dB PSRR power supply rejection ratio note 2 − −30 − dB 0.9 1.0 1.1 V Digital-to-analog converter VO(rms) output voltage (RMS value) ∆VO unbalance between channels − 0.1 − dB RL load resistance 5 − − kΩ CL load capacitance note 4 − − 200 pF RES resolution 16-bit format − 16 − bits 18-bit format − 18 − bits at 0 dB − −90 −82 dB at −20 dB − −75 − dB at −60 dB; A-weighted − −38 −34 dB at −60 dB; A-weighted; note 5 − −44 − dB code 0000H; A-weighted − 104 − dB (THD + N)/S total harmonic distortion plus noise-to-signal ratio note 3 S/N idle channel signal-to-noise ratio αcs channel separation 90 100 − dB PSRR power supply rejection ratio note 2 − −30 − dB Analog loop-through (mode e) (THD + N)/S total harmonic distortion plus noise-to-signal ratio at 0 dB − −85 − dB S/N idle channel signal-to-noise ratio VI = 0 V; A-weighted − 95 − dB Gltr loop-through gain note 1 − −1.1 − dB Eos DC offset error − 1.0 − mV 1998 Jan 06 13 Philips Semiconductors Product specification Low-power stereo bitstream ADC/DAC SYMBOL PARAMETER UDA1309H CONDITIONS MIN. TYP. MAX. UNIT Analog-to-digital decimation filter fs(o) output sample frequency 28 44.1 54 fs(i) input sample frequency − 128fs − fsys system clock frequency 256fs − 256fs kHz B signal bandwidth fs(o) = 44.1 kHz 0.02 − 20 kHz Asup aliasing suppression fs(o) − B < fi < 2fs(o) − B; note 6 60 − − dB fi > 2fs(o) − B; note 6 80 − − dB α frequency response fi = 20 Hz to 20 kHz −0.2 − +0.2 dB OLdet overload detection level note 7 − 0 − dB Digital-to-analog interpolation filter fs(o) output sample frequency − 64fs − fs(i) input sample frequency 28 44.1 54 fsys system clock frequency 256fs − 256fs B signal bandwidth fs(i) = 44.1 kHz 0.02 − 20 kHz α frequency response fi = 20 Hz to 20 kHz −0.2 − +0.2 dB SUP out-of-band suppression 40 50 − dB −0.5 − 0.3VDDD V kHz Digital part; note 8 INPUTS (PINS 1 TO 4, 6, 29 TO 32, 35 TO 38, 40 AND 42 TO 44) VIL LOW level input voltage IIL LOW level input current VI = VSSD − − 10 µA IIH HIGH level input current VI = VDDD − − 10 µA CI(max) maximum input capacitance − − 10 pF 0.7VDDD − VDDD + 0.5 V INPUT (PINS 1 TO 4, 6, 29 TO 32, 35 TO 38, 40 AND 42 TO 44) VIH HIGH level input voltage OUTPUTS (PINS 5 AND 41) VOL LOW level output voltage IOL = 2 mA − − 0.5 V VOH HIGH level output voltage IOH = −2 mA VDDD − 0.5 − − V IOZ 3-state leakage current VO = VDDD or VSSD − − 10 µA 1998 Jan 06 14 Philips Semiconductors Product specification Low-power stereo bitstream ADC/DAC SYMBOL PARAMETER UDA1309H CONDITIONS MIN. TYP. MAX. UNIT Timing BIT CLOCK (BCK) RELATED SIGNALS (see Fig.6); CLKEDGE = 0 Tcy clock period 300 − − ns tHC clock HIGH time 100 − − ns tLC clock LOW time 100 − − ns tr rise time − − 20 ns tf fall time − − 20 ns tsuWS set-up time WS to rising edge of BCK 20 − − ns thWS hold time WS to rising edge of BCK 0 − − ns tsuDA set-up time SDA (DAC) to rising edge of BCK 20 − − ns thDA hold time SDA (DAC) to rising edge of BCK 0 − − ns thAD hold time SDA (ADC) to falling edge of BCK 0 − − ns tdAD delay time SDA (ADC) to falling edge of BCK − − 80 ns SYSTEM CLOCK (SYSCLK) RELATED SIGNALS (see Fig.7) Tcy clock period 72 − − ns tHC clock HIGH time 22 − − ns tLC clock LOW time 22 − − ns tr rise time − − 10 ns tf fall time − − 10 ns Notes 1. VI for full scale digital output is a function of VDDA(AD) [1.0 V (RMS) at VDDA(AD) = 5.0 V is equivalent to −1.0 dB in the digital domain]. 2. Vripple = 1% of the supply voltage and fripple = 100 Hz. 3. At full scale digital input; no de-emphasis; VO(rms) is a function of VDDA(DA). 4. For a load capacitance greater than 33 pF a series resistor of 200 Ω is recommended. 5. 18 bits input data. 6. The aliasing suppression frequency is mirrored around 128fs. 7. VDDA = 5 V; indicated digital level is with respect to −1.0 dB (no overload). 8. All digital voltages = 4.5 to 5.5 V; all ground supply voltages = 0 V; Tamb = −20 to +75 °C. 1998 Jan 06 15 Philips Semiconductors Product specification Low-power stereo bitstream ADC/DAC UDA1309H Tcy handbook, full pagewidth tLC tHC CLKEDGE = 1 VH BCK VL CLKEDGE = 0 tr tf tsuWS thWS tsuDA thDA WS (LRCK) SDA (DAC) tdAD thAD SDA (ADC) MGE769 Fig.6 Serial timing of BCK related signals. 1998 Jan 06 16 Philips Semiconductors Product specification Low-power stereo bitstream ADC/DAC UDA1309H Tcy handbook, full pagewidth tHC tLC SYSCLK tr tf MGE770 Fig.7 Serial timing of SYSCLK related signals. 1998 Jan 06 17 Philips Semiconductors Product specification Low-power stereo bitstream ADC/DAC UDA1309H PACKAGE OUTLINE QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm SOT307-2 c y X A 33 23 34 22 ZE e E HE A A2 wM (A 3) A1 θ bp Lp pin 1 index L 12 44 1 detail X 11 wM bp e ZD v M A D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y mm 2.10 0.25 0.05 1.85 1.65 0.25 0.40 0.20 0.25 0.14 10.1 9.9 10.1 9.9 0.8 12.9 12.3 12.9 12.3 1.3 0.95 0.55 0.15 0.15 0.1 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 θ o 10 0o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 95-02-04 97-08-01 SOT307-2 1998 Jan 06 EUROPEAN PROJECTION 18 Philips Semiconductors Product specification Low-power stereo bitstream ADC/DAC If wave soldering cannot be avoided, for QFP packages with a pitch (e) larger than 0.5 mm, the following conditions must be observed: SOLDERING Introduction • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. • The footprint must be at an angle of 45° to the board direction and must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). Reflow soldering Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. Reflow soldering techniques are suitable for all QFP packages. The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our “Quality Reference Handbook” (order code 9397 750 00192). A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 50 and 300 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 °C. Wave soldering Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. CAUTION Wave soldering is NOT applicable for all QFP packages with a pitch (e) equal or less than 0.5 mm. 1998 Jan 06 UDA1309H 19 Philips Semiconductors Product specification Low-power stereo bitstream ADC/DAC UDA1309H DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1998 Jan 06 20 Philips Semiconductors Product specification Low-power stereo bitstream ADC/DAC NOTES 1998 Jan 06 21 UDA1309H Philips Semiconductors Product specification Low-power stereo bitstream ADC/DAC NOTES 1998 Jan 06 22 UDA1309H Philips Semiconductors Product specification Low-power stereo bitstream ADC/DAC NOTES 1998 Jan 06 23 UDA1309H Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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No. 5, 80640 GÜLTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777 For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 Internet: http://www.semiconductors.philips.com © Philips Electronics N.V. 1998 SCA57 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 547027/1200/02/pp24 Date of release: 1998 Jan 06 Document order number: 9397 750 03167