STMICROELECTRONICS TDA9112A

TDA9112A
HIGH-END I²C CONTROLLED DEFLECTION PROCESSOR
FOR MULTISYNC MONITOR
FEATURES
General
• Advanced I2C-bus controlled deflection
processor dedicated for high-end CRT monitors
• Single supply voltage 12V
• Very low jitter
• DC/DC converter controller
• Advanced EW drive
• Advanced asymmetry corrections
• Automatic multistandard synchronization
• 2 dynamic correction waveform outputs
• X-ray protection and Soft-start & stop on
horizontal and DC/DC drive outputs
• I2C-bus status register
Horizontal section
• 150 kHz maximum frequency
• Corrections of geometric asymmetry: Pin
cushion asymmetry, Parallelogram, separate
Top/Bottom corner asymmetry
• Tracking of asymmetry corrections with vertical
size and position
• Fully integrated horizontal moiré cancellation
Vertical section
• 200 Hz maximum frequency
• Vertical ramp for DC-coupled output stage with
adjustments of: C-correction, S-correction for
super-flat CRT, Vertical size, Vertical position
• Vertical size and position prescales for factory
adjustment
• Vertical moiré cancellation through vertical
ramp waveform
• Compensation of vertical breathing with EHT
variation; I2C-bus gain adjustment
EW section
• Symmetrical geometry corrections: Pin cushion,
Keystone, Top/Bottom corners separately, Sand W-corrections
• Horizontal size adjustment
• Tracking of EW waveform with Vertical size and
position, horizontal size and frequency
• Compensation of horizontal breathing with EHT
variation, I2C-bus gain adjustment
Dynamic correction section
• Generates waveforms for dynamic corrections
like focus, brightness uniformity, ...
• 1 output with vertical dynamic correction
waveform, both polarities, tracking with vertical
size and position
• 1 output with composite HV dynamic correction
waveform, both polarities, shape control on
horizontal waveform component, tracking with
horizontal size
DC/DC controller section
• Step-up and step-down conversion modes
• External sawtooth configuration
• I2C-bus-controlled output voltage
• Synchronized on hor. frequency with phase
selection
• Selectable polarity of drive signal
• Protection at H unlock condition
DESCRIPTION
The TDA9112A is a monolithic integrated circuit
assembled in a 32-pin shrink dual-in-line plastic
package. This IC controls all the functions related
to horizontal and vertical deflection in multimode
or multi-frequency computer display monitors.
Combined with other ST components dedicated
for CRT monitors (microcontroller, video preamplifier, video amplifier, OSD controller), the
TDA9112A allows fully I2C bus-controlled computer display monitors to be built with a reduced
number of external components.
SDIP 32 (Shrink DIP package)
ORDER CODE: TDA9112A
October 2003
This is preliminary information on a new product now in development. Details are subject to change without notice.
1/60
1
Table of Contents
1
PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
PIN FUNCTION REFERENCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4
QUICK REFERENCE DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
6
ELECTRICAL PARAMETERS AND OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . 9
6.1 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
6.2 Supply and Reference voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
6.3 Synchronization inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
6.4 Horizontal section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6.5 Vertical section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6.6 EW drive section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.7 Dynamic correction outputs section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.8 DC/DC controller section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.9 Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7
TYPICAL OUTPUT WAVEFORMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8
I²C-BUS CONTROL REGISTER MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
9
OPERATING DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
9.1 Supply and control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
9.1.1 Power supply and voltage references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
9.1.2 I²C-bus control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
9.2 Synchronization processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
9.2.1 Synchronization signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
9.2.2 Sync. presence detection flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9.2.3 MCU controlled sync. selection mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9.2.4 Automatic sync. selection mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9.3 Horizontal section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
9.3.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
9.3.2 PLL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
9.3.3 Voltage controlled oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
. . . . 36
9.3.4 PLL2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2/60
1
TDA9112A
9.3.5 Dynamic PLL2 phase control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
9.3.6 Output Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
9.3.7 Soft-start and soft-stop on H-drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
9.3.8 Horizontal moiré cancellation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
9.4 Vertical section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
9.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
9.4.2 S and C corrections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
9.4.3 Vertical breathing compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
9.4.4 Vertical after-gain and offset control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
9.4.5 Vertical moiré . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
9.4.6 Biasing of vertical booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
9.5 EW drive section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
9.6 Dynamic correction outputs section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.6.1 Composite horizontal and vertical dynamic correction output HVDyCor . . . . . . . . . 46
9.6.2 Vertical dynamic correction output VDyCor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.7 DC/DC controller section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
9.7.1 Synchronization of DC/DC controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
9.7.2 Soft-start and soft-stop on B-drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
9.8 Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
9.8.1 Safety functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
9.8.2 Composite output HLckVBk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
10 INTERNAL SCHEMATICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
11 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
12 GLOSSARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
3/60
1
TDA9112A
1 PIN CONFIGURATION
H/HVSyn
VSyn
HLckVBk
HOscF
HPLL2C
CO
HGND
RO
HPLL1F
HPosF
HVDyCor
HFly
RefOut
BComp
BRegIn
BISense
4/60
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VDyCor
SDA
SCL
Vcc
BOut
GND
HOut
XRay
EWOut
VOut
VCap
VGND
VAGCCap
VOscF
VEHTIn
HEHTIn
1
HPosF
HPLL1F
7
10
9
H-sync
detection
Polarity
handling
RO CO HOscF
8
Phase/frequency
comparator
6
Horizontal position
PLL1 speed
PLL1
V-blank
H-lock
HPLL2C
12
5
Pin cushion asymm.
Parallelogram
Top corner asymm.
Bottom corner asymm.
Hor. duty cycle
ÕÕÕÕÕ
ÕÕ
3
HFly
Phase comparator
Phase shifter
H duty controller
Horizontal
VCO
Lock detection
HLckVBk
4
H-moiré controller
Õ
31
SCL
30
I²C-bus
interface
HOut
Safety
processor
25
XRay
28
BOut
16
BISense
15
BRegIn
14
BComp
11
HVDyCor
24
EWOut
B+ ref.
I²C-bus control registers
Õ
SDA
26
B+
DC/DC
converter
controller
PLL2
H-moiré amplitude
H-drive
buffer
2 BLOCK DIAGRAM
H/HVSyn
HGND
Õ
: Multiple bit djustments
HV-dynamic correction
Vcc
13
Supply
supervision
V-dynamic
correction
V-sync
extraction
& detection
Reference
generation
HVDyCor V-amplitude
HVDyCor H-amplitude
HVDyCor H-symmetry
HVDyCor H-shape
ÕÕÕÕ
RefOut
(focus,brightness)
29
Tracking
(focus, brightness)
Õ
VDyCor amplitude
EW generator
Internal
ref.
H size
Pin cushion
Keystone
Top corners
Bottom corners
S-correction
W-correction
Breathing gain
ÕÕÕÕÕÕÕÕ
GND
V-ramp control
27
Vertical size & pos.
Prescale size & pos.
S- & C-correction
Vertical moiré
Breathing gain
ÕÕÕÕÕ
V-sync detection
Input selection
Polarity handling
Vertical oscillator
with AGC
21
19
20
VSyn
VGND
VOscF
22
32
VCap VDyCor
VAGCCap
23
18
17
VOut
VEHTIn
HEHTIn
TDA9112A
5/60
TDA9112A
2
TDA9112A
3 PIN FUNCTION REFERENCE
Pin
Name
Function
1
H/HVSyn
TTL compatible Horizontal / Horizontal and Vertical Sync. input
2
VSyn
TTL compatible Vertical Sync. input
3
HLckVBk
Horizontal PLL1 Lock detection and Vertical early Blanking composite output
4
HOscF
High Horizontal Oscillator sawtooth threshold level Filter input
5
HPLL2C
Horizontal PLL2 loop Capacitive filter input
6
CO
Horizontal Oscillator Capacitor input
7
HGND
Horizontal section GrouND
8
RO
Horizontal Oscillator Resistor input
9
HPLL1F
Horizontal PLL1 loop Filter input
10
HPosF
Horizontal Position Filter and soft-start time constant capacitor input
11
HVDyCor
Horizontal and Vertical Dynamic Correction output
12
HFly
Horizontal Flyback input
13
RefOut
Reference voltage Output
14
BComp
B+ DC/DC error amplifier (Compensation) output
15
BRegIn
Regulation feedback Input of the B+ DC/DC converter controller
16
BISense
B+ DC/DC converter current (I) Sense input
17
HEHTIn
Input for compensation of Horizontal amplitude versus EHT variation
18
VEHTIn
Input for compensation of Vertical amplitude versus EHT variation
19
VOscF
Vertical Oscillator sawtooth low threshold Filter (capacitor to be connected to VGND)
20
VAGCCap
Input for storage Capacitor for Automatic Gain Control loop in Vertical oscillator
21
VGND
Vertical section GrouND
22
VCap
Vertical sawtooth generator Capacitor
23
VOut
Vertical deflection drive Output for a DC-coupled output stage
24
EWOut
E/W Output
25
XRay
X-Ray protection input
26
HOut
Horizontal drive Output
27
GND
Main GrouND
28
BOut
B+ DC/DC converter controller Output
29
Vcc
Supply voltage
30
SCL
I²C-bus Serial CLock Input
31
SDA
I²C-bus Serial DAta input/output
32
VDyCor
Vertical Dynamic Correction output
6/60
TDA9112A
4 QUICK REFERENCE DATA
Characteristic
General
Package
Supply voltage
Supply current
Application category
Means of control • Maximum clock frequency
EW drive
DC/DC converter controller
Horizontal section
Frequency range
Autosync frequency ratio (can be enlarged in application)
Positive • Negative polarity of horizontal sync signal • Automatic adaptation
Duty cycle range of the drive signal
Position adjustment range with respect to H period
Soft start • Soft stop feature
Hardware • Software PLL lock indication
Parallelogram
Pin cushion asymmetry correction (also called Side pin balance)
Top • Bottom • Common corner asymmetry correction
Tracking of asymmetry corrections with vertical size & position
Horizontal moiré cancellation (int.) for Combined • Separated architecture
Vertical section
Frequency range
Autosync frequency range (150nF at VCap and 470nF at VAGCCap)
Positive • Negative polarity of vertical sync signal • Automatic adaptation
S-correction • C-correction • Super-flat tube characteristic
Vertical size • Vertical position • Prescale adjustments
Vertical moiré cancellation (internal)
EHT breathing compensation • With I²C-bus gain control
EW section
Pin cushion correction
Keystone correction
Top • Bottom • Common corner correction
S-correction • W-correction
Horizontal size adjustment
Tracking of EW waveform with Frequency • Vertical size & position
EHT breathing compensation • With I²C-bus gain control
Dynamic correction section (dyn. focus, dyn. brightness,...)
Vertical dynamic correction output VDyCor • Positive or negative polarity
Horizontal dynamic correction output HDyCor
Composite HV dynamic correction output HVDyCor • Positive or negative polarity
Shape control on H waveform component of HVDyCor output
Tracking of horizontal waveform component with Horizontal size • EHT
Tracking of vertical waveforms (component) with V. size & position
DC • DC controller section
Step-up • Step-down conversion mode
Internal • External sawtooth configuration
Bus-controlled output voltage • Inhibition at H unlock
Mute • Soft start • Soft stop feature
Positive (N-MOS) • Negative(P-MOS) polarity of BOut signal
Phase selection • Max current selection • Frequency selection
Value
SDIP 32
12
65
High-end
I²C-bus • 400
Yes
Yes
Unit
V
mA
kHz
15 to 150
4.28
Yes • Yes • Yes
30 to 65
±10
Yes • Yes
Yes • Yes
Yes
Yes
Yes • Yes • No
Yes
Yes • Yes
kHz
35 to 200
50 to 180
Yes • Yes • Yes
Yes • Yes • Yes
Yes • Yes • Yes
Yes
Yes • Yes
Hz
Hz
%
%
Yes
Yes
Yes • Yes • No
Yes • Yes
Yes
Yes • Yes
Yes • Yes
Yes • Yes
No
Yes • Yes
Yes
Yes • No
Yes
Yes • Yes
No • Yes
Yes • Yes
Yes • Yes • Yes
Yes • Yes
Yes • Yes • Yes
7/60
TDA9112A
5 ABSOLUTE MAXIMUM RATINGS
All voltages are given with respect to ground.
Currents flowing from the device (sourced) are signed negative. Currents flowing to the device are signed
positive.
Symbol
Value
Min
Max
Unit
VCC
Supply voltage (pin Vcc)
-0.4
13.5
V
V(pin)
Pins HEHTIn, VEHTIn, XRay, HOut, BOut
Pins H/HVSyn, VSyn, SCL, SDA
Pins HLckVBk, CO, RO, HPLL1F, HPosF, HVDyCor, BRegIn,
BISense, VAGCCap, VCap, VDyCor, HOscF, VOscF
Pin HPLL2C
Pin HFly
-0.4
-0.4
-0.4
VCC
5.5
VRefO
V
V
V
-0.4
-0.4
VRefO/2
VRefO
V
V
-2000
2000
V
-40
150
°C
150
°C
VESD
8/60
Parameter
ESD susceptibility
(human body model: discharge of 100pF through 1.5kΩ)
Tstg
Storage temperature
Tj
Junction temperature
TDA9112A
6 ELECTRICAL PARAMETERS AND OPERATING CONDITIONS
Medium (middle) value of an I²C-bus control or adjustment register composed of bits D0, D1,...,Dn is the
one having Dn at "1" and all other bits at "0". Minimum value is the one with all bits at 0, maximum value
is the one with all at "1".
Currents flowing from the device (sourced) are signed negative. Currents flowing to the device are signed
positive.
TH is period of horizontal deflection.
6.1 Thermal data
Symbol
Tamb
Rth(j-a)
Value
Parameter
Min.
Operating ambient temperature
Typ.
Unit
Max.
0
70
Junction-ambience thermal resistance
°C
65
°C/W
6.2 Supply and Reference voltages
Tamb = 25°C
Symbol
Parameter
VCC
Supply voltage at Vcc pin
ICC
Test Conditions
Supply current to Vcc pin
VCC = 12V
VRefO
Reference output voltage at RefOut pin
VCC = 12V, IRefO= -2mA
IRefO
Current capability of RefOut output
Value
Min.
Typ.
Max.
10.8
12
13.2
7.65
7.9
65
-5
Units
V
mA
8.2
V
0
mA
6.3 Synchronization inputs
Vcc = 12V, Tamb = 25°C
Symbol
Parameter
Test Conditions
Value
Min.
VLoH/HVSyn
LOW level voltage on H/HVSyn
0
VHiH/HVSyn
HIGH level voltage on H/HVSyn
2.2
5
V
0
0.8
V
VHiVSyn
HIGH level voltage on VSyn
2.2
RPdSyn
Internal pull-down on H/HVSyn, VSyn
100
H sync. pulse duration on H/HVSyn pin
Proportion of H sync pulse to H period
Pin H/HVSyn
V sync. pulse duration
Pins H/HVSyn, VSyn
Proportion of V sync pulse to V period
Pins H/HVSyn, VSyn
tPulseVSyn
tPulseVSyn /TV
textrV /TH
tHPolDet
175
5
V
250
kΩ
µs
0.5
0.2
0.5
750
µs
0.15
Proportion of H sync pulse length to H pe- Pin H/HVSyn,
riod for extraction as V sync pulse
cap. on pin CO = 820pF
0.21
Polarity detection time (after change)
0.75
Pin H/HVSyn
Units
V
LOW level voltage on VSyn
tPulseHSyn
Max.
0.8
VLoVSyn
tPulseHSyn /TH
Typ.
0.35
ms
9/60
TDA9112A
6.4 Horizontal section
Table 1. Horizontal section
Symbol
Parameter
( Vcc = 12V, Tamb = 25°C)
Test Conditions
Value
Min.
Typ.
Max.
Units
PLL1
IRO
Current load on RO pin
CCO
Capacitance on CO pin
fHO
Frequency of hor. oscillator
fHO(0)
fHOCapt
∆f HO ( 0 )
------------------------f HO( 0) ⋅ ∆T
Free-running frequency of hor. oscill. (1)
RRO=5.23kΩ, CCO=820pF
27
Hor. PLL1 capture frequency (4)
fHO(0) = 28.5kHz
29
Temperature drift of free-running freq. (3)
150
kHz
Average horizontal oscillator sensitivity
fHO(0) = 28.5kHz
H. oscill. control voltage on pin HPLL1F
VRefO=8V
28.5
29.9
kHz
122
kHz
ppm/°C
20.2
1.4
Threshold on H. oscill. control voltage on
VRefO=8V
HPLL1F pin for tracking of EW with freq.
HPOS (Sad01h):
11111111b
10000000b
00000000b
Control voltage on HPosF pin
pF
-150
VHO
VHPosF
mA
390
∆fHO/∆VHO
VHOThrfr
1.5
kHz/V
6.0
V
5.0
V
2.8
3.4
4.0
V
V
V
VHOThrLo
Bottom of hor. oscillator sawtooth(6)
1.6
V
VHOThrHi
Top of hor. oscillator sawtooth(6)
6.4
V
PLL2
RIn(HFly)
IInHFly
VThrHFly
VS(0)
Input impedance on HFly input
V(HFly) >VThrHFly (2)
Current into HFly input
At top of H flyback pulse
Voltage threshold on HFly input
No PLL2 phase modulation
H flyback lock middle point(6)
700
Ω
5
mA
300
500
0.5
0.6
V
4.0
V
Low clamping voltage on HPLL2C
pin(5)
1.6
V
VTopHPLL2C
High clamping voltage on HPLL2C
pin(5)
4.0
V
tph(min) /TH
Min. advance of H-drive OFF before
middle of H flyback(7)
Null asym. correction
0
%
tph(max) /TH
Max. advance of H-drive OFF before
middle of H flyback(8)
Null asym. correction
44
%
VBotHPLL2C
H-drive output on pin HOut
IHOut
tHoff /TH
10/60
Current into HOut output
Output driven LOW
Duty cycle of H-drive signal
fH = 31kHz;
HDUTY (Sad00h):
x1111111b
x0000000b
Soft-start/Soft-stop value
30
27
65
85
mA
%
%
%
TDA9112A
Table 1. Horizontal section
Symbol
( Vcc = 12V, Tamb = 25°C)
Parameter
Test Conditions
Value
Min.
Typ.
Max.
Units
Picture geometry corrections through PLL1 & PLL2
tHph /TH
Hor. VCO phase vs. sync signal (via
PLL1), see Figure 7
HPOS (Sad01h):
11111111b
10000000b
00000000b
+11
0
-11
%
%
%
±0.9
±1.6
±2.6
%
%
%
±1.4
±1.9
±2.4
%
%
%
±0.4
±1.4
±3.5
%
%
%
±0.4
±1.4
±3.5
%
%
%
PCAC (Sad11h) full span
(9)
tPCAC /TH
Contribution of pin cushion asymmetry
correction to phase of H-drive vs. static
phase (via PLL2), measured in corners
VPOS at medium
VSIZE at minimum
VSIZE at medium
VSIZE at maximum
PARAL (Sad12h) full span
(9)
tParalC /TH
Contribution of parallelogram correction
to phase of H-drive vs. static phase (via
PLL2), measured in corners
VPOS at medium
VSIZE at minimum
VSIZE at medium
VSIZE at maximum
TCAC (Sad13h) full span
(9)
tTCAC /TH
Contribution of top corner asymmetry
correction to phase of H-drive vs. static
phase (via PLL2), measured in corners
VPOS at medium
VSIZE at minimum
VSIZE at medium
VSIZE at maximum
BCAC (Sad14h) full span
(9)
tBCAC /TH
Contribution of bottom corner asymmetry
correction to phase of H-drive vs. static VPOS at medium
phase (via PLL2), measured in corners VSIZE at minimum
VSIZE at medium
VSIZE at maximum
Notes about horizontal section
Note 1: Frequency at no sync signal condition. For correct operation, the frequency of the sync signal applied must
always be higher than the free-running frequency. The application must consider the spread of values of real
electrical components in RRO and CCO positions so as to always meet this condition. The formula to calculate
the free-running frequency is fHO(0)=0.122/(RRO CCO)
Note 2: Base of NPN transistor with emitter to ground is internally connected on pin HFly through a series resistance of
about 500Ω and a resistance to ground of about 20kΩ.
Note 3: Evaluated and figured out during the device qualification phase. Informative. Not tested on every single unit.
Note 4: This capture range can be enlarged by external circuitry.
Note 5: The voltage on HPLL2C pin corresponds to immediate phase of leading edge of H-drive signal on HOut pin with
respect to internal horizontal oscillator sawtooth. It must be between the two clamping levels given. Voltage
equal to one of the clamping values indicates a marginal operation of PLL2 or non-locked state.
Note 6: Internal threshold. See Figure 6.
Note 7: The tph(min) parameter is fixed by the application. For correct operation of asymmetry corrections through
dynamic phase modulation, this minimum must be increased by maximum of the total dynamic phase required
in the direction leading to bending of corners to the left. Marginal situation is indicated by reach of VTopHPLL2C
high clamping level by waveform on pin HPLL2C. Also refer to Note 5 and Figure 6.
11/60
TDA9112A
Notes about horizontal section (continued)
Note 8: The tph(max) parameter is fixed by the application. For correct operation of asymmetry corrections through
dynamic phase modulation, this maximum must be reduced by maximum of the total dynamic phase required in
the direction leading to bending of corners to the right. Marginal situation is indicated by reach of VBotHPLL2C
low clamping level by waveform on pin HPLL2C. Also refer to Note 5 and Figure 6.
Note 9: All other dynamic phase corrections of picture asymmetry set to their neutral (medium) positions.
6.5 Vertical section
Table 2. Vertical section (Vcc = 12V, Tamb = 25°C)
Symbol
Parameter
Test Conditions
Value
Min.
Typ.
Max.
Units
AGC-controlled vertical oscillator sawtooth; VRefO = 8V
RL(VAGCCap)
VVOB
VVOTref
Ext. load resistance on
VAGCCap pin(10)
∆Vamp/Vamp(R=∞) ≤1%
Sawtooth bottom voltage on
VCap pin(11)
No load on VOscF pin(11)
65
Sawtooth top voltage internal reference
MΩ
2
V
5
V
5
V
VVOT
Sawtooth top voltage on VCap
pin
tVODis
Sawtooth Discharge time
CVCap=150nF
80
µs
fVO(0)
Free-running frequency
CVCap=150nF
100
Hz
fVOCapt
AGC loop capture frequency
CVCap=150nF
∆VVOdev
-------------------VVOamp
Sawtooth non-linearity(12)(17)
AGC loop stabilized (12)
Frequency drift of sawtooth
amplitude(18)(19)
AGC loop stabilized
fVOCapt(min)≤fVO≤fVOCapt(max)
∆VVOamp
--------------------------------VVOamp ⋅ ∆fVO
AGC loop stabilized
50
185
Hz
0.5
%
200
ppm/Hz
3.5
V
Vertical output drive signal (on pin VOut); VRefO = 8V
Vmidref
Vmid(VOut)
Vamp
VoffVOut
12/60
Internal reference for vertical
sawtooth middle point
Middle point on VOut sawtooth
Amplitude of VOut sawtooth
(peak-to-peak voltage)
VPOS (Sad08h):(22)
x0000000b
x1000000b
x1111111b
VPOF (Sad1Eh):(21)
x0000000b
x1000000b
x1111111b
VSIZE (Sad07h):(23)
x0000000b
x1000000b
x1111111b
VSAG (Sad1Dh):(20)
x0000000b
x1000000b
x1111111b
Level on VOut pin at V-drive "off" I²C-bus bit VOutEn at 0
3.65
3.1
3.45
3.8
3.3
3.3
3.45
3.6
3.5
2.25
3.0
3.75
V
V
V
V
V
V
2.5
V
V
V
2
2.5
3.0
V
V
V
4.0
V
TDA9112A
Table 2. Vertical section (Vcc = 12V, Tamb = 25°C)
Symbol
Parameter
IVOut
Current delivered by VOut output
Test Conditions
Value
Min.
Typ.
-5
Max.
Units
0.25
mA
(13)(20)(21)
VSCor /Vamp
S-correction range
AGC loop stabilized
tVR=1/4 TVR(15)
tVR=3/4 TVR
-4.5
+4.5
%
%
-2.5
0
+2.5
%
%
%
(14)(20)(21)
VCCor /Vamp
C-correction range
VVEHT
Control input voltage range onVEHTIn pin
VVEHTnull
Neutral point on breathing characteristics(16)
∆Vamp
---------------------------------Vamp ⋅ ∆VVEHT
Breathing compensation
AGC loop stabilized
tVR=1/2 TVR(15)
CCOR(Sad0Ah):
x0000000b
x1000000b
x1111111b
1
4
6
V
4.0
V
0
%/V
5
0
-5
%/V
%/V
%/V
VRefO < VVEHT < VCC
VVEHT(min)≤VVEHT≤VVEHT(max):
VEHTG (Sad1Ch):
x0000000b
x1000000b
x1111111b
Notes about vertical section
Note 10: Value of acceptable cumulated parasitic load resistance due to humidity, AGC storage capacitor leakage, etc.,
for less than 1% of Vamp change.
Note 11: The threshold for VVOB is generated internally and routed to VOscF pin. Any DC current on this pin will
influence the value of VVOB.
Note 12: Maximum of deviation from an ideally linear sawtooth ramp at null S-correction (SCOR at 0000000b) and null
C-correction (CCOR at 1000000b). The same rate applies to V-drive signal on VOut pin, no effect on EWOut.
Note 13: Maximum S-correction (SCOR at x1111111b), null C-correction (CCOR at 1000000b).
Note 14: Null S-correction (SCOR at 0000000b).
Note 15: "tVR" is time from the beginning of vertical ramp of V-drive signal on VOut pin. "TVR" is the duration of this ramp,
see Chapter 7 - page 22 and Figure 19.
Note 16: If VVEHT=VVEHTnull or VHEHT=VHEHTnull, respectively, the influence of VVEHT on vertical drive amplitude
or the influence of VHEHT on EW drive signal, respectively, is null.
Note 17: VVOamp = VVOT -VVOB
Note 18: Only the top of the saw tooth drifts. The same rate applies to V-drive signal on VOut pin.
Note 19: Informative, not tested on each unit.
Note 20: VSIZE at medium value 1000000b.
Note 21: VPOS at medium value 1000000b.
Note 22: VPOF at medium value 1000000b.
Note 23: VSAG at maximum value 1111111b.
13/60
TDA9112A
6.6 EW drive section
Table 3. EW drive section (VCC = 12V, Tamb = 25°C)
Symbol
Parameter
Test Conditions
Value
Min.
Typ.
Max.
Units
Output voltage on EWOut pin
1.8
6.5
V
IEWOut
Current delivered by EWOut output
-1.5
0.1
mA
VHEHT
Control voltage range on HEHTIn pin
1
6
V
VHEHTnull
Neutral point on breathing characteristics. See Figure 15.(16)
VEW
4.0
V
2
3.25
4.5
V
V
V
2
V
0
V/V
0
-0.25
0
+0.25
V/V
V/V
V/V
V/V
100
ppm/°C
0
0.75
1.5
V
V
V
0.25
0.5
V
V
(24)(25)(26)(27)(28)(36)(42)(43)
EWTrHFr=0 or VHO >VHO-
VEW-DC
DC component of the EW-drive
signal on EWOut pin(30)
VEW-base
DC reference for the EW-drive
signal on EWOut pin
Thrfr
HSIZE (Sad10h):
00000000b
10000000b
11111111b
(24)(25)(26)(27)(42)(43)
∆VEW –DC
----------------------∆VHEHT
∆VEW –DC
-------------------------------V EW – DC ⋅ ∆T
VRefO < VHEHT < VCC
VHEHT(min)≤VHEHT≤VHEBreathing compensation on DC
HT(max):
component of the EW-drive sigHEHTG (Sad1Bh):
nal(30)
x0000000b
x1000000b
x1111111b
Temperature drift of DC component of the EW-drive signal(30)
(24 )(25)(26)(27 )(28)(36)(42 )(43)
(44 )
(24)(25)(26)(28)(29)(31)
(32)(36)(42)(43)
VEW-PCC
Pin cushion correction component of the EW-drive signal
VSIZE at maximum
PCC (Sad0Ch):
x0000000b
x1000000b
x1111111b
Tracking with VSIZE:
PCC at x1000000b
VSIZE (Sad07h):
x0000000b
x1000000b
(24 )(25 )(26 )(29 )(33 )(35 )(36 )(42 )(43 )
VEW – PCC [ t vr= 0 ]
-------------------------------------------VEW – PCC [ tvr= TVR]
Tracking of PCC component of
the EW-drive signal with vertical
position adjustment
PCC at x1111111b
VPOS (Sad08h):
x0000000b
x1111111b
0.5
2.0
(25 )(26 )(27 )(28 )(29 )(33 )(34 )(36 )(42 )(
43 )
VEW-Key
14/60
Keystone correction component
KEYST (Sad0Dh):
of the EW-drive signal
x0000000b
x1111111b
0.4
-0.4
V
V
TDA9112A
Table 3. EW drive section (VCC = 12V, Tamb = 25°C)
Symbol
Parameter
Test Conditions
Value
Min.
Typ.
Max.
Units
(24 )(26 )(27 )(28 )(29 )(31 )(33 )(36 )(42 )
(43 )
VEW-TCor
Top corner correction component of the EW-drive signal
TCC (Sad0Eh):
x0000000b
x1000000b
x1111111b
-1.4
0
+1.4
V
V
V
-1.4
0
+1.4
V
V
V
-0.3
0
0.3
V
V
V
-0.1
0
0.1
V
V
V
(24 )(25 )(27 )(28 )(29 )(32 )(33 )(36 )(42 )
(43 )
VEW-BCor
Bottom corner correction compo- BCC (Sad0Fh):
nent of the EW-drive signal
x0000000b
x1000000b
x1111111b
(24 )(25 )(26 )(27 )(28 )(29 )(33 )(36 )(41 )
(43 )
VEW-S
Pin Cushion S correction compo- EWSC (Sad19h):
nent of EW-drive signal
x0000000b
x1000000b
x1111111b
(24 )(25 )(26 )(27 )(28 )(29 )(33 )(36 )(41 )
(42 )
VEW-W
Pin Cushion W correction component of EW-drive signal
EWWC (Sad1Ah):
x0000000b
x1000000b
x1111111b
∆VEW –AC
----------------------------------------------------V EW–AC [ fmax ] ⋅ ∆VHO
Tracking of AC component of
EW-drive signal with horizontal
frequency(37)(38)(39)
I²C bit EWTrHFr=1
VHO>VHOThrfr
VHO(min)≤VHO≤VHOThrfr
0
20
%/V
%/V
∆VEW –DC
---------------------------------------------------VEW–DC [span] ⋅ ∆V HO
Tracking of DC component of
EW-drive signal with horizontal
frequency(30)(38)(39)
I²C bit EWTrHFr=1
VHO>VHOThrfr
VHO(min)≤VHO≤VHOThrfr
0
20
%/V
%/V
VEW–AC
-------------------------------------------------VEW – AC [ HSIZE max ]
Tracking of AC component of
EW-drive signal with horizontal
size(37)
I²C bit EWTrHSize=1
HSIZE (Sad10h):
00000000b
10000000b
11111111b
138
119
100
%
%
%
0
%/V
3.5
0
-3.5
%/V
%/V
%/V
∆VEW – AC
-----------------------------------------VEW – A C ⋅ ∆VHEHT
VRefO < VHEHT < VCC
VHEHT(min)≤VHEHT≤VHEHT(max):
Breathing compensation on AC
component of the EW-drive sig- HEHTG (Sad1Bh):
0000000b
nal(37)
1000000b
1111111b
15/60
TDA9112A
Notes about EW drive section
Note 24: KEYST at medium (neutral) value.
Note 25: TCC at medium (neutral) value.
Note 26: BCC at medium (neutral) value.
Note 27: PCC at minimum value.
Note 28: VPOS at medium (neutral) value.
Note 29: HSIZE I²C field at maximum value.
Note 30: VEW-DC is defined as voltage at tVR=1/2 TVR.
Note 31: Defined as difference of (voltage at tVR=0) minus (voltage at tVR=1/2 TVR).
Note 32: Defined as difference of (voltage at tVR=TVR) minus (voltage at tVR=1/2 TVR).
Note 33: VSIZE at maximum value.
Note 34: Difference (voltage at tVR=0) minus (voltage at tVR=TVR).
Note 35: Ratio "A/B"of parabola component voltage at tVR=0 versus parabola component voltage at tVR=TVR.
See Figure 2.
Note 36: VHEHT>VRefO, VVEHT>VRefO
Note 37: VEW-AC is defined as overall peak-to-peak value between tVR=0 and tVR=TVR of all components other than
VEW-DC (contribution of PCC, keystone correction, corner corrections and S- and W-corrections).
Note 38: More precisely tracking with voltage on HPLL1F pin which itself depends on frequency at a rate given by
external components on PLL1 pins
Note 39: VEW-DC[span] = VEW-DC[VHO>VHOThrfr] - VEW-DC[HSIZE=0000000b].
VEW-AC[fmax] = VEW-AC[VHO>VHOThrfr].
Note 40: Defined as difference of (voltage at tVR=1/4 TVR) minus (voltage at tVR=3/4 TVR).
Note 41: Defined as difference of (voltage at tVR=1/2 TVR) minus (voltage at tVR=1/4 TVR).
Note 42: EWSC at medium (neutral) value.
Note 43: EWWC at medium (neutral) value.
Note 44: Informative, not tested on each unit.
16/60
TDA9112A
6.7 Dynamic correction outputs section
Table 4. Dynamic correction outputs section
Symbol
Parameter
(VCC = 12V, Tamb = 25°C)
Test Conditions
Value
Min.
Typ.
Max.
Units
Composite Horizontal and Vertical Dynamic Correction output HVDyCor
IHVDyCor
Current delivered by HVDyCor
output
VHVD-DC
DC component of the drive signal
on HVDyCor output
∆VHVD – DC
-------------------------------------------VHVD – DC ⋅ ∆T
-2
HVDyCorPol = 0
HVDyCorPol = 1
Temperature drift of DC component (19)
of the drive signal on HVDyCor
TBD
TBD
2.1
7.30
1
mA
TBD
TBD
V
V
200
ppm/°C
4.8
1.8
1
V
V
V
4.5
1.5
1
V
V
V
(45)(46)
Amplitude of H-component of the
drive signal on HVDyCor output
VHVD-H
HDyCorTr = 0
HVDC-HSHAP = min
HVDC-HAMP (Sad04h):
x0000000b
x1000000b
x1111111b
HVDC-HSHAP = max
HVDC-HAMP (Sad04h):
x0000000b
x1000000b
x1111111b
(53)
Power index of the H-component of
the drive signal on HVDyCor output
SHVDC-HSHAP
[
]
VHVD– H TrHSOn
--------------------------------------------------------------VHVD –H [TrHSOff]
tHVD-Hoffset /TH
tHVD-Hflat
HVDC-HSHAP (Sad18h)
x0000000b
x1000000b
x1111111b
HSIZE (Sad10h):
Impact of horizontal size adjustment on HVDyCor H-parabola com- 00000000b
11111111b
ponent (tracking) (47)
Offset (phase) of H-parabola component of the drive signal on
HVDyCor output (50)
HVDC-HPH (Sad05h):
x0000000b
x1000000b (51)
x1111111b
fHO=31kHz
Duration of the flat part at the start HDCFlatEn = 0 or/and
HDyCorPh = 0
of H-parabola component of the
drive signal on HVDyCor output (50) HDCFlatEn = 1
HDyCorPh = 1
2
2.8
4
(48)
1
+24.5
0
-24.5
%
%
%
850
ns
(54)
(28)
VHVD-V
VSIZE at x1000000b
HVDC-VAMP (Sad06h):
x0000000b
Amplitude of V-parabola compox1000000b
nent of the drive signal on HVDyCor
x1111111b
output
HVDC-VAMP at max.:
VSIZE (Sad07h):
x0000000b
x1111111b
0
0.6
1.2
V
V
V
0.7
1.9
V
V
17/60
TDA9112A
Table 4. Dynamic correction outputs section
Symbol
VHVD – V [tV R= 0]
-----------------------------------------------------------VHVD – V[tVR= TVR ]
Parameter
(VCC = 12V, Tamb = 25°C)
Test Conditions
Value
Min.
HVDC-VAMP at max.:
Tracking of V-parabola component
VPOS (Sad08h):
of the drive signal on HVDyCor outx0000000b
(49)
put with vertical position
x1111111b
Typ.
Max.
Units
0.5
2.0
Vertical Dynamic Correction output VDyCor
IVDyCor
Current delivered by VDyCor output
VVD-DC
DC component of the drive signal
on VDyCor output
-1.5
RL(VDyCor)=10kΩ
0.1
mA
4
V
0
0.5
1
V
V
V
0.6
1.6
V
V
(28)
VVD-V
VVD – V [t VR= 0]
------------------------------------------------------VVD – V [t VR= TVR]
VSIZE at medium
VDC-AMP (Sad15h):
x0000000b
Amplitude of V-parabola on VDyCor x1000000b
output(52)
x1111111b
VDC-AMP at maximum
VSIZE (Sad07h):
x0000000b
x1111111b
VDC-AMP at maximum
Tracking of V-parabola on VDyCor VPOS (Sad08h):
x0000000b
output with vertical position (49)
x1111111b
0.5
2.0
Notes about dynamic output section
Note 45: HVDC-VAMP at minimum.
Note 46: HVDC-HPH at medium.
Note 47: Ratio of the amplitude at HDyCorTr=1 to the amplitude at HDyCorTr=0 (refer to chapter "I²C-bus control
register map") as a quadratic function of horizontal size adjustment.
Note 48: (1.38)SHVDC-HSHAP
Note 49: Ratio "A/B"of vertical parabola component voltage at tVR=0 versus vertical parabola component voltage at
tVR=TVR.
Note 50: Refer to Figure 16.
Note 51: Taken for reference at given position of HDyCorPh flag.
Note 52: Unsigned value. Polarity selection by VDyCorPol I²C-bus bit. Refer to section I²C-bus control register map.
Note 53: Value gives the shape characteristics of the H-component. Refer to Figure 17.
Note 54: The flat part begins at the start of fly-back and ends at the same moment as for combination HDCFlatEn = 0,
HDyCorPh = 1. Refer to Figure 16.
18/60
TDA9112A
6.8 DC/DC controller section
Table 5. DC/DC controller section
Symbol
Parameter
(VCC = 12V, Tamb = 25°C)
Test Conditions
RB+FB
Ext. resistance applied between
BComp output and BRegIn input
AOLG
Open loop gain of error amplifier on
BRegIn input
Low frequency(19)
fUGBW
Unity gain bandwidth of error amplifier
on BRegIn input
(19)
IRI
IBComp
ABISense
VThrBIsCurr
IBISense
Min.
Output current capability of BOut output
100
dB
6
MHz
µA
2.0
0.5
mA
mA
3
ThrBlsense = 0
ThrBlsense = 1
TBD
TBD
Bias current delivered by BISense
IBOut
Units
kΩ
-0.5
Voltage gain on BISense input
Conduction time of the power transistor
Max.
-0.2
Output current capability of BComp out- BOut enabled
put.
BOut disabled(55)
Threshold voltage on BISense input
corresponding to current limitation
Typ.
5
Bias current delivered by BRegIn
tBOn
VBOSat
Value
2.1
1.2
V
µA
-1
TH - 300ns
0
Saturation voltage of the internal output
IBOut=10mA
transistor on BOut
VBReg
Regulation reference for BRegIn voltage(56)
VRefO=8V
BREF (Sad03h):
x0000000b
x1000000b
x1111111b
tBTrigDel /TH
Delay of BOut “Off-to-On” edge after
middle of flyback pulse (57)
BOutPh = 0 and BOHEdge = 0
10
mA
0.25
V
3.8
4.9
6.0
V
V
V
16
%
Note 55: A current sink is provided by the BComp output while BOut is disabled.
Note 56: Internal reference related to VRefO. The same values to be found on pin BRegIn, while regulation loop is
stabilized.
Note 57: Only applies to configuration specified in "Test conditions" column, i.e. synchronization of BOut “Off-to-On”
edge with horizontal fly-back signal. Refer to chapter "DC/DC controller" for more details.
19/60
TDA9112A
6.9 Miscellaneous
Table 6. Miscellaneous
Symbol
(VCC = 12V, Tamb = 25°C)
Parameter
Test Conditions
Value
Min.
Typ.
Max.
Units
Vertical blanking and horizontal lock indication composite output HLckVBk
ISinkLckBk
VOLckBk
Sink current to HLckVBk pin
Output voltage on HLckVBk output
(58)
V. blank
No
Yes
No
Yes
H. lock
Yes
Yes
No
No
100
µA
0.1
1.1
5
6
V
V
V
V
0
0.02
%
%
0
0.04
%
%
0
3
mV
mV
Horizontal moiré canceller
∆TH ( H – moire)
----------------------------TH
Modulation of TH by H. moiré function
HMoiréMode = 0
HMOIRE (Sad02h):
x0000000b
x1111111b
HMoiréMode = 1
HMOIRE (Sad02h):
x0000000b
x1111111b
Vertical moiré canceller
VV-moiré
Amplitude of modulation of V-drive signal on VOut pin by vertical moiré.
VMOIRE (Sad0Bh):
x0000000b
x1111111b
Protection functions
VRefO
VRefO
VRefO
-10mV
+10mV
VThrXRay
Input threshold on XRay input(59)
tXRayDelay
Delay time between XRay detection
event and protection action
VCCXRayEn
Minimum VCC value for operation of
XRay detection and protection(62)
10.2
VCCEn
VCC value for start of operation at VCC
ramp-up(60)
8.0
V
VCCDis
VCC value for stop of operation at VCC
ramp-down(60)
6.8
V
2TH
TH
10.8
V
Control voltages on HPosF pin and VCC for Soft start/stop operation(19)(61)
VHOn
Threshold for start/stop of H-drive signal
1
V
VBOn
Threshold for start/stop of B-drive signal
1.7
V
VHBNorm
Threshold for full operation duty cycle
of H-drive and B-drive signals
2.4
VCCStop
Minimum supply voltage when voltage
on HPosF pin reaches VHOn threshold(63)
4.8
20/60
TDA9112A
Notes about Miscellaneous section
Note 58: Current sunk by the pin if the external voltage is higher than one the circuit tries to force.
Note 59: See VRefO in Section 6.2.
Note 60: In the regions of VCC where the device’s operation is disabled, the H-drive, V-drive and B+-drive signals on
HOut, VOut and BOut pins, resp., are inhibited, the I²C-bus does not accept any data and the XRayAlarm flag
is reset. Also see Figure 10.
Note 61: See Figure 10.
Note 62: When VCC is below VCCXRayEn XRay detection and protection are disabled.
Note 63: Minimum momentary supply voltage to ensure a correct performance of Soft stop function at VCC fall down is
defined at the moment when the voltage on HPosF pin reaches VHOn threshold.
21/60
TDA9112A
7 TYPICAL OUTPUT WAVEFORMS
Table 7. Typical output waveforms - Note 64
Function
Vertical Size
Vertical Size
After Gain
Vertical
Position
Sad
07
1D
08
Pin
Byte
x0000000
Vamp
x1111111
Vamp
x0000000
Vamp
x1111111
Vamp
1E
Vmid(VOut)
VOut
(23)
VOut
(23)
Vmid(VOut)
Vmidr
Vmid(VOut)
x1000000
Vmidr
Vmid(VOut)
Vmid(VOut)
Vmidr
x0000000
Vmidr
Vmid(VOut)
x1000000
Vmidr
Vmid(VOut)
Vmid(VOut)
Vmidr
Vamp
0
VOut
(23)
½TVR
TVR t
VR
VSCor
x1111111:
Max.
Vamp
0
22/60
Vmid(VOut)
x0000000
x0000000:
Null
09
Vmid(VOut)
VOut
(23)
x1111111
S-correction
Effect on Screen
VOut
(23)
x1111111
Vertical
Position
Offset
Waveform
¼TVR
¾TVR TVR
tVR
TDA9112A
Table 7. Typical output waveforms - Note 64
Function
Sad
Pin
Byte
Waveform
Effect on Screen
Vamp
VCCor
x0000000
0
C-correction
0A
VOut
(23)
x1000000 :
Null
½TVR
TVR
½TVR
TVR t
VR
tVR
Vamp
0
Vamp
VCCor
x1111111
0
½TVR
TVR
tVR
x0000000:Vamp
Null
Vertical moiré
amplitude
0B
(n-1)TV
VOut
(23)
(n+1)TV
nTV
t
VV-moiré
x1111111:Vamp
Max.
(n-1)TV
00000000
10h
½TVR
TVR t
VR
½TVR
TVR t
VR
EWOut
(24)
11111111
t
VEW-DC
0
Horizontal size
(n+1)TV
nTV
VEW-DC
0
VEW-DC
VEW-Key
x0000000
Keystone
correction
0D
0
EWOut
(24)
VEW-Key
x1111111
½TVR
TVR t
VR
VEW-DC
VEW-PCC
x0000000
Pin cushion
correction
0C
0
EWOut
(24)
½TVR
TVR t
VR
VEW-PCC
x1111111
0
½TVR
TVR
tVR
23/60
TDA9112A
Table 7. Typical output waveforms - Note 64
Function
Sad
Pin
Byte
Waveform
Effect on Screen
VEW-TCor
x1111111
Top corner
correction
0E
0
EWOut
(24)
½TVR
TVR t
VR
VEW-TCor
x0000000
0
½TVR
TVR
tVR
VEW-BCor
x1111111
Bottom corner
correction
0F
0
EWOut
(24)
½TVR
TVR t
VR
VEW-BCor
x0000000
x1111111
Pin Cushion
S-correction
19
½TVR
TVR
0
½TVR
TVR tVR
0
½TVR
tVR
VEW-S
EWOut
(24)
x0000000
0
EW-S
TVR
tVR
EW-W
x1111111
Pin Cushion
W-correction
1A
EWOut
(24)
0
½TVR
0
½TVR
TVR tVR
x0000000 EW-W
tParalC
TVR
tVR
static H-phase
x0000000
12h
0
Internal
Parallelogram
correction
static H-phase
0
x0000000
½TVR
½TVR
PCAC
TVR t
VR
static
H-phase
x1111111
0
24/60
TVR t
VR
static
H-phase
PCAC
0
Internal
11h
TVR t
VR
tParalC
x1111111
Pin cushion
asymmetry
correction
½TVR
½TVR
TVR t
VR
TDA9112A
Table 7. Typical output waveforms - Note 64
Function
Sad
Pin
Byte
Waveform
tTCAC
static
H-phase
x0000000
13h
0
Internal
Top corner
asymmetry
correction
Effect on Screen
½TVR
TVR t
VR
static
H-phase
x1111111 tTCAC
0
½TVR
TVR t
VR
tBCAC
static
H-phase
Bottom corner
asymmetry
correction
14h
Internal
x0000000
0
x1111111
½TVR
static
H-phase
tBCAC
0
TVR t
VR
½TVR
TVR t
VR
VDyCorPol=0
VVD-V
VVD-DC
01111111
0
Vertical
dynamic
correction
amplitude
15h
VDyCor
(32)
½TVR
VVD-V
TVR t
VR
VVD-DC
x0000000
0
½TVR
TVR
Application dependent
tVR
VDyCorPol=1
11111111
VVD-D
VVD-V
0
x0000000
HVDyCor
vertical
amplitude
06
VHVD-V
0
HVDyCor
(11)
½TVR
TVR t
VR
VHVD½TVR
TVR
tVR
Application dependent
HVDyCorPol=0
VHVD-V
x1111111
VHVD0
½TVR
TVR
tVR
25/60
TDA9112A
Table 7. Typical output waveforms - Note 64
Function
Sad
Pin
Byte
Waveform
Effect on Screen
VHVD-
VHVD-V
x0000000
HVDyCor
vertical
amplitude
06
0
HVDyCor
(11)
HVDyCorPol=1
½TVR
TVR
tVR
VHVD-
VHVD-V
Application dependent
x1111111
0
HVDyCor
horizontal
adjustments
04
05
18h
HVDyCor
(11)
½TVR
TVR
See Figure 16 on page 47
tVR
Application dependent
Note 64: For any H and V correction component of the waveforms on EWOut and VOut pins and internal waveform for
corrections of H asymmetry, displayed in the table, the weight of the other relevant components is nullified
(minimum for parabola, S-correction, medium for keystone, all corner corrections, C-correction, S- and W-pin
cushion corrections, parallelogram, pin cushion asymmetry correction, written in corresponding registers).
26/60
TDA9112A
8 I²C-BUS CONTROL REGISTER MAP
The device slave address is 8C in write mode and 8D in read mode. The control register map is given in
Table .
Bold weight denotes default value at Power-On-Reset.
I²C-bus data in the adjustment register is buffered and internally applied with discharge of the vertical oscillator (65).
In order to ensure compatibility with future devices, all “Reserved” bits should be set to 0.
Table 8. I²C-bus control registers
Sad
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
WRITE MODE (SLAVE ADDRESS = 8C)
00
01
HDutySyncV
1: Synchro.
0: Asynchro.
HDUTY
0
0
1
0
0
03
B+SyncV
0: Asynchro.
04
HDyCorTr
0: Not active
05
HDyCorPh
1: Middle
0: Start
1
0
06
BOutPol
0: Type N
1
0
07
BOutPh
0: H-flyback
1: H-drive
08
EWTrHFr
0: No tracking
Reserved
Reserved
0B
Reserved
0C
Reserved
0D
Reserved
0E
Reserved
0F
Reserved
0
0
0
0
1
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
1
0
0
1
0
0
1
0
0
C-correction
0
VMOIRE
0
S-correction
0
CCOR
1
Vertical position
0
SCOR
1
Vertical size
0
VPOS
Vertical moiré amplitude
0
PCC
0
Top corner correction
0
BCC
0
Keystone correction
0
TCC
0
Pin cushion correction
0
KEYST
0
HVDyCor vertical amplitude
0
VSIZE
0
HVDyCor horizontal phase
0
HVDC-VAMP
0
HVDyCor horizontal amplitude
0
HVDC-HPH
1
B+reference
0
HVDC-HAMP
0
Horizontal moiré amplitude
0
BREF
0
Horizontal position
0
HMOIRE
02
0A
0
HPOS
HMoiréMode
1: Separated
0: Combined
09
0
Horizontal duty cycle
0
Bottom corner correction
0
0
27/60
TDA9112A
Table 8. I²C-bus control registers
Sad
10
11
D7
D6
D5
D4
HSIZE
1
Reserved
12
Reserved
13
Reserved
14
Reserved
15
VDyCorPol
0: ”∪"
16
XRayReset
0: No effect
1: Reset
17
TV
0: Off(67)
0
0
0
PCAC
1
0
0
PARAL
1
0
0
1
0
0
1
0
0
1
0
0
VSyncAuto
1: On
VSyncSel
0:Comp
1:Sep
SDetReset
0: No effect
1: Reset
TH
0: Off(67)
TVM
0: Off(67)
THM
0: Off(67)
TCAC
BCAC
VDC-AMP
HVDC-HSHAP
18
Reserved
0:
19
Reserved
0:
1A
Reserved
0:
1
0
1B
Reserved
0:
0
0
1C
Reserved
0:
0
0
0
1D
Reserved
0:
1
1
1
1E
Reserved
0:
1
0
0
1F
ThrBlsense
0: High
0
0
0
EWSC
1
0
0
EWWC
0
HEHTG
0
VEHTG
VSAG
VPOF
BMute
0: Off
BSafeEn
0: Disable
D3
D2
D1
D0
0
0
0
Horizontal size
0
Pin cushion asymmetry correction
0
0
0
0
0
0
Parallelogram correction
0
0
Top corner asymmetry correction
0
0
0
0
Bottom corner asymmetry correction
0
0
0
0
0
0
PLL1InhEn
1: On
HLockEn
1: On
VOutEn
0: Disable
BlankMode
1: Perm.
0
0
0
0
0
0
Vertical dynamic correction
0
0
PLL1Pump
1,1: Fastest
0,0: Slowest
BOHEdge
0: Falling
HBOutEn
0: Disable
HVDyCor horizontal shape
0
0
East-West S-correction
0
0
East-West W-correction
0
0
Horizontal EHT compensation gain
0
0
0
0
Vertical EHT compensation gain
0
0
0
0
0
0
0
0
Vertical size after-gain
0
0
Vertical position offset
0
0
EWTrHSize
Ident
HLockSpeed HVDyCorPol HDCFlatEn
0: Tracking 0: No effect 0: Slow
0: ”∪"
0: Disable
READ MODE (SLAVE ADDRESS = 8D)
XX(66
)
HLock
0: Locked
1: Not locked
VLock
0: Locked
1: Not lock.
Polarity detection
XRayAlarm
1: On
HVPol
VPol
0: Off
1: Negative 1: Negative
Sync detection
VExtrDet
0: Not det.
HVDet
0: Not det.
VDet
0: Not det.
Note 65: With exception of HDUTY and BREF adjustments data that can take effect instantaneously if switches
HDutySyncV and B+SyncV are at 0, respectively.
Note 66: In Read Mode, the device always outputs data of the status register, regardless of sub address previously
selected.
Note 67: The TV, TH, TVM and THM bits are for testing purposes and must be kept at 0 by application.
28/60
TDA9112A
DESCRIPTION OF I²C-BUS SWITCHES AND FLAGS
Write-to bits
Sad00h/D7 - HDutySyncV
Synchronization of internal application of Horizontal Duty cycle data, buffered in I²C-bus latch,
with internal discharge of Vertical oscillator.
0: Asynchronous mode, new data applied
with ACK bit of I²C-bus transfer on this sub
address
1: Synchronous mode
Sad02h/D7 - HMoiréMode
Horizontal Moiré characteristics.
0: Adapted to an architecture with EHT generated in deflection section
1: Adapted to an architecture with separated
deflection and EHT sections
Sad03h/D7 - B+SyncV
Same as HDutySyncV, applicable for B+ reference data
Sad08h/D7 - EWTrHFr
Tracking of all corrections contained in waveform on pin EWOut with Horizontal Frequency
0: Not active
1: Active
Sad15h/D7 - VDyCorPol
Polarity of Vertical Dynamic Correction waveform (parabola)
0: Concave (minimum in the middle of the parabola)
1: Convex (maximum in the middle of the parabola)
Sad16h/D0 - HLockEn
Enable of output of Horizontal PLL1 Lock/unlock
status signal on pin HLckVBk
0: Disabled, vertical blanking only on the pin
HLckVBk
1: Enabled
Sad04h/D7 - HDyCorTr
Tracking of Horizontal Dynamic Correction
waveform amplitude with HSIZE adjustment.
0: Not active
1: Active
Sad05h/D7 - HDyCorPh
Phase of start of Horizontal Dynamic Correction waveform in relation to horizontal flyback pulse.
0: Start of the flyback
1: Middle of the flyback
Sad06h/D7 - BOutPol
Polarity of B+ drive signal on BOut pin.
0: adapted to N type of power MOS - high
level to make it conductive
1: adapted to P type of power MOS - low level
to make it conductive
Sad07h/D7 - BOutPh
Phase of start of B+ drive signal on BOut pin
0: End of horizontal flyback or horizontal frequency divided by 2, see BOHEdge bit.
1: With one of edges of line drive signal on
HOut pin, selected by BOHEdge bit
Sad16h/D1 - PLL1InhEn
Enable of Inhibition of horizontal PLL1 during
extracted vertical synchronization pulse
0: Disabled, PLL1 is never inhibited
1: Enabled
Sad16h/D2 and D3- PLL1Pump
Horizontal PLL1 charge Pump current
D3
0
1
0
1
D2
0
0
1
1
Time Constant
Slowest PLL1, lowest current
Moderate Slow PLL1, low current
Moderate Fast PLL1, high current
Fastest PLL1, highest current
Sad16h/D4 - SDetReset
Reset to 0 of Synchronization Detection flags
VDet, HVDet and VExtrDet of status register effected with ACK bit of I²C-bus data transfer into
register containing the SDetReset bit. Also see
description of the flags.
0: No effect
1: Reset with automatic return of the bit to 0
29/60
TDA9112A
Sad16h/D5 - VSyncSel
Vertical Synchronization input Selection between the one extracted from composite HV signal on pin H/HVSyn and the one on pin VSyn. No
effect if VSyncAuto bit is at 1.
0: V. sync extracted from composite signal on
H/HVSyn pin selected
1: V. sync applied on VSyn pin selected
Sad16h/D6 - VSyncAuto
Vertical Synchronization input selection Automatic mode. If enabled, the device automatically
selects between the vertical sync extracted from
composite HV signal on pin H/HVSyn and the one
on pin VSyn, based on detection mechanism. If
both are present, the one coming first is kept.
0: Disabled, selection done according to bit
VSyncSel
1: Enabled, the bit VSyncSel has no effect
Sad16h/D7 - XRayReset
Reset to 0 of XRay flag of status register effected with ACK bit of I²C-bus data transfer into register containing the XRayReset bit. Also see description of the flag.
0: No effect
1: Reset with automatic return of the bit to 0
Sad17h/D0 - BlankMode
Blanking operation Mode.
0: Blanking pulse starting with detection of
vertical synchronization pulse and ending
with end of vertical oscillator discharge
(start of vertical sawtooth ramp on the VOut
pin)
1: Permanent blanking - high blanking level in
composite signal on pin HLckVBk is permanent
Sad17h/D1 - VOutEn
Vertical Output Enable.
0: Disabled, VoffVOut on VOut pin (see Section
6.5 Vertical section)
1: Enabled, vertical ramp with vertical position
offset on VOut pin
Sad17h/D2 - HBOutEn
Horizontal and B+ Output Enable.
0: Disabled, levels corresponding to “power
transistor off” on HOut and BOut pins (high
30/60
for HOut, high or low for BOut, depending on
BOutPol bit).
1: Enabled, horizontal deflection drive signal
on HOut pin providing that it is not inhibited
by another internal event (activated XRay
protection). B+ drive signal on BOut pin if not
inhibited by another internal event.
Programming the bit to 1 after prior value of 0,
will initiate soft start mechanism of horizontal
drive and, if this is not inhibited by another internal event, also the soft start of B+ DC/DC convertor controller. See also bits BMute and BSafeEn.
Sad17h/D3 - BOHEdge
If the bit BOutPh is at 1, selection of Edge of Horizontal drive signal to phase B+ drive Output signal on BOut pin.
1: Rising edge
0: Falling edge
If the bit BOutPh is at 0, selection of signal to
phase B+ drive output on BOut pin:
1: Horizontal frequency divided by 2 signal,
top of horizontal VCO
0: End of horizontal flyback
Sad17h/D4,D5,D6,D7 - THM, TVM, TH, TV
Test bits. They must be kept at 0 level by application S/W.
Sad1Fh/D0 - HDCFlatEn
Enlargement of the Flat part on Horizontal Dynamic Correction waveform (starting at the beginning of horizontal flyback).
0: Disable
1: Enable
Sad1Fh/D1 - HVDyCorPol
Polarity of HV Dynamic Correction waveform.
0: Concave (minimum in the middle of the parabola)
1: Convex (maximum in the middle of the parabola)
Sad1Fh/D2 - HLockSpeed
Response Speed of lock-to-unlock transition of
H-lock component on HLock output and HLock
I²C-bus flag at signal change.
0: Low
1: High
TDA9112A
Sad1Fh/D3 - Ident
Device Identification bit.
If HBOutEn is at 1, the bit has no effect.
If HBOutEn is at 0, then
0: The value of Hlock status bit is 1
1: The value of Hlock status bit is 0
Sad1Fh/D4 - EWTrHSize
Tracking of all corrections contained in waveform on pin EWOut with Horizontal Size I²C-bus
register HSIZE .
0: Active
1: Not active
Sad1Fh/D5 - BSafeEn
B+ Output Safety Enable.
0: Disabled
1: Enabled, BOut goes off as soon as HLock
status of Horizontal PLL1 indicates “unlock”
state. Retrieval of “lock” state will initiate
soft start mechanism of DC/DC controller
on BOut output.
Sad1Fh/D6 - BMute
B+ Output Mute.
0: Disabled
1: Enabled, BOut goes unconditionally off.
Programming this bit back to 0 will initiate
soft start mechanism of DC/DC controller
on BOut output.
Sad1Fh/D7 - ThrBlsense
Threshold on BISense input corresponding to
current limitation.
0: High
1: Low
Read-out flags
SadXX/D0 - VDet(68)
Flag indicating Detection of V synchronization
pulses on VSyn pin.
0: Not detected
1: Detected
SadXX/D1 - HVDet (68)
Flag indicating Detection of H or HV synchronization pulses applied on H/HVSyn pin. Once the
sync pulses are detected, the flag is set and
latched. Disappearance of the sync signal will
not lead to reset of the flag.
0: Not detected
1: Detected.
SadXX/D2 - VExtrDet (68)
Flag indicating Detection of Extracted Vertical
synchronization signal from composite H+V signal applied on H/HVSyn pin.
0: Not detected
1: Detected
SadXX/D3 - VPol
Flag indicating Polarity of V synchronization
pulses applied on VSyn pin with respect to mean
level of the sync signal.
0: Positive
1: Negative
SadXX/D4 - HVPol
Flag indicating Polarity of H or HV synchronization pulses applied on H/HVSyn pin with respect
to mean level of the sync signal.
0: Positive
1: Negative
SadXX/D5 - XRayAlarm
Alarm indicating that an event of excessive voltage has passed on XRay pin. Can only be reset
to 0 through I²C-bus bit XRayReset or by poweron reset.
0: No excess since last reset of the bit
1: At least one event of excess appeared
since the last reset of the bit, HOut inhibited
SadXX/D6 - VLock
Status of “Locking” or stabilizing of Vertical oscillator amplitude to an internal reference by AGC
regulation loop.
0: Locked (amplitude stabilized)
1: Not locked (amplitude non-stabilized)
SadXX/D7 - HLock
Lock status of Horizontal PLL1.
0: Locked
1: Not locked
See also bit Ident (Sad1Fh/D3)
Note 68: This flag, by its value of 1, indicates an event of detection of at least one synchronization pulse since its last
reset (by means of the SDetReset I²C-bus bit). This is to be taken into account by application S/W in a way that
enough time (at least the period between 2 synchronization pulses of analyzed signal) must be provided
31/60
TDA9112A
between reset of the flag through SDetReset bit and validation of information provided in the flag after read-out
of status register.
32/60
TDA9112A
9 OPERATING DESCRIPTION
9.1 Supply and control
9.1.1 Power supply and voltage references
The device is designed for a typical value of power
supply voltage of 12 V.
In order to avoid erratic operation of the circuit at
power supply ramp-up or ramp-down, the value of
VCC is monitored. See Figure 1 and electrical specifications. At switch-on, the device enters a “normal operation” as the supply voltage exceeds VCCEn and stays there until it decreases bellow VCCDis. The two thresholds provide, by their difference, a hysteresis to bridge potential noise. Outside the “normal operation”, the signals on HOut,
BOut and VOut outputs are inhibited and the I²Cbus interface is inactive (high impedance on SDA,
SCL pins, no ACK), all I²C-bus control registers being reset to their default values (see Chapter 8 page 27). The stop of HOut and BOut drive signals
when the VCC falls from normal operation below
VCCDis is not instantaneous. It is only a trigger
point of Soft Stop mechanism (see Subsection 9.3.7page 38).
Figure 1. Supply voltage monitoring
V(Vcc)
VCC
VCCEn
Disabled
hysteresis
Normal operation
VCCDis
Disabled
t
Internal thresholds in all parts of the circuit are derived from a common internal reference supply
VRefO that is lead out to RefOut pin for external filtering against ground as well as for external use
with load currents limited to IRefO. The filtering is
necessary to minimize interference in output signals, causing adverse effects like e.g. jitter.
9.1.2 I²C-bus control
The I²C-bus is a 2 line bidirectional serial communication bus introduced by Philips. For its general
description, refer to corresponding Philips I²C-bus
specification.
This device is an I²C-bus slave, compatible with
fast (400kHz) I²C-bus protocol, with write mode
slave address of 8Ch (read mode slave address
8Dh). Integrators are employed at the SCL (Serial
Clock) input and at the input buffer of the SDA (Serial Data) input/output to filter off the spikes up to
50ns.
The device supports multiple data byte messages
(with automatic incrementing of the I²C-bus subaddress) as well as repeated Start Condition for I²Cbus subaddress change inside the I²C-bus messages. All I²C-bus registers with specified I²C-bus
subaddress are of WRITE ONLY type, whereas
the status register providing a feedback information to the master I²C-bus device has no attributed
I²C-bus subaddress and is of READ ONLY type.
The master I²C-bus device reads this register
sending directly, after the Start Condition, the
READ device I²C-bus slave address (8Dh) followed by the register read-out, NAK (No Acknowledge) signal and the Stop Condition.
For the I²C-bus control register map, refer to Chapter 8 - page 27.
9.2 Synchronization processor
9.2.1 Synchronization signals
The device has two inputs for TTL-level synchronization signals, both with hysteresis to avoid erratic
detection and with a pull-down resistor. On H/
HVSyn input, pure horizontal or composite horizontal/vertical signal is accepted. On VSyn input, only
pure vertical sync. signal is accepted. Both positive and negative polarities may be applied on either input, see Figure 2. Polarity detector and programmable inverter are provided on each of the
two inputs. The signal applied on H/HVSyn pin, after polarity treatment, is directly lead to horizontal
part and to an extractor of vertical sync. pulses,
working on principle of integration, see Figure 3.
The vertical sync. signal applied to the vertical deflection processor is selected between the signal
extracted from the composite signal on H/HVSyn input and the one applied on VSyn input. The selector is controlled by VSyncSel I²C-bus bit.
Besides polarity detection, the device is capable of
detecting presence of sync. signals on each of the
inputs and at the output of vertical sync. extractor.
The information from all detectors is provided in
the I²C-bus status register (5 flags: VDet, HVDet,
33/60
TDA9112A
VExtrDet, VPol, HVPol). The device is equipped
with an automatic mode (switched on or off by
VSyncAuto I²C-bus bit) that also uses the detection information.
Figure 2. Horizontal sync signal
Positive
TH
tPulseHSyn
9.2.2 Sync. presence detection flags
The sync. signal presence detection flags in the
status register (VDet, HVDet, VExtrDet) do not
show in real time the presence or absence of corresponding sync. signal. They are latched to 1 as
soon as a single sync. pulse is detected. In order
to reset them to 0 (all at once), a 1 must be written
into SDetReset I²C-bus bit, the reset action taking
effect with ACK bit of the I²C-bus transfer to the
register containing SDetReset bit. The detection
circuits are ready to capture another event (pulse).
See Note 68.
Negative
Figure 3. Extraction of V-sync signal from H/V-sync signal
H/V-sync
TH
tPulseHSyn
Internal
Integration
textrV
Extracted
V-sync
9.2.3 MCU controlled sync. selection mode
I²C-bus bit VSyncAuto is set to 0. The MCU reads
the polarity and signal presence detection flags,
after setting the SDetReset bit to 1 and an appropriate delay, to obtain a true information of the signals applied, reads and evaluates this information
and controls the vertical signal selector accordingly. The MCU has no access to polarity inverters,
they are controlled automatically.
See also chapter Chapter 8 - page 27.
34/60
9.2.4 Automatic sync. selection mode
I²C-bus bit VSyncAuto is set to 1. In this mode, the
device itself controls the I²C-bus bits switching the
polarity inverters (HVPol, VPol) and the vertical
sync. signal selector (VSyncSel), using the information provided by the detection circuitry. If both
extracted and pure vertical sync. signals are
present, the one already selected is maintained.
No intervention of the MCU is necessary.
TDA9112A
9.3 Horizontal section
9.3.1 General
The horizontal section consists of two PLLs with
various adjustments and corrections, working on
horizontal deflection frequency, then phase shifting and output driving circuitry providing H-drive
signal on HOut pin. Input signal to the horizontal
section is output of the polarity inverter on H/HVSyn
input. The device ensures automatically that this
polarity be always positive.
9.3.2 PLL1
The PLL1 block diagram is in Figure 5. It consists of
a voltage-controlled oscillator (VCO), a shaper
with adjustable threshold, a charge pump with inhibition circuit, a frequency and phase comparator
and timing circuitry. The goal of the PLL1 is to
make the VCO ramp signal match in frequency the
sync. signal and to lock this ramp in phase to the
sync. signal. On the screen, this offset results in
the change of horizontal position of the picture.
The loop, by tuning the VCO accordingly, gets and
maintains in coincidence the rising edge of input
sync. signal with signal REF1, deriving from the
VCO ramp by a comparator with threshold adjustable through HPOS I²C-bus control. The coincidence is identified and flagged by lock detection
circuit on pin HLckVBk as well as by HLock I²C-bus
flag.
The charge pump provides positive and negative
currents charging the external loop filter on HPLL1F
pin. The loop is independent of the trailing edge of
sync. signal and only locks to its leading edge. By
design, the PLL1 does not suffer from any dead
band even while locked. The speed of the PLL1
depends on current value provided by the charge
pump. While not locked, the current is very low, to
slow down the changes of VCO frequency and
thus protect the external power components at
sync. signal change. In locked state, the currents
are much higher, four different values being selectable via PLL1Pump I²C-bus bits to provide a
means to control the PLL1 speed by S/W. Lower
value make the PLL1 slower, but more stable.
Higher values make it faster and less stable. In
general, the PLL1 speed should be higher for high
deflection frequencies. The response speed and
stability (jitter level) depend on the choice of external components making up the loop filter. A “CRC”
filter is generally used (see Figure 4).
Figure 4. H-PLL1 filter configuration
HPLL1F
9
R2
C1
C2
The PLL1 is internally inhibited during extracted
vertical sync. pulse (if any) to avoid taking into account missing or wrong pulses on the phase comparator. Inhibition is obtained by forcing the charge
pump output to high impedance state. The inhibition mechanism can be disabled through
PLL1InhEn I²C-bus bit.
The Figure 7, in its upper part, shows the position of
the VCO ramp signal in relation to input sync.
pulse for three different positions of adjustment of
horizontal position control HPOS.
35/60
TDA9112A
Figure 5. Horizontal PLL1 block diagram
PLL1InhEn
V-sync (extracted)
(I²C)
HLckVBk
PLL1
Blank
3
HLock
(I²C)
HPLL1F RO CO HOscF
9
Sync
Polarity
LOCK
DETECTOR
H/HVSyn
1
INPUT
INTERFACE
8
CHARGE
PUMP
VCO
HPosF
Low
Extracted
V-sync
HOSC
10
PLL1Pump
(I²C)
REF1
4
PLL
INHIBITION
High
COMP
6
HPOS
(I²C)
SHAPER
Figure 6. Horizontal oscillator (VCO) schematic diagram
4 HOscF
I0
I0
(PLL1 filter)
HPLL1F 9
2
VHOThrHi
VHO
+
4 I0
+
-
+
VHOThrLo
RS
Flip-Flop
RO 8
from charge pump
VCO discharge
control
6 CO
VHOThrHi
VHOThrL
9.3.3 Voltage controlled oscillator
The VCO makes part of both PLL1 and PLL2
loops, being an “output” to PLL1 and “input” to
PLL2. It delivers a linear sawtooth. Figure 6 explains its principle of operation. The linears are obtained by charging and discharging an external capacitor on pin CO, with currents proportional to the
current forced through an external resistor on pin
RO, which itself depends on the input tuning voltage VHO (filtered charge pump output). The rising
and falling linears are limited by VHOThrLo and
VHOThrHi thresholds filtered through HOscF pin.
36/60
At no signal condition, the VHO tuning voltage is
clamped to its minimum (see section 6.4 - page
10), which corresponds to the free-running VCO
frequency fHO(0). Refer to subsection 9.3.1 for formula to calculate this frequency using external
components values. The ratio between the frequency corresponding to maximum VHO and the
one corresponding to minimum VHO (free-running
frequency) is about 4.5. This range can easily be
increased in the application. The PLL1 can only
lock to input frequencies falling inside these two
limits.
TDA9112A
rabola of 2nd order for Pin cushion asymmetry correction and half-parabolas of 4th order for corner
corrections independently at the top and at the
bottom) are generated from the output vertical deflection drive waveform, they all track with real vertical amplitude and position, thus being fixed on
the screen. Refer to Chapter 8 - page 27 for details
on I²C-bus controls.
Figure 7. Horizontal timing diagram
tHph
min
HPOS
(I²C)
max
H-sync
(polarized)
max.
med.
min.
PLL1
PLL1 lock
REF1
(internal)
VHOThrHi
VHPosF
max.
med.
min.
H-Osc
(VCO)
VS(0)
VHOThrLo
7/8TH
TH
VThrHFly
H-fly-back
tS
PLL2
control
current
PLL2
9.3.4 PLL2
The goal of the PLL2 is, by means of phasing the
signal driving the power deflection transistor, to
lock the middle of the horizontal flyback to a certain threshold of the VCO sawtooth. This internal
threshold is affected by geometry phase corrections, like e.g., parallelogram. The PLL2 is fast
enough to be able to follow the dynamism of phase
modulation, this speed is strongly related to the
value of the capacitor on HPLL2C. The PLL2 control current (see Figure 7) is significantly increased
during discharge of vertical oscillator (during vertical retrace period) to be able to make up for the
difference of dynamic phase at the bottom and at
the top of the picture. The PLL2 control current is
integrated on the external filter on pin HPLL2C to
obtain smoothed voltage, used, in comparison
with VCO ramp, as a threshold for H-drive rising
edge generation.
As both leading and trailing edges of the H-drive
signal in the Figure 7 must fall inside the rising part
of the VCO ramp, an optimum middle position of
the threshold has been found to provide enough
margin for horizontal output transistor storage time
as well as for the trailing edge of H-drive signal
with maximum duty cycle. Yet, the constraints
thereof must be taken into account while considering the application frequency range and H-flyback
duration. The Figure 7 also shows regions for rising
and falling edges of the H-drive signal on HOut pin.
As it is forced high during the H-flyback pulse and
low during the VCO discharge period, no edge
during these two events takes effect.
The flyback input configuration is in Figure 8.
9.3.5 Dynamic PLL2 phase control
The dynamic phase control of PLL2 is used to
compensate for picture asymmetry versus vertical
axis across the middle of the picture. It is done by
modulating the phase of the horizontal deflection
with respect to the incoming video (synchronization). Inside the device, the threshold VS(0) is compared with the VCO ramp, the PLL2 locking the
middle of H-flyback to the moment of their match.
The dynamic phase is obtained by modulation of
the threshold by correction waveforms. Refer to
Figure 14 and Chapter 7 - page 22. The correction
waveforms have no effect in vertical middle of the
screen (for middle vertical position). As they are
summed, their effect on the phase tends to reach
maximum span at top and bottom of the picture.
As all the components of the resulting correction
waveform (linear for parallelogram correction, pa-
+
ON
H-drive
(on HOut)
ON
OFF
tHoff
forced high
H-drive
region
forced low
tph(max)
H-drive
region
inhibited
tS: HOT storage time
Figure 8. HFly input configuration
~500Ω
HFly 12
~20kΩ
ext.
int.
GND
37/60
TDA9112A
9.3.6 Output Section
The H-drive signal is inhibited (high level) during
flyback pulse, and also when VCC is too low, when
X-ray protection is activated (XRayAlarm I²C-bus
flag set to 1) and when I²C-bus bit HBOutEn is set
to 0 (default position).
The duty cycle of the H-drive signal is controlled
via I²C-bus register HDUTY. This is overruled during soft-start and soft-stop procedures (see Section
9.3.7 and Figure 10).
The PLL2 is followed by a rapid phase shifting
which accepts the signal from H-moiré canceller
(see Section 9.3.8)
The output stage consists of a NPN bipolar transistor, the collector of which is routed to HOut pin
(see Figure 9).
Figure 9. HOut configuration
26 HOut
int.
ext.
9.3.7 Soft-start and soft-stop on H-drive
The soft-start and soft-stop procedure is carried
out at each switch-on or switch-off of the H-drive
signal, either via HBOutEn I²C-bus bit or after reset of XRayAlarm I²C-bus flag, to protect external
power components. By its second function, the external capacitor on pin HPosF is used to time out
this procedure, during which the duty cycle of Hdrive signal starts at its maximum ( tHoff for soft
start/stop in electrical specifications) and slowly
decreases to the value determined by the control
I²C-bus register HDUTY (vice versa at soft-stop).
This is controlled by voltage on pin HPosF. In case
of supply voltage switch off, the transients on HOut
and BOut have different characteristics. See
Figure 10, Figure 11 and Section 9.8.1.
38/60
9.3.8 Horizontal moiré cancellation
The horizontal moiré canceller is intended to blur a
potential beat between the horizontal video pixel
period and the CRT pixel width, which causes visible moiré patterns in the picture.
It introduces a microscopic indent on horizontal
scan lines by injecting little controlled phase shifts
to output circuitry of the horizontal section. Their
amplitude is adjustable through HMOIRE I²C-bus
control.
The behaviour of horizontal moiré is to be optimized for different deflection design configurations
using HMoiréMode I²C-bus bit. This bit is to be
kept at 0 for common architecture (B+ and EHT
common regulation) and at 1 for separated architecture (B+ and EHT each regulated separately).
The maximum amplitude adjustable though HMOIRE I²C-bus control is optimized according to selection by HMoiréMode I²C-bus bit: larger when B+
and EHT are each regulated separately, smaller
when B+ and EHT are common regulation.
TDA9112A
Figure 10. Control of HOut and BOut at start/stop at nominal VCC
minimum value
V(HPosF)
HPOS range
(I²C)
VHPosF
maximum value
VHBNorm
VBOn
VHOn
Normal operation
Soft start
Start
H-drv
Soft stop
Stop
B-drv
Start
B-drv
Stop
H-drv
t
HOut
100%
H-duty cycle
BOut (positive)
B-duty cycle
0%
Figure 11. Events triggering Soft start and Soft stop
V[HPosF]
maximum VCC fall down
speed for correct operation
V[HPosF]
VCCDis
Soft start
event
Soft stop
event
V(HPosF)
V(HPosF)
VHPosF
VHBNorm
τ
VHPosF
VHBNorm
VBOn
τ
VCC
VCCStop
VHBNorm’
VBOn’
VBOn
VHOn
VHOn
τ
HBOutEn=1
XRayAlarm=0
VHOn’
t
t
HOut duty cycle
100%
HOut duty cycle
100%
BOut duty cycle
0%
BOut duty cycle
0%
NOMINAL VCC
FALLING VCC
39/60
TDA9112A
9.4 Vertical section
9.4.1 General
The goal of the vertical section is to drive vertical
deflection output stage. It delivers a sawtooth
waveform with an amplitude independent of deflection frequency, on which vertical linearity corrections of C- and S-type are superimposed (see
Chapter 7 - page 22).
Block diagram is in Figure 12. The sawtooth is obtained by charging an external capacitor on pin
VCap with controlled current and by discharging it
via transistor Q1. This is controlled by the CONTROLLER. The charging starts when the voltage
across the capacitor drops below VVOB threshold.
The discharging starts either when it exceeds
VVOT threshold (free run mode) or a short time after arrival of synchronization pulse. This time is
necessary for the AGC loop to sample the voltage
at the top of the sawtooth. The VVOB reference is
routed out onto VOscF pin in order to allow for further filtration.
The charging current influences amplitude of the
sawtooth. Just before the discharge, the voltage
across the capacitor on pin VCap is sampled and
compared to VVOTref. The comparison error voltage is stored on a storage capacitor connected on
pin VAGCCap. This voltage tunes gain of the
transconductance amplifier providing the charging
current in the next vertical period. Speed of this
AGC loop depends on the storage capacitance on
pin VAGCCap. The VLock I²C-bus flag is set to 1
when the loop is stabilized, i.e. when the tops of
saw tooth on pin VCap match VVOT value. On the
screen, this corresponds to stabilized vertical size
of picture. After a change of frequency on the
sync. input, the stabilization time depends on the
frequency difference and on the capacitor value.
The lower its value, the shorter the stabilization
time, but on the other hand, the lower the loop stability. A practical compromise is a capacitance of
470nF. The leakage current of this capacitor results in difference in amplitude between low and
high frequencies. The higher its parallel resistance
RL(VAGCCap), the lower this difference.
When the synchronization pulse is not present, the
charging current is fixed. As a consequence, the
free-running frequency fVO(0) only depends on the
value of the capacitor on pin VCap. It can be roughly calculated using the following formula
40/60
fVO(0) =
150nF
C(VCap)
. 100Hz
The frequency range in which the AGC loop can
regulate the amplitude also depends on this capacitor.
The vertical sawtooth with regulated amplitude is
lead to amplitude control stage. The discharge exponential is replaced by VVOB level, which, under
control of the CONTROLLER, creates a rapid falling edge and a flat part before beginning of new
ramp.
The AGC output signal passes through gain and
position adjustment stages controlled through
VSIZE and VPOS I²C-bus registers. The resulting
signal serves as input to all geometry correction
circuitry including EW-drive signal, horizontal
phase modulation and dynamic correction outputs.
9.4.2 S and C corrections
For the sake of vertical picture linearity, the S- and
C-corrections are now superimposed on the linear
ramp signal. They both track with VSIZE and
VPOS adjustments to ensure unchanged linearity
on the screen at changes of vertical size or vertical
position. As these corrections are not included in
the AGC loop, their adjustment via CCOR and
SCOR I²C-bus registers, controlling shape of vertical output sawtooth affects by principle its peak-topeak amplitude. However, this stage is conceived
in a way that the amplitude be independent of
these adjustments if VSIZE and VPOS registers
are set to their medium values.
9.4.3 Vertical breathing compensation
The signal provided with the linearity corrections is
amplitude affected in a gain control stage, ruled by
the voltage on VEHTIn input and its I²C-bus control
VEHTG.
9.4.4 Vertical after-gain and offset control
Another gain control is applied via VSAG I²C-bus
register. Then an offset is added, its amount corresponding to VPOF I²C-bus register value. These
two controls result in size and position changes
with no effect on shape of output vertical sawtooth
or any geometry correction signal.
TDA9112A
9.4.6 Biasing of vertical booster
The biasing voltage for external DC-coupled vertical power amplifier is to be derived from VRefO
voltage provided on pin RefOut, using a resistor divider, this to ensure the same temperature drift of
mean (DC) levels on both differential inputs and to
compensate for spread of VRefO value (and so
mean output value) between particular devices.
9.4.5 Vertical moiré
To blur potential moiré patterns due to interaction
of deflection lines with CRT mask grid, the picture
position is to be slightly alternated at frame frequency. For this purpose, a square waveform at
half-frame frequency is superimposed on the output waveform. Its amplitude is adjustable through
VMOIRE I²C-bus control.
Figure 12. Vertical section block diagram
Trans-conductance amplifier
Charge current
OSC
Cap.
VVOTref
VCap
22
Sampling
20 VAGCCap
Discharge
VSyn 2
Synchro
Controller
Sampling
Capacitance
R
Q1
Polarity
Vmidref
Vmidref
To geometry processing
sawtooth
discharge
R
Internal
V-ramp
Vmidref
VVOB
VSIZE (I²C)
19
VPOS (I²C)
VEHTIn 18
VOscF
VVEHTnull
VEHTG (I²C)
SCOR (I²C)
VMOIRE (I²C)
S-correction
VOut 23
VPOF (I²C)
VPOS (I²C)
VSAG (I²C)
CCOR (I²C)
C-correction
41/60
TDA9112A
9.5 EW drive section
The goal of the EW drive section is to provide, on
pin EWOut, a waveform which, used by an external
DC-coupled power stage, serves to compensate
for those geometry errors of the picture that are
symmetric versus vertical axis across the middle
of the screen.
The waveform consists of an adjustable DC value,
corresponding to horizontal size, a parabola of 2nd
order for “pin cushion” correction, a linear for “keystone” correction, independent half-parabolas of
4th order for top and bottom corner corrections, Sshape for “S” correction and W shape for “W” correction. All of them are adjustable via I²C-bus, see
Chapter 8 - page 27.
Refer to Figure 14, Figure 15 and chapter Chapter 7 page 22. The adjustments of these correction
waveforms have no effect in the middle of the vertical scan period (if the VPOS control is adjusted to
its medium value). As they are summed, the resulting waveform tends to reach its maximum span
at top and bottom of the picture. The voltage at the
EWOut is top and bottom limited (see parameter
VEW). According to Figure 15, especially the bottom
limitation seems to be critical for maximum horizontal size (minimum DC). Actually it is not critical
since the parabola component must always be applied to obtain a picture without pin cushion distortion. As all the components of the resulting correction waveform are generated from an internal linear vertical sawtooth waveform bearing VSIZE and
VPOS adjustments, they all track with vertical amplitude and position, thus being fixed vertically on
the screen. They are not affected by C- and S-cor-
42/60
rections, by prescale adjustments (VSAG and
VPOF), by vertical breathing compensation and by
vertical moire cancellation. The sum of components other than DC is conditionally affected by
value in HSIZE I²C-bus control in reversed sense.
Refer to electrical specifications for value. This
tracking with HSIZE can be switched off by
EWTrHSize I²C-bus bit. The DC value, adjusted
via HSIZE control, is also affected by voltage on
HEHTIn input, thus providing a horizontal breathing
compensation. The effect of this compensation is
controlled by HEHTG. The resulting waveform is
conditionally multiplied with voltage on HPLL1F,
which depends on frequency. Refer to electrical
specifications for values. This tracking with frequency provides a rough compensation of variation of picture geometry with frequency and allows
to fix the adjustment ranges of I²C-bus controls
throughout the operating range of horizontal frequencies. It can be switched off by EWTrHFr I²Cbus bit (off by default). The functionality is explained in Figure 13. The upper part gives the influence on DC component, the lower part on AC
component, showing also the tracking with HSIZE.
Grey zones give the total span of breathing correction using the whole range of input operating voltage on HEHTIn input and whole range of adjustment of HEHTG register.
The EW waveform signal is buffered by an NPN
emitter follower, the emitter of which is directly
routed to EWOut output. It is internally biased (see
electrical specifications for current value).
TDA9112A
Figure 13. Tracking of EWOut signal with frequency
VEW-DC
VEW-DC
HSIZE=max
breathing
HS
ax
=m
E
IZ
breathing
breathing
breathing
HSIZE=min
EW-base
HSIZE=min
VEW-base
min
min
EWTrHFr=0
EWTrHFr=1
VHOThrfr max
min
VHOThrfr max
min
VHO
VHO
breathing
HSIZE=min
HSIZE=max
breathing
VEW-AC
VEW-AC
breathing
I
HS
H
EWTrHSize=1
EWTrHFr=0
0
VHO
m
E=
SIZ
breathing
ax
EWTrHSize=1
EWTrHFr=1
0
VHOThrfr max
min
in
=m
E
Z
VHOThrfr max
min
VHO
43/60
TDA9112A
Figure 14. Geometric corrections’ schematic diagram
VDC-AMP
VDyCorPol
VVD-DC
VDyCor
-1
HVDC-HPH
Vmidref
Phase
32
tracking
HSIZE
EWTrHSize
H-Ramp
generator
HVDC-HSHAP
HVDC-HAMP
HVDyCorPol
Xn
Shape
VHVD-DC
HVDyCor
-1
11
X2
H-size control
HVDC-VAMP
X4
Keystone
Pin cushion
KEYST
PCC
DC
0...2.5V
HSIZE
EWTrHSize
Int. V-ramp
(linear, before
corrections)
Breathing
HEHTG
tracking
VHEHTnull
17
Top corner
TCC
HEHTIn
VEW(max)
Bot. corner
BCC
0V
EWOut
“W”
3
X
“S”
Parallelogram
Pin cushion
asymmetry
Top corner
asymmetry
Bottom corner
asymmetry
44/60
EWWC
24
0V
VEW-base
EWSC
PARAL
Tracking
with hor.
frequency
1
9
EWTrHFr 0
0V
HPLL1F
VHOThrfr
PCAC
To HPLL2
TCAC
Internal dynamic
phase waveform
BCAC
VEW(min)
Controls:
1-quadrant
2-quadrant
TDA9112A
Figure 15. EWOut output waveforms
max
VEW-Key
VEW-
VEW-
VEW-W
VEW-S
HSIZE
(I²C)
HEHTG
(I²C)
Tracking with frequency off. (EWTrHFr = 0)
00h
max.
VEW-BCor
min
00h
non-linear region
non-linear region
VEW
7Fh
7Fh
00h
mid.
min.
W alone
V(VCap)
0
VRef
S alone
VHEHT(max
Breathing
compensation
on DC
Bottom
Corners
alone
VHEHTn
PCC
alone
VHEHT(min)
Top
Keystone
alone
VEW-
7Fh
VHEH
Vertical sawtooth
0
TVR
0
TVR
0
TVR
0
TVR
0
TVR
tVR
45/60
TDA9112A
9.6 Dynamic correction outputs section
9.6.1
Composite horizontal and vertical
dynamic correction output HVDyCor
A composite waveform is output on pin HVDyCor. It
consists of a parabola of vertical deflection frequency, on which a parabola of horizontal deflection frequency is superimposed. The two parabolic
components can independently be adjusted via
I²C-bus, the vertical parabola in amplitude ( HVDCVAMP I²C-bus control), the horizontal parabola in
amplitude, phase and shape ( HVDC-HAMP,
HVDC-HPH and HVDC-HSHAP I²C-bus controls).
See also Chapter 8 - page 27 chapter. The influence
of the vertical component can be nullified by adjusting its control to minimum. For horizontal
waveform component, refer to Figure 16 and Figure
17. The minimum value in HVDC-HAMP I²C-bus
control does not correspond to null horizontal amplitude. The phase of the horizontal parabola can
roughly be adjusted via HDyCorPh I²C-bus bit for
the waveform’s start to coincide either with the beginning or the middle of the H-flyback pulse. Moreover, its centre can be offset via HVDC-HPH I²Cbus control. The shape of the horizontal parabola
can be adjusted via HVDC-HSHAP I²C-bus control
from a power-of-two to about a power-of-four. Between the waves of two subsequent lines, a flat is
inserted at level corresponding to the beginning of
the new wave. Putting HDCFlatEn and HDyCorPh
to “1” will cause the flat part to begin at start of Hflyback and end a delay after its middle. Only this
delay (its duration is quasi-constant) is applied
46/60
when HDCFlatEn is at “0”. Refer to electrical specifications for values.
The horizontal parabola component tracks with
value in HSIZE control provided that HDyCorTr I²C
bit is set to 1 (0 by default).
As the vertical parabola component is generated
from the output vertical deflection drive waveform,
it tracks with real vertical amplitude and position. It
is not affected by C- and S-corrections or vertical
breathing compensation. It does not track with
Vertical size after-gain (Sad1Dh) nor with Vertical
position offset (Sad1Eh) adjustments.
The polarity of the HVDyCor output can be adjusted
via HVDyCorPol I²C-bus bit.
9.6.2
Vertical dynamic correction output
VDyCor
A parabola at vertical deflection frequency is available on pin VDyCor. Its amplitude is adjustable via
VDC-AMP I²C-bus control and polarity controlled
via VDyCorPol I²C-bus bit. It tracks with real vertical amplitude and position. It is not affected by Cand S-corrections or breathing compensation. It
does not track with Vertical size after-gain
(Sad1Dh) nor with Vertical position offset
(Sad1Eh) adjustments.
The use of both correction waveforms is up to the
application (e.g. dynamic focus, dynamic brightness control).
TDA9112A
Figure 16. HVDyCor output horizontal component waveform
max
V(HVDyCor)
mid
1
min
HVDC-HPH
HVDyCorPol
min
VHVD-H
0
mid
max
tHVD-Hoffset tHVD-Hoffset
(min)
V(HVDyCor)
VHVD-DC
(max)
HVDC-HSHAP
max mid min
HDCFlatEn=0
HDyCorPh=X
OR
HDCFlatEn=X
HDyCorPh=0
tHVD-Hflat
V(HVDyCor)
HVDC-HSHAP
max mid min
HDCFlatEn=1
HDyCorPh=1
tHVD-Hflat
TH
HDyCorPh=1
Shaped H-flyback
HDyCorPh=0
47/60
TDA9112A
Figure 17. Shape characteristic versus HVDC-HSHAP register adjustment.
4.0
Power factor 3.8
(SHVDCHSHAP)
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
0
31
63
95
127
HVDC-HSHAP I²C register value
9.7 DC/DC controller section
The section is designed to control a switch-mode
DC/DC converter. A switch-mode DC/DC convertor generates a DC voltage from a DC voltage of
different value (higher or lower) with little power
losses. The DC/DC controller is synchronized to
horizontal deflection frequency to minimize potential interference into the picture.
Its operation is similar to that of standard UC3842.
The schematic diagram of the DC/DC controller is
in Figure 18. The BOut output controls an external
switching circuit (a MOS transistor) delivering
pulses synchronized on horizontal deflection frequency, the phase of which depends on H/W and
I²C-bus configuration. See the table at the end of
this chapter. Their duration depends on the feedback provided to the circuit, generally a copy of
DC/DC converter output voltage and a copy of current passing through the DC/DC converter circuitry
(e.g. current through external power component).
The polarity of the output can be controlled by
BOutPol I²C-bus bit. A NPN transistor open-collector is routed out to the BOut pin.
During the operation, a sawtooth is to be found on
pin BISense, generated externally by the application. According to BOutPh I²C-bus bit, the R-S flipflop is set either at H-drive signal edge (rising or
falling, depending on BOHEdge I²C-bus bit), or a
48/60
certain delay (tBTrigDel) after middle of H-flyback,
or at horizontal frequency divided by two (phase
corresponding to VHOThrHi on the VCO ramp). The
output is set On at the end of the short pulse generated by the monostable trigger.
Timing of reset of the R-S flip-flop affects duty cycle of the output square signal and so the energy
transferred from DC/DC converter input to its output. A reset edge is provided by comparator C2 if
the voltage on pin BISense exceeds the internal
threshold VThrBIsCurr. This represents current limitation if a voltage proportional to the current
through the power component or deflection stage
is available on pin BISense. This threshold is affected by voltage on pin HPosF, which rises at soft
start and descends at soft stop. This ensures selfcontained soft control of duty cycle of the output
signal on pin BOut. Refer to Figure 10. Another condition for reset of the R-S flip-flop, OR-ed with the
one described before, is that the voltage on pin BISense exceeds the voltage VC2, which depends on
the voltage applied on input BRegIn of the error
amplifier O1. The two voltages are compared, and
the reset signal generated by the comparator C1.
The error amplifier amplifies (with a factor defined
by external components) the difference between
the input voltage proportional to DC/DC convertor
output voltage and internal reference VBReg. The
TDA9112A
internal reference and so the output voltage is I²Cbus adjustable by means of BREF I²C-bus control.
Both step-up (DC/DC converter output voltage
higher than its input voltage) and step-down (output voltage lower than input) can be built.
9.7.1 Synchronization of DC/DC controller
For sake of application flexibility, the output drive
signal on BOut pin can be synchronized with one of
four events in Table 9. For the first line case, the
synchronization instant is every second top of horizontal VCO saw tooth. See Figure 7.
9.7.2 Soft-start and soft-stop on B-drive
The soft-start and soft-stop procedure is carried
out at each switch-on or switch-off of the B-drive
signal, either via HBOutEn I²C-bus bit or after re-
set of XRayAlarm I²C-bus flag, to protect external
power component. See Figure 10 and sub chapter
Safety functions on page 50.
The drive signal on BOut pin can be switched off
alone by means of BMute I²C-bus bit, without
switching off the drive signal on pin HOut. The
switch-off is quasi-immediate, without the soft-stop
procedure. At switching back on, the soft-start of
the DC/DC controller is performed, timed by an internal timing circuit, see Figure 18.
When BSafeEn I²C-bus bit is enabled, the drive
signal on BOut pin will go off as soon as the horizontal PLL1 indicates unlocked state, without the
soft-stop. Resuming of locked state will initiate the
soft-start mechanism of the DC/DC controller,
timed by an internal timing circuit.
Table 9. IDC/DC controller Off-to-On edge timing
BOutPh
(Sad07h/D7)
BOHEdge
(Sad17h/D3)
Timing of Off-to-On transition on BOut output
0
1
VCO ramp top at Horizontal frequency divided by two
0
0
Middle of H-flyback plus tBTrigDel
1
0
Falling edge of H-drive signal
1
1
Rising edge of H-drive signal
Figure 18. DC/DC converter controller block diagram
BOutPh
(I²C)
0
H-drive edge
1
1
Monostable
BOHEdge
(I²C)
0
H-fly-back
(+delay)
~500ns
I1
0
VCO
÷2
VCC
1
I2
N type
VBReg
Feedback
15
BRegIn
+
O1
-
2R
R
VC2
R
Q
P type
B-drive inhibition
(safety functions)
+
C3
16
BISense
I3
BOutPol
(I²C)
C2
+
Soft start
10
HPosF
S
C1
+
BOut
-
14
BComp
VThrBIsCurr
Safety block
28
-
timing
B-drive protection at H-unlock
(safety functions)
49/60
TDA9112A
9.8 Miscellaneous
9.8.1 Safety functions
The safety functions comprise supply voltage
monitoring with appropriate actions, soft start and
soft stop features on H-drive and B-drive signals
on HOut and BOut outputs, B-drive cut-off at unlock
condition and X-ray protection.
For supply voltage supervision, refer to subsection
9.1.1 and Figure 1. A schematic diagram putting together all safety functions and composite PLL1
lock and V-blanking indication is in Figure 19.
9.8.1.1 Soft start and soft stop function
For soft start and soft stop features for H-drive and
B-drive signal, refer to subsection 9.3.7 and subsection 9.7 , respectively. See also the Figure 10 and
Figure 11. Regardless why the H-drive or B-drive
signal are switched on or off (I²C-bus command,
power up or down, X-ray protection), the signals
always phase-in and phase-out in the way drawn
in the figures, the first to phase-in and last to
phase-out being the H-drive signal, which is to better protect the power stages at abrupt changes like
switch-on and off. The timing of phase-in and
phase-out depends on the capacitance connected
to HPosF pin which is virtually unlimited for this
function. However, as it has a dual function (see
subsection 9.3.2 ), a compromise thereof is to be
found.
50/60
The soft stop at power down condition can be considered as a special case. As at this condition the
thresholds VHOn, VBOn and VHBNorm depend on
the momentary level of supply voltage (marked
VHOn’, VBOn’, VHBNorm’ in Figure 11), the timing of
soft stop mechanism depends, apart from the capacitance on HPosF, also on the falling speed of
supply voltage. The device is capable of performing a correct soft stop sequence providing that, at
the moment the supply voltage reaches VCCStop,
the voltage on HPosF has already fallen below
VHOn (Section 9.8).
9.8.1.2 B-drive cut-off at unlock condition
This function is described in subsection 9.7.2 .
9.8.1.3 X-ray protection
The X-ray protection is activated if the voltage level on XRay input exceeds VThrXRay threshold and if
the VCC is higher than the voltage level VCCXRayEn. As a consequence, the H-drive and B-drive
signals on HOut and BOut outputs are inhibited
(switched off) after a 2-horizontal deflection line
delay provided to avoid erratic excessive X-ray
condition detection at short parasitic spikes. The
XRayAlarm I²C-bus flag is set to 1 to inform the
MCU.
This protection is latched; it may be reset either by
VCC drop or by I²C-bus bit XRayReset
(see Chapter 8 - page 27).
TDA9112A
Figure 19. Safety functions - block diagram
BSafeEn
I²C
B-drive protection at H-unlock
BMute I²C
H-lock detector
0 = Off
1 = On
HBOutEn
I²C
VCC
+
VCCEn
VCCDis
_
HPosF
10
= start
= stop
VCC supervision
(timing)
SOFT
START & STOP
INHIBITION
CONTROL
H-VCO
discharge
control
PLL1
PLL2
DC/DC
XRayAlarm
XRayReset
R
Q
I²C
I²C
XRay
25
VThrXRay
VCC
VCCXRay
HFly
12
In
+
:2
Out
Enable
S
B-drive inhibit
_
H-drive inhibit
H-drive inhibition
(overrule)
+
_
V-drive inhibition
+
_
VThrHFly
B-drive inhibition
VOutEn
I²C
BlankMode
I²C
HLockEn
L1=No blank/blank level
I²C
H-lock detector
Σ
HLckVBk
3
L3=L1+L2
L2=H-lock/unlock level
HLock
V-sawtooth
discharge
R
Q
I²C
S
V-sync
I²C
I²C bit/flag
Int. signal
X Pin
51/60
TDA9112A
9.8.2 Composite output HLckVBk
The composite output HLckVBk provides, at the
same time, information about lock state of PLL1
and early vertical blanking pulse. As both signals
have two logical levels, a four level signal is used
to define the combination of the two. Schematic diagram putting together all safety functions and
composite PLL1 lock and V-blanking indication is
in Figure 19, the combinations, their respective levels and the HLckVBk configuration in Figure 20.
The early vertical blanking pulse is obtained by a
logic combination of vertical synchronization pulse
and pulse corresponding to vertical oscillator discharge. The combination corresponds to the drawing in Figure 20. The blanking pulse is started with
the leading edge of any of the two signals, whichever comes first. The blanking pulse is ended with
the trailing edge of vertical oscillator discharge
pulse. The device has no information about the
vertical retrace time. Therefore, it does not cover,
by the blanking pulse, the whole vertical retrace
period. By means of BlankMode I²C-bus bit, when
at 1 (default), the blanking level (one of two according to PLL1 status) is made available on the
HLckVBk permanently. The permanent blanking, irrespective of the BlankMode I²C-bus bit, is also
provided if the supply voltage is low (under VCCEn
or VCCDis thresholds), if the X-ray protection is active or if the V-drive signal is disabled by VOutEn
I²C-bus bit.
Figure 20. Levels on HLckVBk composite output
L1 - No blank/blank level
L2 - H-lock/unlock level
VCC
3
L1(H)+L2(H)
HLckVBk
L1(L)+L2(H)
ISinkLckBk
VOLckBk
L1(H)+L2(L)
L1(L)+L2(L)
52/60
V-early blanking
No
Yes
No
Yes
HPLL1 locked
Yes
Yes
No
No
TDA9112A
Figure 21. Ground layout recommendations
TDA9112A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
General Ground
53/60
TDA9112A
10 INTERNAL SCHEMATICS
Figure 25.
Figure 22.
VCC
VRefO
5V
H/HVSyn
1
5
HPLL2C
200Ω
Applies also for pin 2 (VSyn)
Figure 26.
Figure 23.
VCC
VCC
VRefO
VRefO
CO
6
HLckVBk 3
Figure 27.
Figure 24.
VCC
12V
VRefO
RO 8
HOscF 4
54/60
3
VRefO
TDA9112A
Figure 28.
Figure 31.
VCC
HPLL1F 9
HFly 12
Figure 29.
Figure 32.
12V VRefO
VCC
HPosF 10
BComp
14
Figure 30.
Figure 33.
VCC
VCC
VCC
BRegIn 15
HVDyCor 11
55/60
3
TDA9112A
Figure 34.
Figure 37.
VCC
VCC
BISense
16
VAGCCap
20
Figure 35.
Figure 38.
VCC
22
VCap
VCC
HEHTIn 17
Applies also for pin 18 (VEHTIn)
Figure 36.
Figure 39.
VCC
VRefO
VCC
VOut
VOscF 19
56/60
3
23
TDA9112A
Figure 40.
Figure 43.
VCC
VCC
SCL 30
EWOut 24
Applies also for pin 32 (VDyCor)
Applies also for pin 31 (SDA)
Figure 41.
VCC
XRay 25
Figure 42.
VCC
HOut 26
Applies also for pin 28 (BOut)
57/60
3
TDA9112A
11 PACKAGE MECHANICAL DATA
32 PINS - PLASTIC SHRINK
E
A
A1
A2
E1
L
C
B
e
B1
Stand-off
eA
eB
D
32
17
1
16
Dimensions
Millimeters
Typ.
Max.
3.759
5.080
Typ.
Max.
0.140
0.148
0.200
A
3.556
0.508
A2
3.048
3.556
4.572
0.120
0.140
0.180
B
0.356
0.457
0.584
0.014
0.018
0.023
B1
0.762
1.016
1.397
0.030
0.040
0.055
C
.203
0.254
0.356
0.008
0.010
0.014
D
27.43
27.94
28.45
1.080
1.100
1.120
E
9.906
10.41
11.05
0.390
0.410
0.435
E1
7.620
8.890
9.398
0.300
0.350
0.370
0.020
e
1.778
0.070
eA
10.16
0.400
L
4
Min.
A1
eB
58/60
Inches
Min.
12.70
2.540
3.048
3.810
0.500
0.100
0.120
0.150
TDA9112A
12 GLOSSARY
AC
ACK
AGC
COMP
CRT
DC
EHT
EW
H/W
HOT
I2C
Alternate Current
ACKnowledge bit of I²C-bus transfer
Automatic Gain Control
COMParator
Cathode Ray Tube
Direct Current
Extra High Voltage
East-West
HardWare
Horizontal Output Transistor
Inter-Integrated Circuit
IIC
Inter-Integrated Circuit
MCU
NAND
NPN
OSC
PLL
PNP
REF
RS, R-S
S/W
TTL
VCO
Micro-Controller Unit
Negated AND (logic operation)
Negative-Positive-Negative
OSCillator
Phase-Locked Loop
Positive-Negative-Positive
REFerence
Reset-Set
SoftWare
Transistor Transistor Logic
Voltage-Controlled Oscillator
59/60
5
TDA9112A
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no
responsibility for the consequences of use of such information nor for any infringement of patents or other
rights of third parties which may result from its use. No license is granted by implication or otherwise under
any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied.
STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
© 2003 STMicroelectronics - All Rights Reserved
STMicroelectronics GROUP OF COMPANIES
Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan
Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A.
www.st.com
60/60
6