TDA9116 LOW-COST I2C CONTROLLED DEFLECTION PROCESSOR FOR MULTISYNC MONITOR FEATURES General 2 ■ ADVANCED I C BUS CONTROLLED DEFLECTION PROCESSOR DEDICATED FOR HIGH-END CRT MONITORS ■ SINGLE SUPPLY VOLTAGE 12V ■ VERY LOW JITTER ■ DC/DC CONVERTER CONTROLLER ■ ADVANCED EW DRIVE ■ ADVANCED ASYMMETRY CORRECTIONS ■ AUTOMATIC MULTISTANDARD SYNCHRONIZATION ■ VERTICAL DYNAMIC CORRECTION WAVEFORM OUTPUT ■ X-RAY PROTECTION AND SOFT-START & STOP ON HORIZONTAL AND DC/DC DRIVE OUTPUTS 2 ■ I C BUS STATUS REGISTER Horizontal section 150 kHz maximum frequency ■ Corrections of geometric asymmetry: Pin cushion asymmetry, Parallelogram ■ Tracking of asymmetry corrections with vertical size and position ■ Fully integrated internal horizontal moiré cancellation and moiré cancellation output ■ Vertical section ■ 200 Hz maximum frequency ■ Vertical ramp for DC-coupled output stage with adjustments of: C-correction, S-correction for super-flat CRT, Vertical size, Vertical position ■ Vertical moiré cancellation through vertical ramp waveform ■ Compensation of vertical breathing with EHT variation Dynamic correction section ■ Output with vertical dynamic correction waveform for dynamic corrections like focus, brightness uniformity, ... ■ Fixed on screen by means of tracking system DC/DC controller section ■ Step-up and step-down conversion modes ■ External sawtooth configuration ■ Bus-controlled output voltage ■ Synchronization on hor. frequency with phase selection ■ Selectable polarity of drive signal DESCRIPTION The TDA9116 is a monolithic integrated circuit assembled in a 32-pin shrink dual-in-line plastic package. This IC controls all the functions related to horizontal and vertical deflection in multimode or multi-frequency computer display monitors. The internal sync processor, combined with the powerful geometry correction block, makes the TDA9116 suitable for very high performance monitors, using few external components. Combined with other ST components dedicated for CRT monitors (microcontroller, video preamplifier, video amplifier, OSD controller) the TDA9116 allows fully I2C bus-controlled computer display monitors to be built with a reduced number of external components. ORDERING INFORMATION Ordering code TDA9116 Package Shrink 32 (plastic) EW section ■ Symmetrical geometry corrections: Pin cushion, Keystone, Top/Bottom corners separately ■ Horizontal size adjustment ■ Tracking of EW waveform with Vertical size and position and adaptation to frequency ■ Compensation of horizontal breathing through EW waveform Version 4.0 September 2003 1/47 1 Table of Contents 1 - GLOSSARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 - PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 - BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 - PIN FUNCTION REFERENCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 - QUICK REFERENCE DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6 - ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7 - ELECTRICAL PARAMETERS AND OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . 10 7.1 - THERMAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 7.2 - SUPPLY AND REFERENCE VOLTAGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 7.3 - SYNCHRONIZATION INPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 7.4 - HORIZONTAL SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 7.5 - VERTICAL SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7.6 - EW DRIVE SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.7 - DYNAMIC CORRECTION OUTPUT SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.8 - DC/DC CONTROLLER SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.9 - MISCELLANEOUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8 - TYPICAL OUTPUT WAVEFORMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 9 - I C BUS CONTROL REGISTER MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - OPERATING DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1 -SUPPLY AND CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 22 26 26 10.1.1 -Power supply and voltage references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 10.1.2 -I2C Bus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 10.2 -SYNC. PROCESSOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 10.2.1 -Synchronization signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.2 -Sync. presence detection flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.3 -MCU controlled sync. selection mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.4 -Automatic sync. selection mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3 -HORIZONTAL SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 27 27 27 27 10.3.1 -General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3.2 -PLL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3.3 -Voltage controlled oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3.4 -PLL2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3.5 -Dynamic PLL2 phase control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3.6 -Output Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3.7 -Soft-start and soft-stop on H-drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3.8 -Horizontal moiré cancellation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4 -VERTICAL SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 27 29 29 29 30 30 30 31 10.4.1 -General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 10.4.2 -Vertical moiré . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 10.5 -EW DRIVE SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 10.6 -DYNAMIC CORRECTION OUTPUT SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 10.6.1 -Vertical dynamic correction output VDyCor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 10.7 -DC/DC CONTROLLER SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3. . . 35 10.8 -MISCELLANEOUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 10.8.1 -Safety functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2/47 10.8.2 -Soft start and soft stop functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.8.3 -X-ray protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.8.4 -Composite output HLckVBk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - INTERNAL SCHEMATICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 - PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 37 39 41 45 3/47 TDA9116 1 - GLOSSARY AC Alternate Current ACK ACKnowledge bit of I2C-bus transfer AGC Automatic Gain Control COMP COMParator CRT Cathode Ray Tube DC Direct Current EHT Extra High Voltage EW East-West H/W HardWare HOT Horizontal Output Transistor I2C Inter-Integrated Circuit IIC Inter-Integrated Circuit MCU Micro-Controller Unit NAND Negated AND (logic operation) NPN Negative-Positive-Negative OSC OSCillator PLL Phase-Locked Loop PNP Positive-Negative-Positive REF REFerence RS, R-S Reset-Set S/W SoftWare TTL Transistor Transistor Logic VCO Voltage-Controlled Oscillator 4/47 TDA9116 2 - PIN CONFIGURATION H/HVSyn VSyn HLckVBk HOscF HPLL2C CO HGND RO HPLL1F HPosF HMoiré HFly RefOut BComp BRegIn BISense 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VDyCor SDA SCL Vcc BOut GND HOut XRay EWOut VOut VCap VGND VAGCCap VOscF VEHTIn HEHTIn 5/47 HPLL1F R0 10 9 8 H-sync detection Polarity handling C0 HOscF Horizontal VCO Phase/frequency comparator 3 PLL1 V-blank H-lock HFly HPLL2C 12 5 Phase comparator Phase shifter H duty controller Horizontal position Lock detection HLckVBk 4 6 Pin cushion asymm. Parallelogram Hor. duty cycle Int. H-moiré ctrl. Ext. H-moiré / DC ctrl. PLL2 H-moiré amplitude Control voltage level SDA 31 SCL 30 Vcc 29 RefOut I2C Bus interface 13 Supply supervision Reference generation Functions controlled via I2C 2 VSyn 21 VGND XRay 28 BOut 16 BISense 15 BRegIn 14 BComp 11 HMoiré 24 EWOut B+ DC/DC converter controller 22 H size Pin cushion Keystone Top corners Bottom corners Vertical size Vertical position Vertical moiré S-correction C-correction 20 EW generator V-ramp control Tracking EHT Vertical oscillator with AGC 19 25 VDyCor amplitude 27 V-sync detection Input selection Polarity handling Safety processor Geometry tracking Internal ref. GND HOut Bus V-dynamic correction (focus, bright.) V-sync extraction & detection 26 B+ ref. I2C Bus registers : H-drive buffer 32 VOscF VCap VDyCor VAGCCap 23 18 17 VOut VEHTIn HEHTIn TDA9116 TDA9116 1 HPosF 7 3 - BLOCK DIAGRAM 6/47 H/HVSyn HGND TDA9116 4 - PIN FUNCTION REFERENCE Pin Name Function 1 H/HVSyn TTL compatible Horizontal / Horizontal and Vertical Sync. input 2 VSyn TTL compatible Vertical Sync. input 3 HLckVBk Horizontal PLL1 Lock detection and Vertical early Blanking composite output 4 HOscF High Horizontal Oscillator sawtooth threshold level Filter input 5 HPLL2C Horizontal PLL2 loop Capacitive filter input 6 CO Horizontal Oscillator Capacitor input 7 HGND Horizontal section GrouND 8 RO Horizontal Oscillator Resistor input 9 HPLL1F Horizontal PLL1 loop Filter input 10 HPosF Horizontal Position Filter and soft-start time constant capacitor input 11 HMoiré Horizontal Moiré / adjustable DC voltage output 12 HFly Horizontal Flyback input 13 RefOut Reference voltage Output 14 BComp B+ DC/DC error amplifier (Comparator) output 15 BRegIn Regulation feedback Input of the B+ DC/DC converter controller 16 BISense B+ DC/DC converter current (I) Sense input 17 HEHTIn Input for compensation of Horizontal amplitude versus EHT variation 18 VEHTIn Input for compensation of Vertical amplitude versus EHT variation 19 VOscF Vertical Oscillator sawtooth low threshold Filter (capacitor to be connected to VGND) 20 VAGCCap Input for storage Capacitor for Automatic Gain Control loop in Vertical oscillator 21 VGND Vertical section GrouND 22 VCap Vertical sawtooth generator Capacitor 23 VOut Vertical deflection drive Output for a DC-coupled output stage 24 EWOut E/W Output 25 XRay X-Ray protection input 26 HOut Horizontal drive Output 27 GND Main GrouND 28 BOut B+ DC/DC converter controller Output 29 Vcc Supply voltage 30 SCL I2C bus Serial CLock Input 31 SDA I2C bus Serial DAta input/output 32 VDyCor Vertical Dynamic Correction output 7/47 TDA9116 5 - QUICK REFERENCE DATA Characteristic General Package Supply voltage Supply current Application category Means of control/Maximum clock frequency EW drive DC/DC converter controller Adjustable DC level output Horizontal section Frequency range Autosync frequency ratio (can be enlarged in application) Positive/Negative polarity of horizontal sync signal/Automatic adaptation Duty cycle range of the drive signal Position adjustment range with respect to H period Soft start/Soft stop feature Hardware/Software PLL lock indication Parallelogram Pin cushion asymmetry correction (also called Side pin balance) Top/Bottom/Common corner asymmetry correction Tracking of asymmetry corrections with vertical size & position Horizontal moiré cancellation (int./ext.) for Combined/Separated architecture Vertical section Frequency range Autosync frequency range (150nF at VCap and 470nF at VAGCCap) Positive/Negative polarity of vertical sync signa/Automatic adaptationl S-correction/C-correction/Super-flat tube characteristic Vertical size/Vertical position adjustment Vertical moiré cancellation (internal) Vertical breathing compensation EW section Pin cushion correction Keystone correction Top/Bottom/Common corner correction Horizontal size adjustment Tracking of EW waveform with Frequency/Vertical size & position Breathing compensation on EW waveform Dynamic correction section (dyn. focus, dyn. brightness,...) Vertical dynamic correction output Horizontal dynamic correction output Composite HV dynamic correction output Tracking of vertical waveform with V. size & position DC/DC controller section Step-up/Step-down conversion mode Internal/External sawtooth configuration Bus-controlled output voltage Soft start/Soft stop feature Positive(N-MOS)/Negative(P-MOS) polarity of BOut signal 8/47 Value SDIP 32 12 65 Mid-range I2C bus/400 Yes Yes Yes Unit V mA kHz 15 to 150 4.28 Yes/Yes/Yes 30 to 65 ±10 Yes/Yes Yes/Yes Yes Yes No/No/No Yes Yes/Yes kHz 35 to 200 50 to 180 Yes/Yes/Yes Yes/Yes/Yes Yes/Yes Yes Yes Hz Hz Yes Yes Yes/Yes/No Yes Yes/Yes Yes Yes No No Yes Yes/Yes No/Yes Yes Yes/Yes Yes/Yes % % TDA9116 6 - ABSOLUTE MAXIMUM RATINGS All voltages are given with respect to ground. Symbol Currents flowing from the device (sourced) are signed negative. Currents flowing to the device are signed positive. Parameter Value Min Max Unit VCC Supply voltage (pin Vcc) -0.4 13.5 V V(pin) Pins HEHTIn, VEHTIn, XRay, HOut, BOut Pins H/HVSyn, VSyn, SCL, SDA Pins HLckVBk, CO, RO, HPLL1F, HPosF, HMoiré, BRegIn, BISense, VAGCCap, VCap, VDyCor, HOscF, VOscF Pin HPLL2C Pin HFly -0.4 -0.4 -0.4 VCC 5.5 VRefO V V V -0.4 -0.4 VRefO/2 VRefO V V -2000 2000 V -40 150 °C 150 °C VESD ESD susceptibility (human body model: discharge of 100pF through 1.5kΩ) Tstg Storage temperature Tj Junction temperature 9/47 TDA9116 7 - ELECTRICAL PARAMETERS AND OPERATING CONDITIONS The medium (middle) value of an I2C Bus control or adjustment register composed of bits D0, D1,...,Dn is the one having Dn at "1" and all other bits at "0". The minimum value is the one with all bits at 0, maximum value is the one with all at "1". Currents flowing from the device (sourced) are signed negative. Currents flowing to the device are signed positive. TH is the period of horizontal deflection. 7.1 - THERMAL DATA Symbol Tamb Rth(j-a) Value Parameter Min. Operating ambient temperature Typ. 0 Junction-ambience thermal resistance Max. 70 65 Unit °C °C/W 7.2 - SUPPLY AND REFERENCE VOLTAGES Tamb = 25°C Symbol Parameter Test Conditions VCC Supply voltage at Vcc pin ICC Supply current to Vcc pin VCC = 12V VRefO Reference output voltage at RefOut pin VCC = 12V, IRefO= -2mA IRefO Current sourced by RefOut output Value Min. 10.8 Typ. Max. 12 13.2 65 7.65 7.9 -5 Units V mA 8.2 V 0 mA 7.3 - SYNCHRONIZATION INPUTS Vcc = 12V, Tamb = 25°C Symbol Parameter Value Test Conditions Min. Typ. Units Max. VLoH/HVSyn LOW level voltage on H/HVSyn 0 VHiH/HVSyn HIGH level voltage on H/HVSyn 2.2 5 V 0 0.8 V VLoVSyn LOW level voltage on VSyn VHiVSyn HIGH level voltage on VSyn 2.2 RPdSyn Internal pull-down on H/HVSyn, VSyn 100 tPulseHSyn H sync. pulse duration on H/HVSyn pin 0.5 tPulseHSyn/TH tPulseVSyn tPulseVSyn/TV Proportion of H sync pulse to H period Pin H/HVSyn V sync. pulse duration Pins H/HVSyn, VSyn Proportion of V sync pulse to V period Pins H/HVSyn, VSyn V 5 V 250 kΩ µs 0.2 750 µs 0.15 textrV/TH 0.21 tHPolDet Polarity detection time (after change) 0.75 10/47 175 0.5 Proportion of sync pulse length to H peri- Pin H/HVSyn, od for extraction as V sync pulse cap. on pin CO = 820pF Pin H/HVSyn 0.8 0.3 ms TDA9116 7.4 - HORIZONTAL SECTION Vcc = 12V, Tamb = 25°C Symbol Parameter Test Conditions Value Min. Typ. Max. Units PLL1 IRO Current load on RO pin CCO Capacitance on CO pin fHO Frequency of hor. oscillator fHO(0) fHOCapt 1.5 390 Free-running frequency of hor. oscill. (1) Hor. PLL1 capture frequency (4) ∆f HO ( 0 ) ---------------------------f HO ( 0 ) ⋅ ∆T Temperature drift of free-running freq. (3) ∆fHO/∆VHO Average horizontal oscillator sensitivity VHO RRO=5.23kΩ, CCO=820pF 27 fHO(0) = 28.5kHz 29 pF 28.5 150 kHz 29.9 kHz 122 kHz -150 fHO(0) = 28.5kHz VHOThrfr H. oscill. control voltage on pin HPLL1F VRefO=8V Threshold on H. oscill. control voltage on V =8V HPLL1F pin for tracking of EW with freq. RefO VHPosF Control voltage on HPosF pin ppm/°C 19.6 1.4 HPOS (Sad01): 1111111xb 1000000xb 0000000xb mA kHz/V 6.0 V 5.0 V 2.8 3.4 4.0 V V V VHOThrLo Bottom of hor. oscillator sawtooth(6) 1.6 V VHOThrHi Top of hor. oscillator sawtooth(6) 6.4 V PLL2 RIn(HFly) IInHFly VThrHFly VS(0) Input impedance on HFly input V(HFly) >VThrHFly (2) Current into HFly input At top of H flyback pulse Voltage threshold on HFly input 300 0.6 No PLL2 phase modulation H flyback lock middle point(6) 500 700 Ω 5 mA 0.7 V 4.0 V VBotHPLL2C Low clamping voltage on HPLL2C pin(5) 1.6 V VTopHPLL2C High clamping voltage on HPLL2C pin(5) 4.0 V tph(min)/TH Min. advance of H-drive OFF before middle of H flyback(7) Null asym. correction 0 % tph(max)/TH Max. advance of H-drive OFF before middle of H flyback(8) Null asym. correction 44 % H-drive output on pin HOut IHOut tHoff/TH Current into HOut output Output driven LOW 30 mA Duty cycle of H-drive signal HDUTY (Sad00): x1111111b x0000000b Soft-start/Soft-stop value 27 65 85 % % % HPOS (Sad01): 1111111xb 0000000xb +11 -11 % % Picture geometry corrections through PLL1 & PLL2 tHph/TH H-flyback (center) static phase vs. sync signal (via PLL1), see Figure 7 11/47 TDA9116 Symbol Parameter tPCAC/TH Contribution of pin cushion asymmetry correction to phase of H-drive vs. static phase (via PLL2), measured in corners Test Conditions Value Min. Typ. Max. Units PCAC (Sad11h) full span (9) VPOS at medium VSIZE at minimum VSIZE at medium VSIZE at maximum ±1.0 ±1.8 ±2.8 % % % ±1.75 ±2.2 ±2.8 % % % ±1.75 % PARAL (Sad12h) full span (9) tParalC/TH Contribution of parallelogram correction to phase of H-drive vs. static phase (via PLL2), measured in corners VPOS at medium VSIZE at minimum VSIZE at medium VSIZE at maximum VPOS at max. or min. VSIZE at minimum Note 1: Frequency at no sync signal condition. For correct operation, the frequency of the sync signal applied must always be higher than the free-running frequency. The application must consider the spread of values of real electrical components in RRO and CCO positions so as to always meet this condition. The formula to calculate the free-running frequency is fHO(0)=0.12125/(RRO CCO) Note 2: Base of NPN transistor with emitter to ground is internally connected on pin HFly through a series resistance of about 500Ω and a resistance to ground of about 20kΩ. Note 3: Evaluated and figured out during the device qualification phase. Informative. Not tested on every single unit. Note 4: This capture range can be enlarged by external circuitry. Note 5: The voltage on HPLL2C pin corresponds to immediate phase of leading edge of H-drive signal on HOut pin with respect to internal horizontal oscillator sawtooth. It must be between the two clamping levels given. Voltage equal to one of the clamping values indicates a marginal operation of PLL2 or non-locked state. Note 6: Internal threshold. See Figure 10. Note 7: The tph(min)/TH parameter is fixed by the application. For correct operation of asymmetry corrections through dynamic phase modulation, this minimum must be increased by maximum of the total dynamic phase required in the direction leading to bending of corners to the left. Marginal situation is indicated by reach of VTopHPLL2C high clamping level by waveform on pin HPLL2C. Also refer to Note 5 and Figure 10. Note 8: The tph(max)/TH parameter is fixed by the application. For correct operation of asymmetry corrections through dynamic phase modulation, this maximum must be reduced by maximum of the total dynamic phase required in the direction leading to bending of corners to the right. Marginal situation is indicated by reach of VBotHPLL2C low clamping level by waveform on pin HPLL2C. Also refer to Note 5 and Figure 10 . Note 9: All other dynamic phase corrections of picture asymmetry set to their neutral (medium) positions. 7.5 - VERTICAL SECTION VCC = 12V, Tamb = 25°C Symbol Parameter Test Conditions Value Min. Typ. Max. Units AGC-controlled vertical oscillator sawtooth; VRefO = 8V Ext. load resistance on VAGCCap pin(10) DVamp/Vamp(R=∞) <1% VVOB Sawtooth bottom voltage on VCap pin(11) No load on VOscF pin(11) VVOT Sawtooth top voltage on VCap pin AGC loop stabilized V sync present No V sync RL(VAGCCap) 12/47 65 MΩ 2 V 5 4.9 V V TDA9116 Symbol Parameter Test Conditions Value Min. Typ. Max. Units tVODis Sawtooth Discharge time CVCap=150nF 80 µs fVO(0) Free-running frequency CVCap=150nF 100 Hz AGC loop capture frequency CVCap=150nF Sawtooth non-linearity(12) AGC loop stabilized, (12) 0.5 % S-correction range AGC loop stabilized, (13) tVR=1/4 TVR(15) tVR=3/4 TVR -5 +5 % % DV VOC – cor --------------------------------V VOamp C-correction range AGC loop stabilized, (14) tVR=1/2 TVR(15) CCOR(Sad0A): x0000000b x1000000b x1111111b -3 0 +3 % % % DV VOamp ---------------------------------------V VOamp ⋅ ∆f VO Frequency drift of sawtooth amplitude(17)(18) AGC loop stabilized fVOCapt(min)<fVO<fVOCapt(max) 200 ppm/ Hz fVOCapt DV VOdev --------------------------------V ( 16 ) 50 185 Hz VOamp DV VOS – cor --------------------------------V VOamp Vertical output drive signal (on pin VOut);VRefO = 8V Vmid(VOut) Vamp VoffVOut Middle point on VOut sawtooth VPOS (Sad08): x0000000b x1000000b x1111111b Amplitude of VOut sawtooth (peak-to-peak voltage) VSIZE (Sad07): x0000000b x1000000b x1111111b 3.3 3.65 3.2 3.5 3.8 V V V 2.5 3.5 2.25 3.0 3.75 V V V Level on VOut pin at V-drive "off" I2Cbit VOutEn at 0 3.8 V IVOut Current delivered by VOut output -5 5 mA VVEHT Control input voltage range on VEHTIn pin 1 VRefO V ∆V amp ----------------------------------------V amp ⋅ ∆V VEHT Breathing compensation VVEHT>VRefO VVEHT(min)<VVEHT<VRefO 0 2.5 %/V %/V Note 10: Value of acceptable cumulated parasitic load resistance due to humidity, AGC storage capacitor leakage, etc., for less than 1% of Vamp change. Note 11: The threshold for VVOB is generated internally and routed to VOscF pin. Any DC current on this pin will influence the value of VVOB. Note 12: Maximum of deviation from an ideally linear sawtooth ramp at null SCOR (Sad09 at x0000000b) and null CCOR (Sad0A at x1000000b). The same rate applies to V-drive signal on VOut pin. Note 13: Maximum SCOR (Sad09 at x1111111b), null CCOR (Sad0A at x1000000b). Note 14: Null SCOR (Sad09 at x0000000b). Note 15: "tVR" is time from the beginning of vertical ramp of V-drive signal on VOut pin. "TVR" is duration of this ramp, see chapter TYPICAL OUTPUT WAVEFORMS and Figure 13. Note 16: VVOamp = VVOT -VVOB Note 17: The same rate applies to V-drive signal on VOut pin. Note 18: Informative, not tested on each unit. 13/47 TDA9116 7.6 - EW DRIVE SECTION VCC = 12V, Tamb = 25°C Symbol Parameter Test Conditions Value Min. Typ. Max. Units Output voltage on EWOut pin 1.8 6.5 V IEWOut Current sourced by EWOut output -1.5 0 mA VHEHT Control voltage range on HEHTIn pin 1 VRefO V VEW (19)(22)(23)(30) tVR=1/2 TVR(15) VEW-DC DC component of the EW-drive signal on EWOut pin HSIZE (Sad10h): 0000000xb 1000000xb 1111111xb Breathing compensation on VEW-DC tVR=1/2 TVR(15) VHEHT>VRefO VHEHT(min)<VHEHT<VRefO 2 3.25 4.5 V V V 0 -0.125 V/V V/V 100 ppm/°C 0 0.7 1.5 V V V 0.25 0.5 V V (19)(20)(21)(22) ∆V EW – DC ---------------------------∆V HEHT ∆V EW – DC ------------------------------------V EW – DC ⋅ ∆T Temperature drift of DC compo- t =1/2 T (15) VR VR nent of the EW-drive signal on Notes (18)(19)(21)(23)(30) EWOut pin (19)(20)(21)(23)(24)(25)(26)(30) VEW-PCC Pin cushion correction component of the EW-drive signal on EWOut pin VSIZE at maximum PCC (Sad0C): x0000000b x1000000b x1111111b Tracking with VSIZE : PCC at x1000000b VSIZE (Sad07): x0000000b x1000000b (19)(20)(21)(24)(27)(29)(30) V EW – PCC [ t vr = 0 ] Tracking of PCC component of the EW-drive signal with vertical ---------------------------------------------------------V EW – PCC [ t vr = T VR ] position adjustment PCC at x1111111b VPOS (Sad08): x0000000b x1111111b 0.52 1.92 (20)(21)(22)(23)(24)(27)(28)(30) VEW-Key Keystone correction component KEYST (Sad0D): of the EW-drive signal on x0000000b EWOut pin x1111111b VEW-TCor Top corner correction component of the EW-drive signal on EWOut pin 0.4 -0.4 V V -1.25 0 +1.25 V V V -1.25 0 +1.25 V V V 0 20 %/V %/V (19)(21)(22)(23)(24)(25)(27)(30) TCC (Sad0E): x0000000b x1000000b x1111111b (19)(20)(22)(23)(24)(26)(27)(30) VEW-BCor Bottom corner correction compo- BCC (Sad0F): nent of the EW-drive signal on x0000000b EWOut pin x1000000b x1111111b ∆V EW VHO>VHOThrfr ----------------------------------------------------------- Tracking of EW-drive signal with VHO(min)<VHO<VHOThrfr V EW [ f max ] ⋅ ∆V HO horizontal frequency(32) 14/47 TDA9116 Symbol ∆V EW – AC ---------------------------------------------------V EW – AC ⋅ ∆V HEHT Parameter Test Conditions Value Min. Typ. Max. Units (25)(26) Breathing compensation on VEW-AC(31) VHEHT>VRefO VHEHT(min)≤VHEHT≤VRefO 0 1.75 %/V %/V Note 19: KEYST at medium (neutral) value. Note 20: TCC at medium (neutral) value. Note 21: BCC at medium (neutral) value. Note 22: PCC at minimum value. Note 23: VPOS at medium (neutral) value. Note 24: HSIZE at minimum value. Note 25: Defined as difference of (voltage at tVR=0) minus (voltage at tVR=1/2 TVR). Note 26: Defined as difference of (voltage at tVR=TVR) minus (voltage at tVR=1/2 TVR). Note 27: VSIZE at maximum value. Note 28: Difference (voltage at tVR=0) minus (voltage at tVR=TVR). Note 29: Ratio "A/B"of parabola component voltage at tVR=0 versus parabola component voltage at tVR=TVR. Note 30: VHEHT>VRefO, VVEHT>VRefO Note 31: VEW-AC is sum of all components other than VEW-DC (contribution of PCC, keystone correction and corner corrections). Note 32: More precisely tracking with voltage on HPLL1F pin which itself depends on frequency at a rate given by external components on PLL1 pins. VEW[fmax] is the value at condition VHO>VHOThrfr. 7.7 - DYNAMIC CORRECTION OUTPUT SECTION VCC = 12V, Tamb = 25°C Symbol Parameter Value Test Conditions Min. Typ. Units Max. Vertical Dynamic Correction output VDyCor IVDyCor Current delivered by VDyCor output VVD-DC DC component of the drive signal on VDyCor output -1.5 RL(VDyCor)=10kΩ 0 mA 4 V 0 0.5 1 V V V 0.6 1.6 V V (23) IVVD-VI V VD – V [ t vr = 0 ] ------------------------------------------------V VD – V [ t vr = T VR ] Amplitude of V-parabola on VDyCor output(34) VSIZE at medium VDC-AMP (Sad15h): x0000000b x1000000b x1111111b VDC-AMP at maximum VSIZE (Sad07): x0000000b x1111111b VDC-AMP at maximum Tracking of V-parabola on VDyCor VPOS (Sad08): output with vertical position (33) x0000000b x1111111b 0.52 1.92 Note 33: Ratio "A/B"of vertical parabola component voltage at tVR=0 versus vertical parabola component voltage at tVR=TVR. Note 34: Unsigned value. Polarity selection by VDyCorPol I2C Bus bit. Refer to section I2C Bus control register map. 15/47 TDA9116 7.8 - DC/DC CONTROLLER SECTION VCC = 12V, Tamb = 25°C Symbol Parameter Value Test Conditions Min. RB+FB AOLG fUGBW IRI IBComp ABISense VThrBIsCurr IBISense Ext. resistance applied between Open loop gain of error amplifier Low frequency(18) on BRegIn input Unity gain bandwidth of error am- (18) plifier on BRegIn input Bias current delivered by regulation input BRegIn Output current capability of BComp HBOutEn = "Enable" -0.5 HBOutEn = "Disable" (35) output. Voltage gain on BISense input kΩ 100 dB 6 MHz -0.2 µA 2.0 0.5 mA mA 3 Threshold voltage on BISense input corresponding to current limitation TBD Input current sourced by BISense input 2.1 V µA -1 Conduction time of the power transistor (38) IBOut Output current capability of BOut output TH - tinh 0 VBOSat Saturation voltage of the internal output IBOut=10mA transistor on BOut VBReg Regulation reference for BRegIn voltage(36) Delay of BOut “Off-to-On” edge after middle of flyback pulse, as part of TH (37) Units Max. 5 BComp output and BRegIn input tBOn tBTrigDel / TH Typ. 10 mA 0.25 V VRefO=8V BREF (Sad03): x0000000b x1000000b x1111111b 3.8 4.9 6.0 V V V BOutPh = "0" 16 % Note 35: A current sink is provided by the BComp output while BOut is disabled: Note 36: Internal reference related to VRefO. The same values to be found on pin BRegIn, while regulation loop is stabilized. Note 37: Only applies to configuration specified in "Test conditions" column, i.e. synchronization of BOut “Off-to-On” edge with horizontal flyback signal. Refer to chapter "DC/DC controller" for more details. Note 38: tinh is about 300ns regardless of the H frequency 16/47 TDA9116 7.9 - MISCELLANEOUS VCC = 12V, Tamb = 25°C Symbol Parameter Value Test Conditions Min. Typ. Units Max. Vertical blanking and horizontal lock indication composite output HLckVBk ISinkLckBk VOLckBk 100 µA 0.1 1.1 5 6 V V V V HMoiMode=0 (internal) HMOIRE (Sad02): x0000000b x1111111b 0 0.04 % % HMoiMode=1 (external) Rext=10kΩ H-moiré pulse amplitude on HMoiré pin HMOIRE (Sad02): x0000000b x1111111b 0.1 2.1 V V 0.1 5 V V 0.1 V 0 3 mV mV (39) Sink current to HLckVBk pin Output voltage on HLckVBk output V.blank No Yes No Yes H.lock Yes Yes No No Horizontal moiré canceller ∆T H ( H – moire ) --------------------------------------TH VAC-HMoiré VDC-HMoiré Modulation of TH by H-moiré function HMoiMode=0 (internal) Rext=10kΩ VOLCTRL (Sad04): x0000000b x1111111b HMoiMode=1 (external) Rext=10kΩ DC level on HMoiré pin Vertical moiré canceller VV-moiré Amplitude of modulation of V-drive signal on VOut pin by vertical moiré. VMOIRE (Sad0Bh): x0000000b x1111111b Protection functions VThrXRay Input threshold on XRay input(40) tXRayDelay Delay time between XRay detection event and protection action 2TH VCCEn VCC value for start of operation at VCC ramp-up(41) 8.5 V VCCDis VCC value for stop of operation at VCC ramp-down(41) 6.5 V Control voltages on HPosF pin for Soft start/stop 7.65 7.9 8.2 V operation(18)(42) VHOn Threshold for start/stop of H-drive signal 1 V VBOn Threshold for start/stop of B-drive signal 1.7 V VHBNorm f Threshold for full operational duty cycle of H-drive and B-drive signals 2.4 VHPos Normal operation Voltage on HPosF pin as function of ad- HPOS (Sad01) justment of HPOS register 0000000xb 1111111xb 4.0 2.8 V V 17/47 TDA9116 Note 39: Current sunk by the pin if the external voltage is higher than one the circuit tries to force. Note 40: The threshold is equal to actual VRefO. Note 41: In the regions of VCC where the device's operation is disabled, the H-drive, V-drive and B+-drive signals on HOut, VOut and BOut pins, resp., are inhibited, the I2C Bus does not accept any data and the XRayAlarm flag is reset. Also see Figure 15 Note 42: See Figure 10 18/47 TDA9116 8 - TYPICAL OUTPUT WAVEFORMS Note (43) Function Vertical Size Sad 07 Pin Byte Waveform x0000000 Vamp(min) x1111111 Vamp(max) Vmid(VOut) VOut Vmid(VOut) 3.5V x0000000 Vertical Position 08 VOut Vmid(VOut) x1000000 Vmid(VOut) x0000000: Null 09 3.5V Vmid(VOut) x1111111 S-correction Effect on Screen 3.5V VVOamp VVOS-cor VOut x1111111: Max. VVOamp 0 ¼TVR ¾TVR TVR t VR VVOamp x0000000 VVOC-cor 0 C-correction 0A VOut x1000000 : Null ½TVR TVR t VR VVOamp VVOamp VVOC-cor x1111111 0 ½TVR TVR t VR 19/47 TDA9116 Function Sad Pin Byte x0000000: Null Vertical moiré amplitude Waveform Vamp (n-1)TV 0B 0000000x Vamp t VEW-DC(min) ½TVR TVR tVR ½TVR TVR tVR EWOut 1111111x VEW-DC(max) 0 0D (n+1)TV nTV 0 Keystone correction t VV-moiré (n-1)TV 10h (n+1)TV nTV VOut x1111111: Max. Horizontal size Effect on Screen x0000000 VEW-key x1111111 VEW-key VEW-DC EWOut VEW-DC VEW-PCC(min) x0000000 Pin cushion correction 0 0C EWOut ½TVR TVR t VR VEW-PCC(max) x1111111 0 ½TVR TVR t VR VEW-TCor(max) x1111111 Top corner correction 0E 0 EWOut ½TVR TVR t VR VEW-TCor(min) x0000000 0 ½TVR TVR t VR VEW-TBot(max) x1111111 Bottom corner correction 0F 0 EWOut ½TVR TVR t VR VEW-TBot(min) x0000000 0 20/47 ½TVR TVR t VR TDA9116 Function Sad Pin Byte Waveform Effect on Screen static phase tParalC(min) x0000000 12h 0 Internal Parallelogram correction tParalC(max) static phase x1111111 0 ½TVR tPCAC(max) x0000000 11h 0 Internal Pin cushion asymmetry correction ½TVR ½TVR VVD-V(max) TVR t VR TVR t VR VDyCorPol=0 VVD-DC 01111111 0 ½TVR VVD-V(max) VDyCor static H-phase static H-phase 0 15h TVR t VR tPCAC(max) x1111111 Vertical dynamic correction amplitude TVR t VR ½TVR x0000000 0 ½TVR VVD-V(max) 11111111 0 ½TVR TVR t VR VVD-DC Application dependent TVR t VR VDyCorPol=1 VVD-DC TVR t VR Note 43: For any H and V correction component of the waveforms on EWOut and VOut pins and for internal waveform for corrections of H asymmetry, displayed in the table, weight of the other relevant components is nullified (minimum for parabola, S-correction, medium for keystone, all corner corrections, C-correction, parallelogram, parabola asymmetry correction, written in corresponding registers). 21/47 TDA9116 9 - I2C BUS CONTROL REGISTER MAP and internally applied with discharge of the vertical oscillator (44). In order to ensure compatibility with future devices, all “Reserved” bits should be set to 0. The device slave address is 8C in write mode and 8D in read mode. Bold weight denotes default value at Power-OnReset. I2C Bus data in the adjustment register is buffered Sad D7 D6 D5 D4 D3 D2 D1 D0 0 0 WRITE MODE (SLAVE ADDRESS = 8C) 00 01 HDutySyncV 1: Synchro. 0: Asynchro. HDUTY 0 0 0 0 HPOS 1 0 0 (Horizontal duty cycle) 0 (Horizontal position) 0 HMOIRE HMoiré 1: Separated 0: Combined 0 0 0 03 B+SyncV 0: Asynchro. 1 0 0 04 Reserved 1 0 05 Reserved Reserved 06 BOutPol 0: Type N Reserved 07 BOutPh 0: H-flyback 1: H-drive 08 EWTrHFr 0: No tracking 09 Reserved 0A Reserved 0B Reserved 0C Reserved 0D Reserved 0E 0F 10 22/47 Reserved Reserved 0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 0 1 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (Keystone correction) 0 0 (Top corner correction) BCC (Bottom corner correction) 0 0 0 0 0 TCC HSIZE 1 0 (Pin cushion correction) 0 KEYST 0 (Vertical moiré amplitude) 0 PCC 0 (C-correction) 0 VMOIRE 0 (S-correction) 0 CCOR 0 (Vertical position) 0 SCOR 0 (Vertical size) 0 VPOS Reserved (Control voltage level) 0 VSIZE 0 (B+reference) 0 VOLCTRL 0 (Horizontal moiré amplitude) 02 BREF 0 0 0 (Horizontal size) 0 Reserved TDA9116 Sad 11 12 D7 Reserved Reserved D6 D5 D4 D3 PCAC 1 0 0 0 PARAL 1 0 0 0 Reserved 14 Reserved VDyCorPol 0: ”∪" 16 XRayReset 0: No effect 1: Reset 17 TV 0: Off(46) VDC-AMP 1 0 VSyncAuto 1: On VSyncSel 0:Comp 1:Sep TH 0: Off(46) TVM 0: Off(46) 0 D0 0 0 0 0 0 0 (Vertical dynamic correction amplitude) 0 SDetReset HMoiMode 0: No effect 0: Internal 1: Reset 1: External THM 0: Off(46) D1 (Parallelogram correction) 13 15 D2 (Pin cushion asymmetry correction) BOHEdge 0: Falling 0 0 0 PLL1Pump 1: Fast 0: Slow PLL1InhEn 1: On HLockEn 1: On HBOutEn 0: Disable VOutEn 0: Disable BlankMode 1: Perm. READ MODE (SLAVE ADDRESS = 8D) XX (45) HLock 0: Locked 1: Not locked VLock 0: Locked 1: Not lock. XRayAlarm 1: On 0: Off Polarity detection HVPol 1: Negative VPol 1: Negative Sync detection VExtrDet 0: Not det. HVDet 0: Not det. VDet 0: Not det. Note 44: With exception of HDUTY and BREF adjustments data that can take effect instantaneously if switches HDutySyncV and B+SyncV are at 0 respectively. Note 45: In Read Mode, the device always outputs data of the status register, regardless of sub address previously selected. Note 46: The TV, TH, TVM and THM bits are for testing purposes and must be kept at 0 by application. Description of I2C Bus switches and flags Write-to bits Sad00/D7 - HDutySyncV Synchronization of internal application of Horizontal Duty cycle data, buffered in I2C Bus latch, with internal discharge of Vertical oscillator 0: Asynchronous mode, new data applied with ACK bit of I2C Bus transfer on this sub address 1: Synchronous mode Sad02/D7 - HMoiré Horizontal Moiré characteristics 0: Adapted to an architecture with EHT generated in deflection section 1: Adapted to an architecture with separated deflection and EHT sections Sad03/D7 - B+SyncV Same as HDutySyncV, applicable for B+ reference data Sad06/D7 - BOutPol Polarity of B+ drive signal on BOut pin 0: adapted to N type of power MOS - high level to make it conductive 1: adapted to P type of power MOS - low level to make it conductive Sad07/D7 - BOutPh Phase of start of B+ drive signal on BOut pin 0: Just after horizontal flyback pulse 1: With one of edges of line drive signal on HOut pin, selected by BOHEdge bit Sad08/D7 - EWTrHFr Tracking of all corrections contained in waveform on pin EWOut with Horizontal Frequency 0: Not active 1: Active Sad15/D7 - VDyCorPol Polarity of Vertical Dynamic Correction waveform (parabola) 0: Concave (minimum in the middle of the parabola) 1: Convex (maximum in the middle of the parabola) 23/47 TDA9116 Sad16/D0 - HLockEn Enable of output of Horizontal PLL1 Lock/unlock status signal on pin HLckVBk 0: Disabled, vertical blanking only on the pin HLckVBk 1: Enabled one on pin VSyn, based on detection mechanism. If both are present, the one coming first is kept. 0: Disabled, selection done according to bit VSyncSel 1: Enabled, the bit VSyncSel has no effect Sad16/D1 - PLL1InhEn Enable of Inhibition of horizontal PLL1 during extracted vertical synchronization pulse 0: Disabled, PLL1 is never inhibited 1: Enabled Sad16/D7 - XRayReset Reset to 0 of XRay flag of status register effected with ACK bit of I2C Bus data transfer into register containing the XRayReset bit. Also see description of the flag. 0: No effect 1: Reset with automatic return of the bit to 0 Sad16/D2 - PLL1Pump Horizontal PLL1 charge Pump current 0: Slow PLL1, low current 1: Fast PLL1, high current Sad16/D3 - HMoiMode Horizontal Moiré Mode. In position “Internal”, the H-moiré signal affects timing of H-drive signal on HOut pin and a DC voltage level adjusted via VOLCTRL I2C Bus register is on pin HMoiré. In position “External”, the H-moiré signal is output on HMoiré pin (without adjustable DC voltage level) and has no effect on H-drive. In both cases, the amplitude of H-moiré signal is adjusted through I2C Bus register HMOIRE. 0: Internal 1: External Sad16/D4 - SDetReset Reset to 0 of Synchronization Detection flags VDet, HVDet and VExtrDet of status register effected with ACK bit of I2C Bus data transfer into register containing the SDetReset bit. Also see description of the flags. 0: No effect 1: Reset with automatic return of the bit to 0 Sad16/D5 - VSyncSel Vertical Synchronization input Selection between the one extracted from composite HV signal on pin H/HVSyn and the one on pin VSyn. No effect if VSyncAuto bit is at 1. 0: V. sync extracted from composite signal on H/HVSyn pin selected 1: V. sync applied on VSyn pin selected Sad16/D6 - VSyncAuto Vertical Synchronization input selection Automatic mode. If enabled, the device automatically selects between the vertical sync extracted from composite HV signal on pin H/HVSyn and the 24/47 Sad17/D0 - BlankMode Blanking operation Mode 0: Blanking pulse starting with detection of vertical synchronization pulse and ending with end of vertical oscillator discharge (start of vertical sawtooth ramp on the VOut pin) 1: Permanent blanking - high blanking level in composite signal on pin HLckVBk is permanent Sad17/D1 - VOutEn Vertical Output Enable 0: Disabled, VoffVOut on VOut pin (see 7.5 Vertical section) 1: Enabled, vertical ramp with vertical position offset on VOut pin Sad17/D2 - HBOutEn Horizontal and B+ Output Enable 0: Disabled, levels corresponding to “power transistor off” on HOut and BOut pins (high for HOut, high or low for BOut, depending on BOutPol bit). 1: Enabled, horizontal deflection drive signal on HOut pin providing that it is not inhibited by another internal event (activated XRay protection). B+ drive signal on BOut pin. Programming the bit to 1 after prior value of 0, will initiate soft start mechanism of horizontal drive and of B+ DC/DC convertor if this is in external sawtooth configuration. Sad17/D3 - BOHEdge Selection of Edge of Horizontal drive signal to phase B+ drive Output signal on BOut pin. Only applies if the bit BOutPh is set to 1, otherwise BOHEdge has no effect. 0: Falling edge 1: Rising edge TDA9116 Sad17/D4,D5,D6,D7 - THM, TVM, TH, TV Test bits. They must be kept at 0 level by application S/W. Read-out flags SadXX/D0 - VDet(47) Flag indicating Detection of V synchronization pulses on VSyn pin. 0: Not detected 1: Detected SadXX/D1 - HVDet (47) Flag indicating Detection of H or HV synchronization pulses applied on H/HVSyn pin. Once the sync pulses are detected, the flag is set and latched. Disappearance of the sync signal will not lead to reset of the flag. 0: Not detected 1: Detected. SadXX/D2 - VExtrDet (47) Flag indicating Detection of Extracted Vertical synchronization signal from composite H+V signal applied on H/HVSyn pin 0: Not detected 1: Detected SadXX/D4 - HVPol Flag indicating Polarity of H or HV synchronization pulses applied on H/HVSyn pin with respect to mean level of the sync signal 0: Positive 1: Negative SadXX/D5 - XRayAlarm Alarm indicating that an event of excessive voltage has passed on XRay pin. Can only be reset to 0 through I2C Bus bit XRayReset or by poweron reset. 0: No excess since last reset of the bit 1: At least one event of excess appeared since the last reset of the bit, HOut inhibited SadXX/D6 - VLock Status of “Locking” or stabilization of Vertical oscillator amplitude to an internal reference by AGC regulation loop. 0: Locked (amplitude stabilized) 1: Not locked (amplitude non-stabilized) SadXX/D7 - HLock Status of Locking of Horizontal PLL1 0: Locked 1: Not locked SadXX/D3 - VPol Flag indicating Polarity of V synchronization pulses applied on VSyn pin with respect to mean level of the sync signal 0: Positive 1: Negative Note 47: This flag, by its value of 1, indicates an event of detection of at least one synchronization pulse since its last reset (by means of the SDetReset I2C Bus bit). This is to be taken into account by application S/W in a way that enough time (at least the period between 2 synchronization pulses of analyzed signal) must be provided between reset of the flag through SDetReset bit and validation of information provided in the flag after readout of status register. 25/47 TDA9116 10 - OPERATING DESCRIPTION 10.1 - SUPPLY AND CONTROL 10.1.1 - Power supply and voltage references The device is designed for a typical value of power supply voltage of 12 V. In order to avoid erratic operation of the circuit at power supply ramp-up or ramp-down, the value of VCC is monitored. See Figure 1 and electrical specifications. At switch-on, the device enters a “normal operation” as the supply voltage exceeds VCCEn and stays there until it decreases bellow VCCDis. The two thresholds provide, by their difference, a hysteresis to bridge potential noise. Outside the “normal operation”, the signals on HOut, BOut and VOut outputs are inhibited and the I2C bus interface is inactive (high impedance on SDA, SCL pins, no ACK), all I2C bus control registers being reset to their default values (see chapter I2C BUS CONTROL REGISTER MAP on page 22). Figure 1. Supply voltage monitoring V(Vcc) VCC VCCEn Disabled hysteresis Normal operation VCCDis Disabled t Internal thresholds in all parts of the circuit are derived from a common internal reference supply VRefO that is lead out to RefOut pin for external fil- tering against ground as well as for external use with load currents limited to IRefO. The filtering is necessary to minimize interference in output signals, causing adverse effects like e.g. jitter. 10.1.2 - I2C Bus Control The I2C bus is a 2 line bi-directional serial communication bus introduced by Philips. For its general description, refer to corresponding Philips I2C bus specification. This device is an I2C bus slave, compatible with fast (400kHz) I2C bus protocol, with write mode slave address of 8C (read mode slave address 8D). Integrators are employed at the SCL (Serial Clock) input and at the input buffer of the SDA (Serial Data) input/output to filter off the spikes of up to 50ns. The device supports multiple data byte messages (with automatic incrementation of the I2C bus subaddress) as well as repeated Start Condition for I2C bus subaddress change inside the I2C bus messages. All I2C bus registers with specified I2C bus subaddress are of WRITE ONLY type, whereas the status register providing a feedback information to the master I2C bus device has no attributed I2C bus subaddress and is of READ ONLY type. The master I2C bus device reads this register sending directly, after the Start Condition, the READ device I2C bus slave address (8D) followed by the register read-out, NAK (No Acknowledge) signal and the Stop Condition. For the I2C bus control register map, refer to chapter I2C BUS CONTROL REGISTER MAP on page 22. 10.2 - SYNC. PROCESSOR 10.2.1 - Synchronization signals The device has two inputs for TTL-level synchronization signals, both with hysteresis to avoid erratic detection and with a pull-down resistor. On H/ HVSyn input, pure horizontal or composite horizontal/vertical signal is accepted. On VSyn input, only pure vertical sync. signal is accepted. Both positive and negative polarities may be applied on either input, see Figure 2. Polarity detector and programmable inverter are provided on each of the two inputs. The signal applied on H/HVSyn pin, after polarity treatment, is directly lead to horizontal part and to an extractor of vertical sync. pulses, working on principle of integration, see Figure 3. 26/47 The vertical sync. signal applied to the vertical deflection processor is selected between the signal extracted from the composite signal on H/HVSyn input and the one applied on VSyn input. The selector is controlled by VSyncSel I2C bus bit. Besides the polarity detection, the device is capable of detecting the presence of sync. signals on each of the inputs and at the output of vertical sync. extractor. The information from all detectors is provided in the I2C bus status register (5 flags: VDet, HVDet, VExtrDet, VPol, HVPol). The device is equipped with an automatic mode (switched on or off by VSyncAuto I2C bus bit) that also uses the detection information. TDA9116 Figure 2. Horizontal sync signal Positive tPulseHSyn TH Negative show in real time the presence or absence of the corresponding sync. signal. They are latched to 1 as soon as a single sync. pulse is detected. In order to reset them to 0 (all at once), a 1 must be written into SDetReset I2C bus bit, the reset action taking effect with ACK bit of the I2C bus transfer to the register containing the SDetReset bit. The detection circuits are then ready to capture another event (pulse). See Note 47. 10.2.2 - Sync. presence detection flags The sync. signal presence detection flags in the status register (VDet, HVDet, VExtrDet) do not Figure 3. Extraction of V-sync signal from H/V-sync signal H/V-sync TH tPulseHsyn Internal Integration textrV Extracted V-sync 10.2.3 - MCU controlled sync. selection mode I2C bus bit VSyncAuto is set to 0. The MCU reads the polarity and signal presence detection flags, after setting the SDetReset bit to 1 and an appropriate delay, to obtain a true information of the signals applied, reads and evaluates this information and controls the vertical signal selector accordingly. The MCU has no access to polarity inverters, they are controlled automatically. See also chapter I2C BUS CONTROL REGISTER MAP on page 22. 10.2.4 - Automatic sync. selection mode I2C bus bit VSyncAuto is set to 1. In this mode, the device itself controls the I2C bus bits switching the polarity inverters (HVPol, VPol) and the vertical sync. signal selector (VSyncSel), using the information provided by detection circuitry. If both extracted and pure vertical sync. signals are present, the one already selected is maintained. No intervention of the MCU is necessary. 10.3 - HORIZONTAL SECTION 10.3.1 - General The horizontal section consists of two PLLs with various adjustments and corrections, working on horizontal deflection frequency, then phase shifting and output driving circuitry providing H-drive signal on HOut pin. Input signal to the horizontal section is output of the polarity inverter on H/ HVSyn input. The device ensures automatically that this polarity be always positive. 10.3.2 - PLL1 The PLL1 block diagram is in Figure 5. It consists of a voltage-controlled oscillator (VCO), a shaper with adjustable threshold, a charge pump with inhi- bition circuit, a frequency and phase comparator and timing circuitry. The goal of the PLL1 is to make the VCO ramp signal match in frequency the sync. signal and to lock this ramp in phase to the sync. signal, with a possibility to adjust a permanent phase offset. On the screen, this offset results in the change of horizontal position of the picture. The loop, by tuning the VCO accordingly, gets and maintains in coincidence the rising edge of input sync. signal with signal REF1, which is derived from the VCO ramp by a comparator with threshold adjustable through HPOS I2C bus control. The coincidence is identified and flagged by lock detection circuit on pin HLckVBk as well as by HLock I2C bus flag. 27/47 TDA9116 The charge pump provides positive and negative currents charging the external loop filter on HPosF pin. The loop is independent of the trailing edge of sync. signal and only locks to its leading edge. By design, the PLL1 does not suffer from any dead band even while locked. The speed of the PLL1 depends on the current value provided by the charge pump. While not locked, the current is very low, to slow down the changes of VCO frequency and thus protect the external power components at sync. signal change. In locked state, the currents are much higher, two different values being selectable via PLL1Pump I2C bus bit to provide a mean to control the PLL1 speed by S/W. Lower values make the PLL1 slower, but more stable. Higher values make it faster and less stable. In general, the PLL1 speed should be higher for high deflection frequencies. The response speed and stability (jitter level) depends on the choice of external components making up the loop filter. A “CRC” filter is generally used (see Figure 4 on page 28). Figure 4. H-PLL1 filter configuration HPLL1F 9 R2 C1 C2 The PLL1 is internally inhibited during extracted vertical sync. pulse (if any) to avoid taking into account missing or wrong pulses on the phase comparator. Inhibition is obtained by forcing the charge pump output to high impedance state. The inhibition mechanism can be disabled through PLL1Pump I2C bus bit. The Figure 7, in its upper part, shows the position of the VCO ramp signal in relation to input sync. pulse for three different positions of adjustment of horizontal position control HPOS. Figure 5. Horizontal PLL1 block diagram Sync Polarity H/HVSyn 1 INPUT INTERFACE Extracted V-sync 28/47 00 0 00 00 00 00 00 00 00 00 00 00 0 00 00 00 00 PLL1InhEn V-sync (extracted) (I2C) Lock Status (pin & I2C) PLL1 HPLL1F R0 C0 HOscF 9 LOCK DETECTOR 8 PLL INHIBITION High CHARGE PUMP COMP VCO HPosF Low REF1 6 PLL1Pump (I2C) HOSC 10 SHAPER HPOS (I2C) 4 TDA9116 Figure 6. Horizontal oscillator (VCO) schematic diagram I0 I0 (PLL1 filter) HPLL1F 9 VHO 4 VHOThrHi 2 + 4 I0 VHOThrLo HOscF + + RS Flip-Flop RO 8 from charge pump VCO discharge control 6 CO VHOThrHi VHOThrLo 10.3.3 - Voltage controlled oscillator The VCO makes part of both PLL1 and PLL2 loops, being an “output” to PLL1 and “input” to PLL2. It delivers a linear sawtooth. Figure 6 explains its principle of operation. The linears are obtained by charging and discharging an external capacitor on pin CO, with currents proportional to the current forced through an external resistor on pin RO, which itself depends on the input tuning voltage VHO (filtered charge pump output). The rising and falling linears are limited by VHOThrLo and VHOThrHi thresholds filtered through HOscF pin. At no signal condition, the VHO tuning voltage is clamped to its minimum (see chapter ELECTRICAL PARAMETERS AND OPERATING CONDITIONS, part horizontal section), which corresponds to the free-running VCO frequency fHO(0). Refer to Note 1 for the formula to calculate this frequency using external components values. The ratio between the frequency corresponding to maximum VHO and the one corresponding to minimum VHO (free-running frequency) is about 4.5. This range can easily be increased in the application. The PLL1 can only lock to input frequencies falling inside these two limits. 10.3.4 - PLL2 The goal of the PLL2 is, by means of phasing the signal driving the power deflection transistor, to lock the middle of the horizontal flyback to a certain threshold of the VCO sawtooth. This internal threshold is affected by geometry phase corrections, like e.g., parallelogram. The PLL2 is much faster than PLL1 to be able to follow the dynamism of this phase modulation. The PLL2 control current (see Figure 7) is significantly increased during discharge of vertical oscillator (during vertical retrace period) to be able to make up for the difference of dynamic phase at the bottom and at the top of the picture. The PLL2 control current is integrated on the external filter on pin HPLL2C to obtain smoothed voltage, used, in comparison with VCO ramp, as a threshold for H-drive rising edge generation. As both leading and trailing edges of the H-drive signal in the Figure 7 must fall inside the rising part of the VCO ramp, an optimum middle position of the threshold has been found to provide enough margin for horizontal output transistor storage time as well as for the trailing edge of H-drive signal with maximum duty cycle. Yet, the constraints thereof must be taken into account while considering the application frequency range and H-flyback duration. The Figure 7 also shows regions for rising and falling edges of the H-drive signal on HOut pin. As it is forced high during the H-flyback pulse and low during the VCO discharge period, no edge during these two events takes effect. The flyback input configuration is in Figure 8. 10.3.5 - Dynamic PLL2 phase control The dynamic phase control of PLL2 is used to compensate for picture asymmetry versus vertical axis across the middle of the picture. It is done by modulating the phase of the horizontal deflection with respect to the incoming video (synchronization). Inside the device, the threshold VS(0) is compared with the VCO ramp, the PLL2 locking the middle of H-flyback to the moment of their match. The dynamic phase is obtained by modulation of the threshold by correction waveforms. Refer to Figure 12 and to chapter TYPICAL OUTPUT WAVEFORMS. The correction waveforms have no effect in vertical middle of the screen (for middle vertical position). As they are summed, their effect on the phase tends to reach maximum span at top and bottom of the picture. As all the components of the resulting correction waveform (linear for parallelogram correction and parabola of 2nd order for Pin cushion asymmetry correction) are 29/47 TDA9116 generated from the output vertical deflection drive waveform, they both track with real vertical amplitude and position (including breathing compensation), thus being fixed on the screen. Refer to I2C BUS CONTROL REGISTER MAP on page 22 for details on I2C bus controls. Figure 7. Horizontal timing diagram 00 00 00 00 00 00 max. 0 0 0 med. 0 0 0 min. 0 0 0 00 00 00 PLL1lock 00 00 00 REF1 00 00 00 0 0 0 (internal) 000 000 VHOThrHi 0 0 0 0 0 0 VHPosF 00 00 00 00 00 00 max. V 00 00 00 00 00 00 S(0) H-Osc med. min. 000 000 (VCO) VHOThrLo0 0 0 0 0 0 000 000 7/8TH 00 00 00 TH 00 00 00 00 00 00 V 000 ThrHFly H-flyback 00 00 00 00 00 00 t S PLL2 + 000 control 00 00 00 current 00 00 00 ON OFF H-drive ON 00 00 00 (on HOut) tHoff 000 0000000000000000000000 forced high forced low 00 00 00 H-drive 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 00 00 region 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tph(max) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 000 H-drive 000000000000000000000 00 00 00 region 000 HPOS (I2C) PLL2 PLL1 H-sync (polarized) tHph min max inhibited tS: HOT storage time Figure 8. HFly input configuration 00 00 00 HFly 12 00 00 00 00 ext. 0 int. 00 ~500Ω ~20kΩ GND 10.3.6 - Output Section The H-drive signal is inhibited (high level) during flyback pulse, and also when VCC is too low, when X-ray protection is activated (XRayAlarm I2C bus flag set to 1) and when I2C bus bit HBOutEn is set to 0 (default position). 30/47 The duty cycle of the H-drive signal is controlled via I2C bus register HDUTY. This is overruled during soft-start and soft-stop procedures (see sub chapter Soft-start and soft-stop on H-drive on page 30 and Figure 10). The PLL2 is followed by a rapid phase shifting which accepts the signal from H-moiré canceller (see sub chapter Horizontal moiré cancellation on page 30) The output stage consists of a NPN bipolar transistor, the collector of which is routed to HOut pin (see Figure 9). Figure 9. HOut configuration 0 00 00 26 00 HOut 0 int. 00 ext. 00 0 Non-conductive state of HOT (Horizontal Output Transistor) must correspond to non-conductive state of the device output transistor. 10.3.7 - Soft-start and soft-stop on H-drive The soft-start and soft-stop procedure is carried out at each switch-on or switch-off of the H-drive signal, either via HBOutEn I2C bus bit or after reset of XRayAlarm I2C bus flag, to protect external power components. By its second function, the external capacitor on pin HPosF is used to time out this procedure, during which the duty cycle of Hdrive signal starts at its maximum (“tHoff/TH for soft start/stop” in electrical specifications) and slowly decreases to the value determined by the control I2C bus register HDUTY (vice versa at soft-stop). This is controlled by voltage on pin HPosF. See Figure 10 and sub chapter Safety functions on page 37. 10.3.8 - Horizontal moiré cancellation The horizontal moiré canceller is intended to blur a potential beat between the horizontal video pixel period and the CRT pixel width, which causes visible moiré patterns in the picture. On pin HMoiré, in position “External” of I2C bus bit HMoiMode, it generates a square line-synchronized waveform with amplitude adjustable through HMOIRE I2C bus control. In position “Internal” of I2C bus bit HMoiMode, it introduces a microscopic indent on horizontal scan lines by injecting little controlled phase shifts to output circuitry of the horizontal section. Their amplitude is adjustable through HMOIRE I2C bus control. Only one H-moiré, internal or external, is generated at a time. In internal H-moiré mode, a DC volt- TDA9116 age adjusted via HMOIRE I2C bus control is output on pin HMoiré for control purposes. The behaviour of horizontal moiré is to be optimised for different deflection design configurations using HMoiré I2C bus bit. This bit is to be kept at 0 for common architecture (B+ and EHT common regulation) and at 1 for separated architecture (B+ and EHT each regulated separately). Figure 10. Control of HOut and BOut at start/stop at nominal V cc minimum value VHPosMin V(HPosF) HPOS (I2C) range VHPosMax maximum value VHBNorm VBOn VHOn Soft start Start HOut Normal operation Start BOut Soft stop Stop BOut Stop HOut t HOut H-duty cycle 100% BOut (positive) B-duty cycle 0% 10.4 - VERTICAL SECTION 10.4.1 - General The goal of the vertical section is to drive vertical deflection output stage. It delivers a sawtooth waveform with an amplitude independent of deflection frequency, on which vertical geometry corrections of C- and S-type are superimposed (see chapter TYPICAL OUTPUT WAVEFORMS). Block diagram is in Figure 11. The sawtooth is obtained by charging an external capacitor on pin VCap with controlled current and by discharging it via transistor Q1. This is controlled by the CONTROLLER. The charging starts when the voltage across the capacitor drops below VVOB threshold. The discharging starts either when it exceeds VVOT threshold or a short time after arrival of synchronization pulse. This time is necessary for the AGC loop to sample the voltage at the top of the sawtooth. The VVOB reference is routed out onto VOscF pin in order to allow for further filtration. The charging current influences amplitude and shape of the sawtooth. Just before the discharge, the voltage across the capacitor on pin VCap is sampled and stored on a storage capacitor connected on pin VAGCCap. During the following ver- tical period, this voltage is compared to internal reference REF (VVOT), the result thereof controlling the gain of the transconductance amplifier providing the charging current. Speed of this AGC loop depends on the storage capacitance on pin VAGCCap. The VLock I2C bus flag is set to 1 when the loop is stabilized, i.e. when the voltage on pin VAGCCap matches VVOT value. On the screen, this corresponds to stabilized vertical size of picture. After a change of frequency on the sync. input, the stabilization time depends on the frequency difference and on the capacitor value. The lower its value, the shorter the stabilization time, but on the other hand, the lower the loop stability. A practical compromise is a capacitance of 470nF. The leakage current of this capacitor results in difference in amplitude between low and high frequencies. The higher its parallel resistance RL(VAGCCap), the lower this difference. When the synchronization pulse is not present, the charging current is fixed. As a consequence, the free-running frequency fVO(0) only depends on the value of the capacitor on pin VCap. It can be roughly calculated using the following formula 31/47 TDA9116 fVO(0) = 150nF C(VCap) I2C bus control, its amplitude through VSIZE I2C bus control. Vertical moiré is superimposed. The biasing voltage for external DC-coupled vertical power amplifier is to be derived from V RefO voltage provided on pin RefOut, using a resistor divider, this to ensure the same temperature drift of mean (DC) levels on both differential inputs and to compensate for spread of VRefO value (and so mean output value) between particular devices. 10.4.2 - Vertical moiré To blur the interaction of deflection lines with CRT mask grid pitch that can generate moiré pattern, the picture position is to be alternated at half-frame frequency. For this purpose, a square waveform at half-frame frequency is superimposed on the output waveform’s DC value. Its amplitude is adjustable through VMOIRE I2C bus control. . 100Hz The frequency range in which the AGC loop can regulate the amplitude also depends on this capacitor. The C- and S-corrections of shape serve to compensate for the vertical deflection system non-linearity. They are controlled via CCOR and SCOR I2C bus controls. Shape-corrected sawtooth with regulated amplitude is lead to amplitude control stage. The discharge exponential is replaced by VVOB level, which, under control of the CONTROLLER, creates a rapid falling edge and a flat part before beginning of new ramp. Mean value of the waveform output on pin VOut is adjusted by means of VPOS Figure 11. Vertical section block diagram Charge current OSC Cap. REF VCap 22 Sampling Discharge VSyn2 Synchro Controller Transconductance amplifier Q1 20 VAGCCap Sampling Capacitance S-correction SCOR (I2C) Polarity CCOR (I2C) C-correction sawtooth discharge 18 VEHTIn 23 VVOB 19 VOscF VMOIRE (I2C) VPOS (I2C) 32/47 VSIZE (I2C) VOut TDA9116 10.5 - EW DRIVE SECTION The goal of the EW drive section is to provide, on pin EWOut, a waveform which, used by an external DC-coupled power stage, serves to compensate for those geometry errors of the picture that are symmetric versus vertical axis across the middle of the picture. The waveform consists of an adjustable DC value, corresponding to horizontal size, a parabola of 2nd order for “pin cushion” correction, a linear for “keystone” correction and independent half-parabolas of 4th order for top and bottom corner corrections. All of them are adjustable via I2C bus, see I2C BUS CONTROL REGISTER MAP on page 22 chapter. Refer to Figure 12, Figure 13 and to chapter TYPICAL OUTPUT WAVEFORMS. The correction waveforms have no effect in the vertical middle of the screen (if the VPOS control is adjusted to its medium value). As they are summed, the resulting waveform tends to reach its maximum span at top and bottom of the picture. The voltage at the EWOut is top and bottom limited (see parameter VEW). According to Figure 13, especially the bottom limitation seems to be critical for maximum horizontal size (minimum DC). Actually it is not critical since the parabola component must always be applied. As all the components of the resulting correction waveform are generated from the output vertical deflection drive waveform, they all track with real vertical amplitude and position (including breathing compensation), thus being fixed vertically on the screen. They are also affected by C- and S-corrections. The sum of components other than DC is affected by value in HSIZE I2C bus control in reversed sense. Refer to electrical specifications for value. The DC value, adjusted via HSIZE control, is also affected by voltage on HEHTIn input, thus providing a horizontal breathing compensation (see electrical specifications for value). The resulting waveform is conditionally multiplied with voltage on HPLL1F, which depends on frequency. Refer to electrical specifications for value and more precision. This tracking with frequency provides a rough compensation of variation of picture geometry with frequency and allows to fix the adjustment ranges of I2C bus controls throughout the operating range of horizontal frequencies. It can be switched off by EWTrHFr I2C bus bit (off by default). The EW waveform signal is buffered by an NPN emitter follower, the emitter of which is directly routed to EWOut output, with no internal resistor to ground. It is to be biased externally. 33/47 TDA9116 Figure 12. Geometric corrections’ schematic diagram VDC-AMP (I2C) Controls: one-quadrant VDyCorPol (I2C) two-quadrant 32 VDyCor Vmid(VOut) 2 VOut 23 Vertical ramp Top parabola generator 2 TCC (I2C) PCC (I2C) Tracking HEHTIn/HSize 17 BCC (I2C) 2 Bottom parabola generator KEYST (I2C) Tracking with Hor Frequency HEHTIn PCAC (I2C) To horizontal dyn. phase control PARAL (I2C) 34/47 HSize 24 EWOut TDA9116 Figure 13. EWOut output waveforms V(EWOut) VEW(max) VEW-DC VEW-TCor VEW-PCC VEW-Key ma xim VEW operating range HSIZE (I2C) um non-authorized region VEW-BCor me diu min m imu m VEW(min) Top Keystone alone PCC alone Bottom Corners alone Breathing compensation VHEHT(min) VRefO V(VCap) V(HEHT) Vertical sawtooth 0 TVR 0 TVR 0 TVR tVR 10.6 - DYNAMIC CORRECTION OUTPUT SECTION 10.6.1 - Vertical dynamic correction output VDyCor A parabola at vertical deflection frequency is available on pin VDyCor. Its amplitude is adjustable via VDC-AMP I2C bus control and polarity controlled via VDyCorPol I2C bus bit. It tracks with real verti- cal amplitude and position (including breathing compensation). It is also affected by C- and S-corrections. The use of the correction waveform is up to the application (e.g. dynamic focus). 10.7 - DC/DC CONTROLLER SECTION The section is designed to control a switch-mode DC/DC converter. A switch-mode DC/DC convertor generates a DC voltage from a DC voltage of different value (higher or lower) with little power losses. The DC/DC controller is synchronized to horizontal deflection frequency to minimize potential interference into the picture. Its operation is similar to that of standard UC3842. The schematic diagram of the DC/DC controller is in Figure 14. The BOut output controls an external switching circuit (a MOS transistor) delivering pulses synchronized on horizontal deflection frequency, the phase of which depends on I2C bus configuration, see the table at the end of this chapter. Their duration depends on feedback provided to the circuit, generally a copy of DC/DC converter output voltage and a copy of current passing through the DC/DC converter circuitry (e.g. current through external power component). The polarity of the output can be controlled by BOutPol I2C bus bit. A NPN transistor open-collector is routed out to the BOut pin. 35/47 TDA9116 During the operation, a sawtooth is to be found on pin BISense, generated externally by the application. According to BOutPh I2C bus bit, the R-S flipflop is set either at H-drive signal edge (rising or falling, depending on BOHEdge I2C bus bit), or a certain delay (tBTrigDel / TH) after middle of H-flyback. The output is set On at the end of a short pulse generated by the monostable trigger. Timing of reset of the R-S flip-flop affects duty cycle of the output square signal and so the energy transferred from DC/DC converter input to its output. A reset edge is provided by comparator C2 if the voltage on pin BISense exceeds the internal threshold VThrBIsCurr. This represents current limitation if a voltage proportional to the current through the power component or deflection stage is available on pin BISense. This threshold is affected by the voltage on pin HPosF, which rises at soft start and descends at soft stop. This ensures self-contained soft control of duty cycle of the output signal on pin BOut. Refer to Figure 10. Another condition for the reset of the R-S flip-flop, OR-ed with the one described before, is that the voltage on pin BISense exceeds the voltage VC1, which depends on the voltage applied on input BISense of the error amplifier O1. The two voltages are compared, and the reset signal generated by the comparator C1. The error amplifier amplifies (with a factor defined by external components) the difference between the input voltage proportional to DC/DC convertor output voltage and internal reference VBReg. The internal reference and so the output voltage is I2C bus adjustable by means of BREF I2C bus control. Both step-up (DC/DC converter output voltage higher than its input voltage) and step-down (output voltage lower than input) are possible. DC/DC controller Off-to-On edge timing BOutPh BOHEdge (Sad07/ D7) 0 Timing of Off-to-On transition on BOut output (Sad17/ D3) don’t care Middle of H-flyback plus tBTrigDel 1 0 Falling edge of H-drive signal 1 1 Rising edge of H-drive signal Figure 14. DC/DC converter controller block diagram BOHEdge BOutPh (I2C) (I2C) H-drive edge Monostable ~500ns H-flyback (+delay) VCC I1 VBReg Feedback I2 N type + O1 - 2R R VC1 - BRegIn + BComp VThrBIsCurr + - 36/47 S BOut Q R HBOutEn BIsense P type BOutPol (I2C) C2 XRayAlarm (I2C) Soft start HPosF C1 I3 TDA9116 10.8 - MISCELLANEOUS 10.8.1 - Safety functions The safety functions comprise supply voltage monitoring with appropriate actions, soft start and soft stop features on H-drive and B-drive signals on HOut and BOut outputs and X-ray protection. For supply voltage supervision, refer to paragraph Power supply and voltage references on page 26 and Figure 1. A schematic diagram putting together all safety functions and composite PLL1 lock and V-blanking indication is in Figure 15. 10.8.2 - Soft start and soft stop functions For soft start and soft stop features for H-drive and B-drive signal, refer to paragraph Soft-start and soft-stop on H-drive on page 30 and sub chapterDC/DC CONTROLLER SECTION on page 35, respectively. See also the Figure 10. Regardless why the H-drive or B-drive signal are switched on or off (I2C bus command, power up or down, X-ray protection), the signals always phase-in and phase-out in the way drawn in the figure, the first to phase-in and last to phase-out being the H-drive signal, which is to better protect the power stages at abrupt changes like switch-on and off. The timing of phase-in and phase-out only depends on the capacitance connected to HPosF pin which is virtually unlimited for this function. Yet it has a dual function (see paragraph PLL1 on page 27), so a compromise thereof is to be found. 10.8.3 - X-ray protection The X-ray protection is activated if the voltage level on XRay input exceeds VThrXRay threshold. As a consequence, the H-drive and B-drive signals on HOut and BOut outputs are inhibited (switched off) after a 2-horizontal deflection line delay provided to avoid erratic excessive X-ray condition detection at short parasitic spikes. The XRayAlarm I2C bus flag is set to 1 to inform the MCU. This protection is latched; it may be reset either by VCC drop or by I2C bus bit XRayReset (see chapter I2C BUS CONTROL REGISTER MAP on page 22). 37/47 TDA9116 Figure 15. Safety functions - block diagram HBOutEn I2C VCCEn VCCDis 29 Vcc HPosF (timing) 10 VCC supervision + SOFT START & STOP _ R XRayReset I2C XRay 25 XRayAlarm Out In VThrXRay S :2 + B-drive inhibit R _ HFly 12 I2C Q H-drive inhibit H-VCO discharge control H-drive inhibition (overrule) + _ VThrHFly V-drive inhibition VOutEn I2C B-drive inhibition BlankMode I2C HlockEn L1=No blank/blank level I2C H-lock detector V-sawtooth discharge Σ HLckVbk 3 L3=L1+L2 L2=H-lock/unlock level R HLock I2C Q S V-sync I2C I2C bit/flag 38/47 Int. signal 3 Pin TDA9116 10.8.4 - Composite output HLckVBk The composite output HLckVBk provides, at the same time, information about lock state of PLL1 and early vertical blanking pulse. As both signals have two logical levels, a four level signal is used to define the combination of the two. Schematic diagram putting together all safety functions and composite PLL1 lock and V-blanking indication is in Figure 15, the combinations, their respective levels and the HLckVBk configuration in Figure 16. The early vertical blanking pulse is obtained by a logic combination of vertical synchronization pulse and pulse corresponding to vertical oscillator discharge. The combination corresponds to the drawing in Figure 16. The blanking pulse is started with the leading edge of any of the two signals, whichever comes first. The blanking pulse is ended with the trailing edge of vertical oscillator discharge pulse. The device has no information about the vertical retrace time. Therefore, it does not cover, by the blanking pulse, the whole vertical retrace period. By means of BlankMode I2C bus bit, when at 1 (default), the blanking level (one of two according to PLL1 status) is made available on the HLckVBk permanently. The permanent blanking, irrespective of the BlankMode I2C bus bit, is also provided if the supply voltage is low (under VCCEn or VCCDis thresholds), if the X-ray protection is active or if the V-drive signal is disabled by VOutEn I2C bus bit. Figure 16. Levels on HLckVBk composite output L1 - No blank/blank level L2 - H-lock/unlock level VCC L1(H)+L2(H) 3 HLckVBk L1(L)+L2(H) ISinkLckBlk L1(H)+L2(L) VOLckBlk L1(L)+L2(L) V-early blanking No Yes No Yes HPLL1 locked Yes Yes No No 39/47 TDA9116 Figure 17. Ground layout recommendations 32 1 2 TDA9116 31 30 3 29 4 28 5 27 6 26 7 25 8 24 9 23 10 22 11 21 12 20 13 19 14 18 15 16 17 40/47 General Ground TDA9116 11 - INTERNAL SCHEMATICS Figure 18. Figure 21. RefOut 12V 13 5V 5 Pins 1-2 H/HVSyn VSyn HPLL2C 200Ω Figure 19. Figure 22. 12V 12V 13 RefOut RefOut 13 C0 6 HLckVBkl 3 Figure 20. Figure 23. 12V 12V RefOut 13 Pin 13 R0 8 HOSCF Pin 4 41/47 TDA9116 Figure 24. Figure 27. 12V HPLL1F 9 HFly 12 Figure 25. Figure 28. 12V RefOut HPosF 10 BComp 14 Figure 26. Figure 29. 12V 5V 5V 12V BRegIn 15 HMoiré 11 42/47 TDA9116 Figure 30. Figure 33. 12V 12V BISense16 VAGCCap 20 Figure 31. Figure 34. 12V VCap 22 12V 18 VEHTIn 17 HEHTIn Figure 32. Figure 35. 12V Pin 13 12V VOSCF 19 VOut 23 43/47 TDA9116 Figure 36. Figure 39. 12V 30 SCL 31SDA 24 EWOut 32 VDyCor Figure 37. 12V XRay 25 Figure 38. 12V 26 HOut 28 BOut 44/47 TDA9116 12 - PACKAGE MECHANICAL DATA 32 PINS - PLASTIC SHRINK E A A1 A2 E1 L C B e B1 Stand-off eA eB D 32 17 1 16 Dimensions Millimeters Inches Min. Typ. Max. Min. Typ. Max. 3.759 5.080 0.140 0.148 0.200 A 3.556 A1 0.508 A2 3.048 3.556 4.572 0.120 0.140 0.180 B 0.356 0.457 0.584 0.014 0.018 0.023 B1 0.762 1.016 1.397 0.030 0.040 0.055 C .203 0.254 0.356 0.008 0.010 0.014 D 27.43 27.94 28.45 1.080 1.100 1.120 E 9.906 10.41 11.05 0.390 0.410 0.435 E1 7.620 8.890 9.398 0.300 0.350 0.370 0.020 e 1.778 0.070 eA 10.16 0.400 eB L 12.70 2.540 3.048 3.810 0.500 0.100 0.120 0.150 45/47 TDA9116 Revision follow-up PRODUCT PREVIEW September 2000 version 2.0 Document created from last version of TDA9113 with changes emphasized in red. In internal schematics, Pin 11 copied from TDA9115. November 23, 2000 version 2.0 correction in pages 11, 14, 17, 20: HPOS and HSIZE were described on 8 bits instead of 7. page 34:the unused current source has been deleted page 36, figure 14: text relative to int./ext. sawtooth has been deleted. January 11, 2001 version 2.1 page 8: value for autosync frequency (4.5) ratio replaced by 4.28 April 10, 2001 version 2.2, page 10: new values for VRefO: 7.65, 7.9, 8.2 (min, typ, max respectively) Page 17: new values for VThrXRay: 7.65, 7.9, 8.2 (min, typ, max respectively) April 18, 2001 version 2.2 page 14: VEW-BCor parameter: in test conditions, sadOE replaced by sadOF PRELIMINARY DATA July 13, 2001 version 3.0 Section 10.4.1 -right column"The higher its value,..." ---> "The lower its value" Section 10.5 -."...at the vertical middle..." ---> "...in the vertical middle..." Section 7.6 -EW DRIVE SECTION parameter "∆VEW/VEW.∆VHO", added [fmax]. and changed value to +20 Note 31: added: “VEW[fmax] is the value at conditionVHO>VHOThrfr”. Section 10.4 - “stabilizing time” changed to “stabilization time” (twice) Section 7.9 - : max values for vertical and horizontal moiré cancellers moved to typ. values DATASHEET October 11, 2001 version 4.0 Section 7.1 -added “Min. Typ. Max.” in Thermal Data table Section 10.5 -.Replaced figure 13: EWOut output waveforms 2 TDA9116 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. 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