STMICROELECTRONICS TDA9109

TDA9109/SN
LOW-COST DEFLECTION PROCESSOR
FOR MULTISYNC MONITORS
PRELIMINARY DATA
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HORIZONTAL
SELF-ADAPTATIVE
DUAL PLL CONCEPT
150kHz MAXIMUM FREQUENCY
X-RAY PROTECTION INPUT
I2C CONTROLS : H-POSITION, FREQUENCY
GENERATOR FOR BURN-IN MODE
VERTICAL
VERTICAL RAMP GENERATOR
50 TO 185Hz AGC LOOP
GEOMETRY TRACKING WITH VPOS & VAMP
I2C CONTROLS :
VAMP, VPOS, S-CORR, C-CORR
DC BREATHING COMPENSATION
I2C GEOMETRY CORRECTIONS
VERTICAL PARABOLA GENERATOR
(Pin Cushion - E/W, Keystone, Corner)
HORIZONTAL DYNAMIC PHASE
(Side Pin Balance & Parallelogram)
VERTICAL DYNAMIC FOCUS
(Vertical Focus Amplitude)
GENERAL
SYNC PROCESSOR
12V SUPPLY VOLTAGE
8V REFERENCE VOLTAGE
HOR. & VERT. LOCK/UNLOCK OUTPUTS
READ/WRITE I 2C INTERFACE
HORIZONTAL AND VERTICAL MOIRE
B+ REGULATOR
- INTERNAL PWM GENERATOR FOR B+
CURRENT MODE STEP-UP CONVERTER
- SOFT START
2
- I C ADJUSTABLEB+ REFERENCE VOLTAGE
- OUTPUT PULSES SYNCHRONIZED ON
HORIZONTAL FREQUENCY
- INTERNALMAXIMUMCURRENT LIMITATION
COMPARED
WITH
THE
TDA9109,
THE TDA9109/SN HAS :
- CORNER CORRECTION,
- HORIZONTAL MOIRÉ,
.
SHRINK32
(Plastic Package)
ORDER CODE : TDA9109/SN
-
B+ SOFT START,
INCREASED MAX.VERTICAL FREQUENCY,
NO HORIZONTAL FOCUS,
NO STEP DOWN OPTION FOR DC/DC CONVERTER,
- NO I2C FREE RUNNING ADJUSTMENT,
- FIXED HORIZONTAL DUTY CYCLE (48%),
- INCREASED MAXIMUM STORAGE TIME
OF THE HORIZONTAL SCANNING TRANSISTOR.
DESCRIPTION
The TDA9109/SN is a monolithic integrated circuit
assembledin 32-pin shrink dual in line plastic package. This IC controls all the functions related to the
horizontal and vertical deflection in multimode or
multi-frequency computer display monitors.
The internal sync processor, combinedwith the very
powerful geometry correction block make the
TDA9109/SN suitable for very high performance
monitors, using very few external components.
The horizontaljitter level is very low. It is particularly
well suited for high-end 15” and 17” monitors.
Combined with the ST7275 Microcontroller family, TDA9206 (Video preamplifier) and STV942x
(On-Screen Display controller) the TDA9109/SN
allows fully I2 C bus controlled computer display
monitors to be built with a reduced number of
external components.
June 1998
This is advance information on a new product now in development or undergoing evaluatio n. Details are subject to change without notice.
1/30
TDA9109/SN
2/30
H/HVIN
1
32
5V
VSYNCIN
2
31
SDA
HLOCKOUT
3
30
SCL
PLL2C
4
29
VCC
C0
5
28
BOUT
R0
6
27
GND
PLL1F
7
26
HOUT
HPOSITION
8
25
XRAY
HMOIRE
9
24
EWOUT
FOCUS-OUT
10
23
VOUT
HGND
11
22
VCAP
HFLY
12
21
VREF
HREF
13
20
VAGCCAP
COMP
14
19
VGND
REGIN
15
18
BREATH
ISENSE
16
17
B+GND
9109SN01.EPS
PIN CONNECTIONS
TDA9109/SN
PIN CONNECTIONS
Pin
Name
1
H/HVIN
Function
TTL compatible Horizontal sync Input (separate or composite)
2
VSYNCIN
3
HLOCKOUT
TTL compatible Vertical sync Input (for separated H&V)
4
PLL2C
5
C0
6
R0
7
PLL1F
8
HPOSITION
9
HMOIRE
10
FOCUSOUT
11
HGND
12
HFLY
Horizontal Flyback Input (positive polarity)
13
HREF
Horizontal Section Reference Voltage (to be filtered)
14
COMP
B+ Error Amplifier Output for frequency compensation and gain setting
15
REGIN
Regulation Input of B+ control loop
16
ISENSE
Sensing of external B+ switching transistor current
17
B+GND
Ground (related to B+ reference adjustment)
18
BREATH
DC Breathing Input Control (compensation of vertical amplitude against EHV variation)
First PLL Lock/Unlock Output (0V unlocked - 5V locked)
Second PLL Loop Filter
Horizontal Oscillator Capacitor
Horizontal Oscillator Resistor
First PLL Loop Filter
Horizontal Position Filter (capacitor to be connected to HGND)
Horizontal Moiré Output (to be connected to PLL2C through a resistor divider)
Vertical Dynamic Focus Output
Horizontal Section Ground
19
VGND
20
VAGCCAP
Vertical Section Ground
21
VREF
Vertical Section Reference Voltage (to be filtered)
22
VCAP
Vertical Sawtooth Generator Capacitor
23
VOUT
Vertical Ramp Output (with frequency independant amplitude and S or C Corrections if any).
It is mixed with vertical position voltage and vertical moiré.
24
EWOUT
26
HOUT
Horizontal Drive Output (internal transistor, open collector)
25
XRAY
X-RAY protection input (with internal latch function)
Memory Capacitor for Automatic Gain Control Loop in Vertical Ramp Generator
27
GND
General Ground (referenced to VCC)
28
BOUT
B+ PWM Regulator Output
29
VCC
Supply Voltage (12V typ)
30
SCL
I2C Clock Input
31
SDA
I2C Data Input
32
5V
9109SN01.TBL
Pin Cushion - E/W Correction Parabola Output
Supply Voltage (5V typ.)
3/30
TDA9109/SN
QUICK REFERENCE DATA
Value
Unit
Horizontal Frequency
15 to 150
kHz
Autosynch Frequency (for given R0 and C0)
1 to 4.5 f0
± Horizontal Sync Polarity Input
YES
Polarity Detection (on both Horizontal and Vertical Sections)
YES
TTL Composite Sync
YES
Lock/Unlock Identification (on both Horizontal 1st PLL and Vertical Section)
YES
I2C Control for H-Position
± 10
XRAY Protection
YES
I2C Horizontal Duty Fixed
48
I2C Free Running Frequency Adjustment
NO
Stand-by Function
YES
Dual Polarity H-Drive Outputs
NO
Supply Voltage Monitoring
YES
PLL1 Inhibition Possibility
NO
Blanking Outputs
NO
%
%
Vertical Frequency
35 to 200
Hz
Vertical Autosync (for 150nF on Pin 22 and 470nF on Pin 20)
50 to 185
Hz
Vertical S-Correction
YES
Vertical C-Correction
YES
Vertical Amplitude Adjustment
YES
DC Breathing Control on Vertical Amplitude
YES
Vertical Position Adjustment
YES
East/West (E/W) Parabola Output (also known as Pin Cushion Output)
YES
E/W Correction Amplitude Adjustment
YES
Keystone Adjustment
YES
Corner Correction
YES
Internal Dynamic Horizontal Phase Control
YES
Side Pin Balance Amplitude Adjustment
YES
Parallelogram Adjustment
YES
Tracking of Geometric Corrections with Vertical Amplitude and Position
YES
Reference Voltage (both on Horizontal and Vertical)
YES
Vertical Dynamic Focus
YES
2
I C Horizontal Dynamic Focus Amplitude Adjustment
NO
I2C Horizontal Dynamic Focus Symmetry Adjustment
NO
I2C Vertical Dynamic Focus Amplitude Adjustment
YES
Detection of Input Sync Type
YES
Vertical Moiré Output
YES
Horizontal Moiré Output
YES
2
I C Controlled Moiré Amplitude
YES
Frequency Generator for Burn-in
YES
2
Fast I C Read/Write
400
B+ Regulation adjustable by I2C
YES
B+ Soft Start
YES
4/30
kHz
9109SN02.TBL
Parameter
2
VSYNCIN
9109SN02.EPS
GND 27
SCL 30
SDA 31
5V 32
VGND 19
VREF 21
XRAY 25
VCC 29
1
H/HVIN
SYNC
PROCESSOR
I2C INTERFACE
RESET
GENERATOR
VREF
SYNC INPUT
SELECT
(1 bit)
PLL1F
HGND 11
HLOCKOUT
6 bits
4
X
Spin Bal
6 bits
X2
SAFETY
PROCESSOR
PHASE
COMPARATOR
12
24
23
TDA9109/SN
AMPVDF
6 bits
HORIZONTAL
MOIRE CANCEL
5 BITS+ON/OFF
18
X
Keyst.
6 bits
X2
E/W
7 bits
X
4
HOUT
BUFFER
26
B+
CONTROLLER
VOUT
BREATH
20
VPOS
7 bits
VERTICAL
OSCILLATOR
RAMP GENERATOR
VAMP
7 bits
H-DUTY
(48%)
B+ Adjust
7 bits
Corner
7 bits
5V
VCC
XRAY
PHASE
SHIFTER
GEOMETRY
TRACKING
VERTICAL
Parallelogram
MOIRE
6 bits
CANCEL
5 BITS+ON/OFF
Forced
Frequency
2 bits
VCO
VSYNC
EWOUT
VAGCCAP
22
S AND C
CORRECTION
6 bits
LOCK/UNLOCK
IDENTIFICATION
PHASE/FREQUENCY
COMPARATOR
H-PHASE (7 bits)
5
R0
VREF
C0
6
HFLY
3
PLL2C
HREF 13
8
HOUT
HSYNC
HPOSITION
7
HMOIRE
10 FOCUS
9
17 BGND
16 ISENSE
15 REGIN
28 B+OUT
14 COMP
TDA9109/SN
BLOCK DIAGRAM
VCAP
5/30
TDA9109/SN
VESD
Tstg
Tj
Toper
Parameter
Supply Voltage (Pin 29)
Supply Voltage (Pin 32)
Max Voltage on Pin 4
Pin 5
Pins 6, 7, 8, 14, 15, 16, 20, 22
Pins 9, 10, 18, 23, 24, 25, 26, 28
Pins 1, 2, 3, 30, 31
ESD susceptibility Human Body Model,100pF Discharge through 1.5kΩ
EIAJ Norm, 200pF Discharge through 0Ω
Storage Temperature
Junction Temperature
Operating Temperature
Value
13.5
5.7
4.0
6.4
8.0
VCC
VDD
2
300
-40, +150
+150
0, +70
Unit
V
V
V
V
V
V
V
kV
V
o
C
o
C
o
C
THERMAL DATA
Symbol
Rth (j-a)
Parameter
Value
Junction-Ambient Thermal Resistance
Max.
Unit
o
65
C/W
9109SN04.TBL
Symbol
VCC
VDD
VIN
9109SN03.TBL
ABSOLUTE MAXIMUM RATINGS
SYNC PROCESSOR
Operating Conditions (VDD = 5V, T amb = 25oC)
Symbol
HsVR
MinD
Mduty
VsVR
VSW
VSmD
VextM
IHLOCKOUT
Parameter
Voltage on H/HVIN Input
Minimum Horizontal Input Pulses Duration
Maximum Horizontal Input Signal Duty Cycle
Voltage on VSYNCIN
Minimum Vertical Sync Pulse Width
Maximum Vertical Sync Input Duty Cycle
Maximum Vertical Sync Width on TTL H/Vcomposite
Sink and Source Current
Test Conditions
Pin 1
Pin 1
Pin 1
Pin 2
Pin 2
Pin 2
Pin 1
Pin3
Min.
0
0.7
Typ.
Max.
5
25
5
0
5
15
750
250
Unit
V
µs
%
V
µs
%
µs
µA
Electrical Characteristics (VDD = 5V, Tamb = 25oC)
Symbol
VINTH
RIN
TfrOut
VHlock
VoutT
Parameter
Horizontal and Vertical Input Logic Level
(Pins 1, 2)
Horizontal and Vertical Pull-Up Resistor
Fall and Rise Time, Output CMOS Buffer
Horizontal 1st PLL Lock Output Status (Pin 3)
Extracted Vsync Integration Time (% of TH)
on H/V Composite (see Note 1)
Test Conditions
Low Level
High Level
Pins 1, 2
Pin 3, COUT = 20pF
Locked, ILOCKOUT = -250µA
Unlocked, I LOCKOUT = +250µA
C0 = 820pF
Min.
Typ.
Max.
0.8
2.2
200
4.4
26
0
5
35
Min.
Typ.
200
0.5
Unit
V
V
kΩ
ns
V
V
%
Note 1 : TH is the horizontal period.
I2C READ/WRITE (see Note 2)
Electrical Characteristics (VDD = 5V,Tamb = 25oC)
Symbol
Parameter
Test Conditions
Max.
Unit
400
kHz
µs
µs
V
V
2
Fscl
Tlow
Thigh
Vinth
VACK
Maximum Clock Frequency
Low period of the SCL Clock
High period of the SCL Clock
SDA and SCL Input Threshold
Acknowledge Output Voltage on SDA input with 3mA
Note 2 : See also I2C Table Control and I2C Sub Address Control.
6/30
Pin 30
Pin 30
Pin 30
Pins 30,31
Pin 31
1.3
0.6
2.2
0.4
9109SN05.TBL
I C PROCESSOR
TDA9109/SN
HORIZONTAL SECTION
Operating Conditions
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
VCO
R0(Min.)
Minimum Oscillator Resistor
Pin 6
6
C0(Min.)
Minimum Oscillator Capacitor
Pin 5
390
F(Max.)
Maximum Oscillator Frequency
kΩ
pF
150
kHz
OUTPUT SECTION
I12m
Maximum Input Peak Current
Pin 12
5
mA
HOI
Horizontal Drive Output Maximum Current
Pin 26, Sunk current
30
mA
Unit
Electrical Characteristics (VCC = 12V, Tamb = 25oC)
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
SUPPLY AND REFERENCE VOLTAGES
VCC
Supply Voltage
Pin 29
10.8
12
13.2
V
VDD
Supply Voltage
Pin 32
4.5
5
5.5
V
ICC
Supply Current
Pin 29
50
mA
IDD
Supply Current
Pin 32
5
mA
VREF-H
Horizontal Reference Voltage
Pin 13, I = -2mA
7.4
8
8.6
VREF-V
Vertical Reference Voltage
Pin 21, I = -2mA
7.4
8
8.6
V
IREF-H
Max. Sourced Current on VREF-H
Pin 13
5
mA
IREF-V
Max. Sourced Current on VREF-V
Pin 21
5
mA
V
1st PLL SECTION
Delay Time for detecting polarity change
(see Note 3)
Pin 1
VVCO
VCO Control Voltage (Pin 7)
VREF-H = 8V
f0
fH(Max.)
1.3
6.2
V
V
Vcog
VCO Gain (Pin 7)
R0 = 6.49kΩ, C 0 = 820pF,
dF/dV = 1/11R0C 0
17.1
kHz/V
Hph
Horizontal Phase Adjustment (see Note 4)
% of Horizontal Period
±10
%
Horizontal Phase Setting Value (Pin 8) (see Note 4)
Minimum Value
Typical Value
Maximum Value
Sub-Address 01
Byte x1111111
Byte x1000000
Byte x0000000
2.8
3.4
4.0
V
V
V
PLL1 Filter Current Charge
PLL1 is Unlocked
PLL1 is Locked
±140
±1
µA
mA
Free Running Frequency
R0 = 6.49kΩ, C 0 = 820pF,
f0 = 0.97/8R0C 0
22.8
kHz
-150
ppm/C
Vbmin
Vbtyp
Vbmax
IPll1U
IPll1L
f0
df0/dT
CR
FF
Notes : 3.
4.
5.
6.
0.75
Free Running Frequency Thermal Drift
(No drift on external components) (see Note 5)
PLL1 Capture Range
Forced Frequency
R0 = 6.49kΩ, C 0 = 820pF,
from f0+0.5kHz to 4.5f0
fH(Min.)
fH(Max.)
FF1 Byte 11xxxxxx
FF2 Byte 10xxxxxx
Sub-Address 02
ms
25
90
kHz
kHz
2f0
3f0
This delay is mandatory to avoid a wrong detection of polarity change in the case of a composite sync.
See Figure 10 for explanation of reference phase.
These parameters are not tested on each unit. They are measured during our internal qualification.
This PLL capture range may be obtained only if f0 is captured (for instance bu adjusting R0). If not, more margin must be provided
between fH (Min.) and f0, to cope with the components spread.
7/30
9109SN05.TBL
HpolT
TDA9109/SN
HORIZONTAL SECTION (continued)
Electrical Characteristics (VCC = 12V, Tamb = 25oC) (continued)
Symbol
Parameter
Test Conditions
Min.
Typ. Max.
Unit
0.65
0.75
V
70
ppm
48
%
2nd PLL SECTION AND HORIZONTAL OUTPUT SECTION
FBth
Flyback Input Threshold Voltage (Pin 12)
Hjit
Horizontal Jitter
HD
Horizontal Drive Output Duty-Cycle
(Pin 26) (see Note 7)
XRAYth
At 31.4kHz
X-RAY Protection Input Threshold Voltage
Pin 25, see Note 8
8
V
Internal Clamping Levels on 2nd PLL
Loop Filter (Pin 4)
Low Level
High Level
1.6
4.0
V
V
VSCinh
Threshold Voltage to Stop H-Out,V-Out,
B-Out and Reset XRAY
when VCC < VSCinh (see Note 8)
Pin 29
7.5
V
VSDinh
Threshold Voltage to Stop H-Out,V-Out,
B-Out and Reset XRAY
when VDD < VSDinh
Pin 32
4.0
V
Horizontal Drive Output (low level)
Pin 26, IOUT = 30mA
Vphi2
HDvd
0.4
V
VERTICAL DYNAMIC FOCUS FUNCTION (positive parabola)
Bottom DC Output Level
TDHDF
DC Output Voltage Thermal Drift (see
Note 5)
RLOAD = 10kΩ, Pin 10
2
V
200
ppm/C
0
0.5
1
VPP
VPP
VPP
Parabola Amplitude Function of VAMP Sub-Address 05
(tracking between VAMP and VDF) with
Byte 10000000
VPOS Typ. (see Figure 1 and Note 9)
Byte 11000000
Byte 11111111
0.6
1
1.5
VPP
VPP
VPP
VHDFKeyt Parabola Asymetry Function of VPOS Sub-Address 06
Control (tracking between VPOS and VDF)
Byte x0000000
with VAMP Max.
Byte x1111111
0.52
0.52
VPP
VPP
AMPVDF
VDFAMP
Vertical Dynamic Focus Parabola
Amplitude with VAMP and VPOS Typical
Min. Byte 000000
Typ. Byte 100000
Max. Byte 111111
Sub-Address 0F
Notes : 5. These parameters are not tested on each unit. They are measured during our internal qualification.
7. Duty Cycle is the ratio between the output transistor OFF time and the period. The power transistor is controlled OFF when the
output transistor is OFF.
7. Initial Condition for Safe Operation Start Up
8. See Figure 14.
9. S and C correction are inhibited so the output sawtooth has a linear shape.
8/30
9109SN05.TBL
HDFDC
TDA9109/SN
VERTICAL SECTION
Operating Conditions
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
6.5
V
OUTPUTS SECTION
VEWM
Maximum E/W Output Voltage
Pin 24
VEWm
Minimum E/W Output Voltage
Pin 24
1.8
V
R LOAD
Minimum Load for less than 1% Vertical Amplitude Drift
Pin 20
65
MΩ
Electrical Characteristics (VCC = 12V, Tamb = 25oC)
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
VERTICAL RAMP SECTION
VRB
Voltage at Ramp Bottom Point
VREF-V = 8V, Pin 22
2
V
VRT
Voltage at Ramp Top Point (with Sync)
VREF-V = 8V, Pin 22
5
V
VRTF
Voltage at Ramp Top Point (without Sync)
Pin 22
VRT-0.1
V
VSTD
Vertical Sawtooth Discharge Time
Pin 22, C22 = 150nF
70
µs
VFRF
Vertical Free Running Frequency
(see Note 10)
C OSC (Pin 22) = 150nF
Measured on Pin22
100
Hz
ASFR
AUTO-SYNC Frequency (see Note 11)
C22 = 150nF ±5%
RAFD
Ramp Amplitude Drift Versus Frequency at C 22 = 150nF
50Hz < f and f < 185Hz
Maximum Vertical Amplitude (see Note 5)
200
ppm/Hz
Ramp Linearity on Pin 22 (see Note 10)
2.5V < V27 and V27 < 4.5V
0.5
%
Vertical Position Adjustment Voltage
(Pin 23 - VOUT mean value)
Sub Address 06
Byte x0000000
Byte x1000000
Byte x1111111
3.3
3.65
3.2
3.5
3.8
V
V
V
Vertical Output Voltage
(peak-to-peak on Pin 23)
Sub Address 05
Byte x0000000
Byte x1000000
Byte x1111111
2.5
3.5
2.25
3
3.75
V
V
V
VOR
VOI
Vertical Output Maximum Current (Pin 23)
dVS
Max Vertical S-Correction Amplitude
(see Note 12)
x0xxxxxx inhibits S-CORR
x1111111 gives max S-CORR
Sub Address 07
Vertical C-Corr Amplitude
x0xxxxxx inhibits C-CORR
Sub Address 08
∆V/VPP @ TV/2
Byte x1000000
Byte x1100000
Byte x1111111
Ccorr
∆V/VPP at TV/4
∆V/VPP at 3TV/4
185
Hz
±5
mA
-4
+4
%
%
-3
0
3
%
%
%
Notes : 5. These parameters are not tested on each unit. They are measured during our internal qualification.
10. With Register 07 at Byte x0xxxxxx (S correction is inhibited) and with Register 08 at Byte x0xxxxxx (C correction is inhibited), the
sawtooth has a linear shape.
11. This is the frequency range for which the vertical oscillator will automatically synchronize, using a single capacitor value on Pin 22
and with a constant ramp amplitude.
12. TV is the vertical period.
9/30
9109SN05.TBL
Rlin
VPOS
50
TDA9109/SN
VERTICAL SECTION (continued)
Electrical Characteristics (VCC = 12V, Tamb = 25oC) (continued)
Symbol
Parameter
Test Conditions
Min.
Typ. Max.
Unit
DC Output Voltage with Typ. VPOS, Keystone and
Corner inhibited
Pin 24, see Figure 2
2.5
V
East/West (E/W) FUNCTION
EWDC
TDEW DC
DC Output Voltage Thermal Drift
See Note 13
100
ppm/C
EWpara
Parabola Amplitude with Max. VAMP, Typ. VPOS,
Keystone and Corner inhibited
Subaddress 0A
Byte 11111111
Byte 11000000
Byte 10000000
1.7
0.85
0
VPP
VPP
VPP
Parabola Amplitude Function of VAMP Control
(tracking between VAMP and E/W) with Typ. VPOS,
Typ. E/W Amplitude, Keystone and Corner inhibited
(see Note 10)
Subaddress 05
Byte 10000000
Byte 11000000
Byte 11111111
0.30
0.55
0.85
VPP
VPP
VPP
Keystone Adjustment Capability with Typ. VPOS,
Corner and E/W inhibited and Max. Vertical
Amplitude (see Note 10 and Figure 4)
Subaddress 09
Byte 1x000000
Byte 1x111111
0.65
0.65
VPP
VPP
Intrinsic Keystone Function of VPO S Control
(tracking between VPOS and E/W) with Max. E/W
Amplitude,Max. Vertical Amplitude and Corner
inhibited (see Note 13 and Figure 2)
A/B Ratio
B/A Ratio
Subaddress 06
Byte x0000000
Byte x1111111
0.52
0.52
Corner Amplitude with Max. VAMP, Typ. VPOS,
Keystone and E/W inhibited
Subaddress 0B
Byte 11111111
Byte 11000000
Byte 10000000
1.7
0
-1.7
VPP
VPP
VPP
Side Pin Balance Parabola Amplitude (Figure 3) with
Max. VAMP, Typ. VPOS and Parallelogram inhibited
(see Notes 10 & 14)
Subaddress 0D
Byte x1111111
Byte x1000000
+1.4
-1.4
%TH
%TH
Side Pin Balance Parabola Amplitude function of
VAMP Control (tracking between VAMP and SPB)
with Max. SPB, Typ. VPOS and Parallelogram
inhibited (see Notes 10 & 14)
Subaddress 05
Byte 10000000
Byte 11000000
Byte 11111111
0.5
0.9
1.4
%TH
%TH
%TH
P ara ll elo gr am A dju st men t Capa bilit y w ith
M ax . V AM P , T yp . VP O S a n d M a x. S PB
(see Notes 10 & 14)
Subaddress 0E
Byte x1111111
Byte x1000000
+1.4
-1.4
%TH
%TH
Intrinsic Parallelogram Function of VPOS Control
( tracki ng be tween VPO S and DHPC) with
Max. VAMP, Max. SPB and Parallelogram inhibited
(see Notes 10 & 14)
A/B Ratio
B/A Ratio
Subaddress 06
EWtrack
KeyAdj
KeyTrack
Corner
INTERNAL DYNAMIC HORIZONTAL PHASE CONTROL
SPBpara
SPBtrack
ParAdj
Partrack
Byte x0000000
Byte x1111111
0.52
0.52
VERTICAL MOIRE
VMOIRE
Vertical Moiré (measured on VOUT : Pin 23)
Subaddress 0C
Byte 01x11111
6
mV
BRRANG
BRADj
DC Breathing Control Range (see Note 15)
V18
Vertical Output Variation versus DC Breathing
Control (Pin 23)
V18 ≥ VREF-V
V18 = 4V
1
12
0
-10
V
%
%
Notes : 10. With Register 07 at Byte x0xxxxxx (S correction is inhibited) and with Register 08 at Byte x0xxxxxx (C correction is inhibited), the
sawtooth has a linear shape.
13. These parameters are not tested on each unit. They are measured during our internal qualification.
14. TH is the horizontal period.
15. When not used the DC breathing control pin must be connected to 12V.
10/30
9109SN05.TBL
BREATHING COMPENSATION
TDA9109/SN
B+ SECTION
Operating Conditions
Symbol
Parameter
Test conditions
FeedRes Minimum Feedback Resistor
Resistor between Pins 15 and 14
Min.
Typ.
Max.
Unit
5
kΩ
Electrical Characteristics (VCC = 12V, Tamb = 25oC)
Parameter
Test conditions
OLG
Error Amplifier Open Loop Gain
ICOMP
Sunk Current on Error Amplifier Pin 14 (see Figure 14)
Output when BO UT is in safety
condition
UGBW
Unity Gain Bandwidth
(see Note 13)
IRI
Regulation Input Bias Current
Current sourced by Pin 15 (PNP base)
EAOI
Error Amplifier Output Current
Current sourced by Pin 14
Current sunk by Pin 14
CSG
Current Sense Input Voltage Gain
Pin 16
MCEth
ISI
Min.
At low frequency (see Note 16)
Max.
Unit
85
dB
0.5
mA
6
MHz
µA
0.2
0.5
2
mA
mA
3
Max Current Sense Input Threshold Pin 16
Voltage
Current Sense Input Bias Current
Typ.
Current sourced by Pin 16 (PNP base)
1.2
V
1
µA
Tonmax
Maximum ON Time of the external % of Horizontal period,
power transistor
f0 = 27kHz (see Note 17)
100
%
B+OSV
B+ Output Saturation Voltage
V28 with I28 = 10mA
0.25
V
Internal Reference Voltage
On erroramp (+) inputfor Subaddress 0B
Byte 1000000
4.8
V
+20
-20
%
%
100
ns
IVREF
VREFADJ
tFB+
I nt e rna l R e fe r en ce
Adjustment Range
V ol tag e Byte 1111111
Byte 0000000
Fall Time
Pin 28
9109SN05.TBL
Symbol
Notes : 13. These parameters are not tested on each unit. They are measured during our internal qualification.
16. These parameters are not tested on each unit. They are measured during our internal qualification procedure which includes
characterization on batches coming from corners of our processes and also temperature characterization.
17. The external power transistor is OFF during about 400ns.
Figure 1 : Vertical Dynamic Focus Function
B
B
A
9109SN03.EPS
A
HDFDC
Figure 3 :
EWPARA
Dynamic Horizontal Phase Control
Output
9109SN04.EPS
VDFAMP
Figure 2 : E/W Output
EWDC
Figure 4 :
Keystone Effect on E/W Output
(PCC and Corner Inhibited)
B
A
DHPCDC
9109SN06.EPS
SPBPARA
9109SN05.EPS
Keyadj
11/30
TDA9109/SN
TYPICAL VERTICAL OUTPUT WAVEFORMS
Function
Sub
Address
Pin
Byte
Specification
VOUTDC
Effect on Screen
2.25V
10000000
Vertical Size
05
23
VOUTDC
3.75V
11111111
Vertical
Position
DC
Control
06
23
VOUTDC = 3.2V
VOUTDC = 3.5V
VOUTDC = 3.8V
x0000000
x1000000
x1111111
0xxxxxxx
Inhibited
Vertical
S
Linearity
07
∆V
23
1x111111
VPP
1x000000
Vertical
C
Linearity
08
VPP
∆V
∆V = 3%
V PP
23
∆V
1x111111
VPP
∆V = 3%
V PP
12/30
9109SN06.TBL / 9109SN07.EPS TO 9109SN13.EPS
∆V = 4%
V PP
TDA9109/SN
GEOMETRY OUTPUT WAVEFORMS
Function
Sub
Address
Pin
Byte
Specification
Effect on Screen
E/W+ Corner
inhibited
Keystone
(Trapezoid)
Control
E/W
(Pin Cushion)
Control
09
1x000000
0.65V
2.5V
1x111111
0.65V
2.5V
2.5V
0V
24
Keystone +
Corner
inhibited
10000000
0A
24
1.7V
11111111
Keystone+
E/W inhibited
1.7V
11111111
Corner
Control
0B
2.5V
24
10000000
1.7V
SPB
inhibited
1x000000
0E
Parallelogram
inhibited
3.7V
1.4% TH
3.7V
1.4% TH
1x000000
0D
Internal
1x111111
Vertical
Dynamic
Focus
1.4% TH
Internal
1x111111
Side Pin
Balance
Control
3.7V
0F
9109SN07.TBL / 9109SN14.EPS TO 9109SN24.EPS
Parrallelogram
Control
10
1.4% TH
3.7V
2V
TV
13/30
TDA9109/SN
I2C BUS ADDRESS TABLE
Slave Address (8C) : Write Mode
Sub Address Definition
D8
D7
D6
D5
D4
D3
D2
D1
0
0
0
0
0
0
0
0
0
Horizontal Drive Selection
1
0
0
0
0
0
0
0
1
Horizontal Position
2
0
0
0
0
0
0
1
0
Forced Frequency
3
0
0
0
0
0
0
1
1
Sync Priority / Horizontal Moiré Amplitude
4
0
0
0
0
0
1
0
0
Refresh / B+ Reference Adjustment
5
0
0
0
0
0
1
0
1
Vertical Ramp Amplitude
6
0
0
0
0
0
1
1
0
Vertical Position Adjustment
7
0
0
0
0
0
1
1
1
S Correction
8
0
0
0
0
1
0
0
0
C Correction
9
0
0
0
0
1
0
0
1
E/W Keystone
A
0
0
0
0
1
0
1
0
E/W Amplitude
B
0
0
0
0
1
0
1
1
E/W Corner Adjustment
C
0
0
0
0
1
1
0
0
Vertical Moiré Amplitude
D
0
0
0
0
1
1
0
1
Side Pin Balance
E
0
0
0
0
1
1
1
0
Parallelogram
F
0
0
0
0
1
1
1
1
Vertical Dynamic Focus Amplitude
Slave Address (8D) : Read Mode
No sub address needed.
14/30
TDA9109/SN
I2C BUS ADDRESS TABLE (continued)
D8
D7
D6
D5
[0]
[0]
D4
D3
D2
D1
[0]
[0]
WRITE MODE
HDrive
0, off
[1], on
00
01
02
03
Xray
1, reset
[0]
Horizontal Phase Adjustment
[1]
Forced Frequency
1, on
1, f0 x 2
[0], off
[0], f0 x 3
Sync
HMoiré
0, Comp
1, on
[1], Sep
[0]
04
Detect
Refresh
[0], off
05
Vramp
0, off
[1], on
06
07
S Select
1, on
[0]
08
C Select
1, on
[0]
09
E/W Key
0, off
[1]
0A
[0]
[0]
Horizontal Moiré Amplitude
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
B+ Reference Adjustment
[1]
[0]
[0]
[0]
Vertical Ramp Amplitude Adjustment
[1]
[0]
[0]
[0]
[0]
[0]
[0]
[1]
[0]
Vertical Position Adjustment
[0]
[0]
[0]
S Correction
[0]
[0]
[1]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
C Correction
[1]
[0]
[0]
[0]
E/W Keystone
[1]
[0]
[0]
[0]
[0]
[1]
[0]
E/W Amplitude
[0]
[0]
[0]
E/W Corner Adjustment
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
0B
E/W Cor
0, off
[1]
[1]
0C
Test V
1, on
[0], off
VMoiré
1, on
[0]
0D
SPB Sel
0, off
[1]
0E
Parallelo
0, off
[1]
0F
Test H
1, on
[0], off
[0]
[0]
[0]
Vertical Moiré Amplitude
[0]
[0]
[0]
Side Pin Balance
[1]
[0]
[0]
[0]
Parallelogram
[1]
[0]
[1]
[0]
[0]
[0]
Vertical Dynamic Focus Amplitude
[0]
[0]
READ MODE
Hlock
0, on
[1], no
Vlock
0, on
[1], no
Xray
1, on
[0], off
Polarity Detection
V pol
H/V pol
[1], negative [1], negative
Vext det
[0], no det
Sync Detection
H/V det
V det
[0], no det
[0], no det
[ ] initial value
Data is transferred with vertical sawtooth retrace.
We recommend to set the unspecified bit to [0] in order to assure the compatibility with future devices.
15/30
TDA9109/SN
OPERATING DESCRIPTION
I - GENERAL CONSIDERATIONS
I.1 - Power Supply
The typical values of the power supply voltages
VCC and VDD are 12V and 5V respectively. Optimum operation is obtained for VCC between 10.8
and 13.2V and VDD between 4.5 and 5.5V.
Inorderto avoiderraticoperationof thecircuit during
the transient phase of VCC and VDD switching on, or
off, the value of VCC and VDD are monitored : if VCC
is less than 7.5V typ. or if VDD is less than 4.0V typ.,
the outputs of the circuit are inhibited.
Similarly, beforeVDD reaches4V, all the I2C register
are reset to their default value.
In order to have very good power supply rejection,
the circuit is internally supplied by several voltage
references (typ. value : 8V). Two of these voltage
references are externally accessible, one for the
vertical and one for the horizontal part. They can be
used to bias external circuitry (if ILOAD is less than
5mA). It is necessary to filter the voltagereferences
by externalcapacitorsconnectedto ground,in order
to minimize the noise and consequently the ”jitter”
on vertical and horizontal output signals.
I.2 - I2C Control
TDA9109/SN belongs to the I 2C controlled device
family. Instead of being controlled by DC voltages
on dedicated control pins, each adjustment can be
done via the I2C Interface.
The I2C bus is a serial bus with a clock and a data
input. Thegeneral functionand thebus protocolare
specified in the Philips-bus data sheets.
Theinterface (Data and Clock)is a comparatorwith
hysteresis ; the thresholds(less then 2.2V on rising
edge, more than 0.8V on falling edge with 5V
supply) are TTL-compatible. Spikes of up to 50ns
are filtered by an integrator and the maximum clock
speed is limited to 400kHz.
The data line (SDA) can be used bidirectionally.
In read-mode the IC sends reply information
(1 byte) to the micro-processor.
The bus protocol prescribes a full-byte transmission in all cases. The first byte after the start
condition is used to transmit the IC-address
(hexa 8C for write, 8D for read).
16/30
I.3 - Write Mode
In write mode the second byte sent contains the
subaddress of the selected function to adjust (or
controlsto affect)and the thirdbyte the corresponding data byte. It is possible to send more than one
data byte to the IC. If after the third byte no stop or
start condition is detected, the circuit increments
automatically by one the momentary subaddressin
the subaddress counter (auto-increment mode).
So it is possible to transmit immediately the following data bytes without sending the IC address or
subaddress.This can be useful to reinitialize all the
controls very quickly (flash manner). This procedure can be finished by a stop condition.
The circuit has 14 adjustment capabilities : 1 for the
horizontal part, 4 for the vertical, 2 for the E/W
correction, 2 for the dynamic horizontal phase control,1 for the Moiré option, 3 for the horizontal and
the vertical dynamic focus and 1 for the B+ reference adjustment.
17 bits are also dedicated to several controls
(ON/OFF, Horizontal Forced Frequency, Sync Priority, Detection Refresh and XRAY reset).
I.4 - Read Mode
During the read mode the second byte transmits
the reply information.
The reply byte contains the horizontal and vertical
lock/unlock status, the XRAY activation status and,
the horizontal and vertical polarity detection.It also
contains the sync detection status which is used by
the MCU to assign the sync priority.
A stop conditionalways stops all the activities of the
bus decoder and switches to high impedance both
the data and clock line (SDA and SCL).
See I2C subaddress and control tables.
I.5 - Sync Processor
T h e in t e rn a l s yn c p ro ce ss o r a llo ws t h e
TDA9109/SN to accept :
- separated horizontal & vertical TTL-compatible
sync signal,
- composite horizontal & vertical TTL-compatible
sync signal.
TDA9109/SN
OPERATING DESCRIPTION (continued)
Sync priority
Subaddress
03 (D8)
Yes Yes
1
Yes No
0
Vext H/V
det det
No
Yes
V
det
Comment
Sync type
Separated H & V
Composite TTL H&V
Ofcourse, when the choice is made, we can refresh
the sync detections and verify that the extracted
Vsync is present and that no sync type change has
occured. The sync processor also gives sync polarity information.
I.7 - IC status
The IC can inform the MCU about the 1st horizontal
PLL and vertical section status (locked or not) and
about the XRAY protection (activated or not).
Resetting the XRAY internal latch can be done
either by decreasing the VCC or VDD supply or
directly resetting it via the I2C interface.
I.8 - Sync Inputs
Both H/HVIN and VSYNCIN inputs are TTL compatible triggers with hysterisis to avoid erratic
detection. Both inputs include a pull up resistor
connected to VDD.
I.9 - Sync Processor Output
The sync processor indicates on the HLOCKOUT
Pin whether 1st PLL is locked to an incoming
horizontal sync. HLOCKOUT is a TTL compatible
CMOS output. Its level goes to high when locked.
In the same time the D8 bit of the status register is
set to 0.
This information is mainly used to trigger safety
procedures (like reducing B+ value) as soon as a
change is detected on the incoming sync.
II - HORIZONTAL PART
II.1 - Internal Input Conditions
A digital signal (horizontal sync pulse or TTL
composite) is sent by the sync processor to the
horizontal input. It may be positiveornegative (see
Figure 5).
9109SN25.EPS
Figure 5
Using internal integration, both signals are recognized if Z/T < 25%. Synchronization occurs on the
leading edge of the internal sync signal. The minimum value of Z is 0.7µs.
Another integration is able to extract the vertical
pulse from compositesync if the duty cycle is higher
than 25% (typically d = 35%) (see Figure 6).
Figure 6
C
TRAMEXT
d
9109SN26.EPS
I.6 - Sync Identification Status
The MCU can read (address read mode : 8D) the
status register via the I 2C bus, and then select the
sync priority depending on this status.
Among other data this register indicates the presence of sync pulses on H/HVIN, VSYNCIN and
(when 12V is supplied) whether a Vext has been
extracted from H/HVIN. Both horizontaland vertical
sync are detected even if only 5V is supplied.
In order to choose the right sync priority the MCU
may proceed as follows (see I2C Address Table) :
- refresh the status register,
- wait at least for 20ms (Max. vertical period),
- read this status register.
Sync priority choice should be :
d
The last feature performed is the removal of equalization pulses to avoid parasitic pulses on the phase
comparator (which would be disturbed by missing
or extraneous pulses).
II.2 - PLL1
The PLL1 consists of a phase comparator, an
external filter and a voltage-controlled oscillator (VCO).
The phase comparator is a ”phase frequency”type
designed in CMOS technology. This kind of phase
detector avoids locking on wrong frequencies. It is
followed by a ”charge pump”, composed of two
current sources : sunk and sourced (typically I = 1mA when locked and I = 140µA when
unlocked). This difference between lock/unlock allows smooth catching of the horizontal frequency
by PLL1. This effect is reinforced by an internal
original slow down system when PLL1 is locked,
avoiding the horizontal frequency changing too
quickly.
The dynamic behaviour of PLL1 is fixed by an
external filter which integrates the current of the
charge pump. A ”CRC” filter is generally used
(see Figure 7).
17/30
TDA9109/SN
OPERATING DESCRIPTION (continued)
Figure 7
PLL1F
7
1.8kΩ
9109SN27.EPS
1µF
4.7µF
The PLL1 is internally inhibited during extracted vertical sync (if any) to avoid taking in account missing
pulses or wrong pulses on phase comparator.
The inhibition is done by a switch located between
the charge pump and the filter (see Figure 8).
The VCO uses an external RC network. It delivers
a linear sawtooth obtained by the charge and the
discharge of the capacitor, with a current proportional to the current in the resistor. The typical
thresholds of the sawtooth are 1.6V and 6.4V.
The control voltage of the VCO is between 1.33V
and 6V (see Figure 9). The theorical frequency
range of this VCO is in the ratio of 1 to 4.5. The
effective frequency range ha s to be smaller
(1 to 4.2) due to clamp intervention on the filter
lowest value.
Figure 8 : Block Diagram
Lock/Unlock
Status
Tramext
LOCKDET
PLL1F
7
I2C
Forced
Frequency
R0
6
C0
5
High
1
CHARGE
PUMP
COMP1
E2
PLL
INHIBITION
Low
VCO
HPOSITION
8
Tramext
OSC
I2C
HPOS
Adj.
PHASE
ADJUST
9109SN28.EPS
H/HVIN
INPUT
INTERFACE
Figure 9 : Details of VCO
I0
I0
2
6.4V
PLL1F
(Loop Filter) 7
RS
FLIP FLOP
1.6V
6
4 I0
(1.3V < V7 < 6V)
6.4V
5
C0
1.6V
0 0.875TH TH
18/30
9109SN29.EPS
R0
TDA9109/SN
OPERATING DESCRIPTION (continued)
Thesync frequencymust always be higherthan the
free running frequency. For example, when using
a sync range between 24kHz and 100kHz, the
suggested free running frequency is 23kHz.
This can beobtainedonly byadjustingf0 (forinstance,
making R0 adjustable). If no adjustment is possible,
more margin must be provided to cope with the
components spread : ±8% for the IC, ±1% for R0,
±2 or 5% for C0, leading to ±11% or 14% on f0. The
same percentage of frequency range will lost at
upper end of the range.
Another feature is the capability for the MCU to
force the horizontal frequency through I2C to 2xf0
or 3xf0 (for burn-in mode or safety requirements).
In this case, the inhibition switch is opened, leaving
PLL1 free, but the voltage on PLL1 filter is forced
to 2.66V (for 2xf0) or 4.0V (for 3xf0).
PLL1 ensuresthe coincidencebetween the leading
edge of the sync signal and a phase reference
obtained by comparison between the sawtooth of
the VCO and an internal DC voltage which is I2C
adjustable between 2.8V and 4.0V (corresponding
to ± 10%) (see Figure 10).
available on HLOCKOUT (see Sync Processor).
When PLL1 is unlocked, it forces HLOCKOUT to
high level.
The lock/unlock information is also available
through the I2C read.
II.3 - PLL2
PLL2 ensures a constant position of the shaped
flyback signal in comparison with the sawtooth of
the VCO, taking into accountthe saturationtime Ts
(see Figure 11).
Figure 11 : PLL2 Timing Diagram
H Osc
Sawtooth
4.0V
1.6V
Flyback
Internally
Shaped Flyback
1/8TH
H Drive
6.4V
2.8V < Vb < 4.0V
Vb
Ts
Duty Cycle
1.6V
The duty cycle of H-drive is fixed (48%).
Phase REF1
The TDA9109/SN also includes a Lock/Unlock
identification block which senses in real time
whether PLL1 is locked or not on the incoming
horizontal sync signal. The resulting information is
9109SN30.EPS
H Synchro
Phase REF1 is obtained by comparison between the sawtooth and
a DC voltage adjustable between 2.8V and 4.0V. The PLL1 ensures the exact coincidence between the signal phase REF and
HSYNC. A ± TH/10 phase adjustment is possible.
9109SN31.EPS
7/8TH
1/8TH
6.4V
Figure 10 : PLL1 Timing Diagram
H Osc
Sawtooth
7/8TH
The phase comparator of PLL2 (phase type comparator) is followed by a charge pump (typical
output current : 0.5mA).
The flyback input consists of an NPN transistor.
This input must be current driven. The maximum
recommended input current is 5mA (see Figure 12).
The duty cycle is fixed (48%).
The maximum storage time (Ts Max.) is (0.44TH TFLY/2). Typically, TFLY/TH is around 20% which
means that Ts max is around 34% of TH.
19/30
TDA9109/SN
OPERATING DESCRIPTION (continued)
II.5 - X-RAY Protection
The X-Ray protection is activated by application of
a high level on the X-Ray input (8V on Pin 25).
It inhibits the H-Drive and B+ outputs.
This protection is latched ; it may be reset either by
VCC or VDD switch off or by I2C (see Figure 14).
Figure 12 : Flyback Input Electrical Diagram
400Ω
Q1
HFLY 12
GND 0V
9109SN32.EPS
20kΩ
Figure 13
VCC
26 H-DRIVE
9109SN33.EPS
II.4 - Output Section
The H-drive signal is sent to the output through a
shaping stage which also controls the H-drive duty
cycle (I 2C adjustable) (see Figure 11). In order to
secure the scanning power part operation, the
output is inhibited in the following cases :
- when VCC or VDD are too low,
- when the XRAY protection is activated,
- during the Horizontal flyback,
- when the HDrive I2C bit control is off.
The output stage consists of a NPN bipolar transistor. Only the collector is accessible(see Figure 13).
This output stage is intended for ”reverse” base
control, where setting the output NPN in off-state
will control the power scanning transistor in offstate (see Application Diagram).
The maximum output current is 30mA, and the
corresponding voltage drop of the output VCEsat is
0.4V Max.
Obviously the power scanning transistor cannot be
directly driven by the integratedcircuit. An interface
has to be added between the circuit and the power
transistor either of bipolar or MOS type.
II.6 - Vertical Dynamic Focus
The TDA9109/SN delivers a vertical parabola
waveform on Pin 10.
This vertical dynamic focus is tracked with VPOS
and VAMP. Its amplitude can be adjusted. It is also
affectedby Sand Ccorrections. This positive signal
once amplified is to be sent to the CRT focusing
grids.
Figure 14 : Safety Functions Block Diagram
VCC Checking
I2C Drive on/off
VCC
VSCinh
HORIZONTAL
OUTPUT
INHIBITION
VDD Checking
VDD
VSDinh
XRAY Protection
XRAY
VCC or VDD off or I C Reset
2
S
R
Q
I2C Ramp on/off
VERTICAL
OUTPUT
INHIBITION
Horizontal Flyback
BOUT
20/30
9109SN34.EPS
0.7V
TDA9109/SN
OPERATING DESCRIPTION (continued)
III - VERTICAL PART
III.1 - Function
When the synchronization pulse is not present, an
internal current source sets the free running frequency. For an external capacitor, COSC = 150nF,
the typical free running frequency is 100Hz.
The typical free running frequency can be calculated by :
1
f0 (Hz) = 1.5 ⋅ 10−5 ⋅
COSC
A negative or positive TTL level pulse applied on
Pin 2 (VSYNC)as well as a TTLcomposite sync on
Pin 1 can synchronize the ramp in the range
[fmin , fmax]. This frequencyrange depends on the
ext e rn al capa c it or con nect ed on Pin 2 2.
A 150nF (±5%) capacitor is recommended for
50Hz to 185Hz applications.
The typical maximum and minimum frequency, at
25oC and without any correction (S correction or
C correction), can be calculated by :
f(Max.) = 3.5 x f0 and f(Min.) = 0.33 x f0
If S or C corrections are applied, these values are
slighty affected.
If a synchronization pulse is applied, the internal
oscillator is synchonized immediately but its
amplitude chan ges. An internal correction then
adjusts it in less than half a second. The top
value of the ramp (Pin 22) is sampled on the
AGC capacitor (Pin 20) at each clock pulse and
a transconduct ance amplifier modifies the
charge current of the capacitor in such a way to
make the amplitude again constant.
The read status register provides the vertical LockUnlock and the vertical sync polarity information.
We recommend the use of an AGC capacitor with
low leakage current. A value lower than 100nA is
mandatory.
A good stability of the internal closed loop is
reached by a 470nF ± 5% capacitor value on
Pin 20 (VAGC).
Figure 15 : AGC Loop Block Diagram
CHARGE CURRENT
TRANSCONDUCTANCE
AMPLIFIER
REF
22
20
VSYNCIN 2
SYNCHRO
OSC
CAP
SAMPLING
OSCILLATOR
SAMPLING
CAPACITANCE
S CORRECTION
VS_AMP
SUB07/6bits
POLARITY
COR_C
SUB08/6bits
C CORRECTION
Vlow
18 BREATH
Sawth.
Disch.
23 VOUT
VERT_AMP
SUB05/7bits
VMOIRE
SUB0C/5bits
9109SN35.EPS
DISCH.
VPOSITION
SUB06/7bits
21/30
TDA9109/SN
OPERATING DESCRIPTION (continued)
III.2 - I2C Control Adjustments
S and C correction shapes can then be added to
this ramp. These frequency independent S and C
corrections are generated internally. Their amplitudes are adjustable by their respective I2C registers. They can also be inhibited by their select bits.
Finally, the amplitude of this S and C corrected
ramp can be adjusted by the vertical ramp amplitude control register.
The adjusted ramp is available on Pin 23 (VOUT) to
drive an external power stage.
The gain of this stage can be adjusted (±25%)
dependingon its register value.
The mean value of this ramp is driven by its own
I2C register (vertical position). Its value is
VPOS = 7/16 ⋅ VREF-V ± 300mV.
Usually VOUT is sent through a resistive divider to
the inverting input of the booster. Since VPOS
derives from VREF-V, the bias voltage sent to the
non-inverting input of the booster should also derive from VREF-V to optimize the accuracy (see Application Diagram).
III.3 - Vertical Moiré
By using the vertical moiré, VPOS can be modulated from frame to frame. This function is intended
to cancel the fringes which appear when line to line
interval is very close to the CRT vertical pitch.
The amplitude of the modulation is controlled by
register VMOIRE on sub-address 0C and can be
switched-off via the control bit D7.
III.4 - Basic Equations
In first approximation,the amplitude of the ramp on
Pin 23 (VOUT) is :
VOUT - VPOS = (VOSC - VDCMID) ⋅ (1 + 0.25 (V AMP))
with :
- VDCMID = 7/16 ⋅ VREF (middle value of the ramp
on Pin 22, typically 3.5V)
- VOSC = V22 (ramp with fixed amplitude)
- VAMP = -1 for minimum vertical amplitude register
value and +1 for maximum
- VPOS is calculated by : VPOS = VDCMID + 0.3 VP
with VP equals -1 for minimum vertical position
register value and +1 for maximum
The current available on Pin 22 is :
3
IOSC = ⋅ VREF ⋅ COSC ⋅ f
8
with : COSC : capacitor connected on Pin 22 and
f : synchronization frequency.
22/30
III.5 - Geometric Corrections
The principle is represented in Figure 16.
Starting from the vertical ramp, a parabola-shaped
currentis generatedfor E/W correction(also known
as Pin Cushion correction), dynamic horizontal
phase control correction, and vertical dynamic Focus correction.
The parabola generator is made by an analog
multiplier, the output current of which is equal to :
∆I = k ⋅ (VOUT - VDCMID)2
where VOUT is the vertical output ramp (typically between2 and5V)andVDCMID is3.5V(forVREF-V = 8V).
One more multiplier provides a currentproportional
to (VOUT - VDCMID)4 for corner correction.
The VOUT sawtooth is typically centered on 3.5V.
By changing the vertical position, the sawtooth
shifts by ±0.3V.
In order to have good screen geometry for any end
user adjustment, the TDA9109/SN has the ”geometry tracking” feature, which allows generation
of a dissymetric parabola depending on the vertical position.
Due to the large output stage voltage range (E/W,
Keystone, Corner), the combination of tracking
function with maximum vertical amplitude, maximum or minimum vertical position and maximum
gain on the DAC control may lead to the output
stage saturation. This must be avoided by limiting
the output voltage with apropriate I2C registers
values.
For the E/W part and the dynamic horizontal phase
control part, a sawtooth-shapeddifferential current
in the following form is generated:
∆I’ = k’ ⋅ (VOUT - VDCMID)
Then ∆I and ∆I’ are added and converted into
voltage for the E/W part.
Each of the three E/W components, and the two
dynamichorizontal phasecontrolsmay be inhibited
by their own I2C select bit.
The E/W parabola is available on Pin 24 via an
emitter follower output stage which has to be biased by an external resistor (10kΩ to ground).
Since stable in temperature, the device can be DC
coupled with an external circuitry.
The vertical dynamic focus is available on Pin 10.
The dynamic horizontal phase control drives internally the H-position, moving the HFLY position on
the horizontal sawtooth in the range of ± 1.4% TH
both for side pin balance and parallelogram.
TDA9109/SN
OPERATING DESCRIPTION (continued)
Figure 16 : Geometric Corrections Principle
V.Focus
Amp
2
VDCMID (3.5V)
10
23
Dynamic Focus
Vertical Ramp VOUT
Parabola
Generator
EW+ Amp
2
Corner
VDCMID
(3.5V)
24
EW Output
Keystone
Sidepin Amp
To Horizontal
Phase
Sidepin Balance
Output Current
Parallelogram
III.6 - E/W
EWOUT = 2.5V + K1 (VOUT - VDCMID)+ K2 (VOUT - VDCMID)2 + K3 (VOUT - VDCMID)4
K1 is adjustable by the keystone I2C register,
K2 is adjustable by the E/W amplitude I2C register,
K3 is adjustable by the corner I2C register.
III.7 - Dynamic Horizontal Phase Control
IOUT = K4 (VOUT - VDCMID)+ K5 (VOUT - VDCMID)2
K4 is adjustable by the parallelogram I2C register,
K5 is adjustable by the side pin balance I2C register.
23/30
9109SN36.EPS
VDCMID
(3.5V)
TDA9109/SN
OPERATING DESCRIPTION (continued)
IV - DC/DC CONVERTER PART
This unit controls the switch-mode DC/DC converter. It converts a DC constant voltage into the
B+ voltage (roughly proportional to the horizontal
frequency) necessary for the horizontal scanning.
ThisDC/DC converter must be configured in stepup mode. It operates very similarly to the well
known UC3842.
4.8V and compared to the internal4.8V reference
(IVREF). The difference is amplified by an error
amplifier, the output of which controls the power
MOS switch-off current.
Main Features
- Switching synchronized on the horizontal frequency,
- B+ voltage always higher than the DC source,
- Current limited on a pulse-by-pulse basis.
The DC/DC converter is disabled :
- when VCC or VDD are too low,
- when X-Ray protection is latched,
- directly through I2C bus.
When disabled, BOUT is driven to GND by a 0.5mA
current source. This feature allows to implement
externally a soft start circuit.
IV.1 - Step-up Mode
Operating Description
- The power MOS is switched-on at the middle of
the horizontal flyback.
- The power MOS is switched-off when its current
reachesa predeterminedvalue. For this purpose,
a sense resistor is inserted in its source. The
voltage on this resistor is sent to Pin16 (ISENSE).
- The feedback (coming either from the EHV or
from the flyback) is divided to a voltage close to
Figure 17 : DC/DC Converter
I2 C
DAC
7bits
400ns
± Iadjust
12V
8V
4.8V ±20%
95dB
A
Σ
BOUT
1/3
C2
28
S
Q
Inhibit
SMPS
R
1.2V
Soft
Start
C3
1.2V
Inhibit SMPS
REGIN
15
COMP
14
ISENSE
16
TDA9109/SN
1MΩ
L
22kΩ
VB+
24/30
9109SN37.EPS
+
TDA9109/SN
INTERNAL SCHEMATICS
Figure 18
Figure 19
5V
Figure 20
Figure 21
12V
12V
HREF
13
PLL2C
HLOCKOUT
9109SN38.EPS
3
9109SN39.EPS
200Ω
Pins 1 -2
H/HVIN
VSYNCIN
20kΩ
5V
HREF
13
4
5
Figure 22
9109SN41.EPS
9109SN40.EPS
C0
Figure 23
HREF
HREF
13
13
PLL1F 7
12V
9109SN43.EPS
9109SN42.EPS
R0 6
25/30
TDA9109/SN
INTERNAL SCHEMATICS (continued)
Figure 24
Figure 25
HREF
5V
12V
12V
HPOSITION 8
Figure 26
9109SN45.EPS
9109SN44.EPS
HMOIRE 9
Figure 27
12V
HREF
13
12V
12V
FOCUSOUT 10
Figure 28
9109SN47.EPS
9109SN46.EPS
HFLY 12
Figure 29
12V
REGIN 15
26/30
9109SN49.EPS
9109SN48.EPS
COMP 14
TDA9109/SN
INTERNAL SCHEMATICS (continued)
Figure 30
Figure 31
12V
12V
ISENSE 16
Figure 32
9109SN51.EPS
9109SN50.EPS
BREATH 18
Figure 33
12V
VCAP 22
12V
9109SN52.EPS
9109SN53.EPS
VAGCCAP 20
Figure 34
Figure 35
12V
12V
EWOUT 24
9109SN54.EPS
9109SN55.EPS
VOUT 23
27/30
TDA9109/SN
INTERNAL SCHEMATICS (continued)
Figure 36
Figure 37
12V
12V
HOUT-BOUT
Pins 26-28
Figure 38
12V
9109SN58.EPS
Pins 30-31
SDA - SCL
28/30
9109SN57.EPS
9109SN56.EPS
XRAY 25
TDA9109/SN
APPLICATION DIAGRAMS
Figure 39 : Demonstration Board
J16
J15
J14
+12V
TP1
TP13 J11
PC1
47kΩ
CC2
10µF
1 H/HVIN
+5V
L1
22µH
R39
4.7kΩ
R29
4.7kΩ
R42
100Ω
+5V 32
C30
100µF
TP16
R41
100Ω
C32
100nF
C40
22pF
SCL
TP17 J12
7
6
C48
10µF
4
3
2
1
C43
47µF
C37
33pF
R15
1kΩ
R34
1kΩ
R45 33kΩ
TILT
J13
R30
10kΩ
E/W POWER STAGE
R37
27kΩ
TP14
+5V
C42
1µF
+5V
+12V
C36
1µF
R49
22kΩ
R43
10kΩ
D2
1N4148
R7 10kΩ
EWOUT 24
5
L2
22µH
C38
33pF
C17 1µF
9 HMOIRE
8
8MHz
R56
560Ω
C49
100nF
2kΩ
9
PWM0
R53
1kΩ
HOUT
8 HPOSITION XRAYIN 25
R8
10kΩ
10
IC3 - STV9422
HOUTCOL 26
PWM7
+12V
7 PLL1F
11
FBLK
J8
GGND 27
C13 10nF
C31
4.7µF R36 1.8kΩ
HOUT
C22
33pF
6 R0
12
X1
R23
6.49kΩ 1%
C25
33pF
R35
10kΩ
+12V
B+OUT 28
PWM1
R10
10kΩ
5 C0
C5
100µF
PWM6
+12V
+12V
C6
100nF
VSYNC
QA
GND
CC4
47pF
PC2
47kΩ
VCC 29
4 PLL2C
C28
820pF 5%
TEST
QB
8
B
QB
IA
QA
7
V DD
IB
IA
6
HSYNC
IB
5
24
G
CDB
TA2
CDA
4
23
PXCK
TB2
TA1
3
22
R
TB1
2
SCL 30
C7 22nF
21
CKOUT
VCC
1
3 HLOCKOUT
2Ω
20
GND
9
19
XTALOUT
10
18
RST
11
17
SDA
12
16
PWM2
13
15
XTALIN
14
14
PWM3
15
ICC1
MC14528
16
13
SCL
TP10
PWM5
SDA
+12V
CC1
100nF
C45
10µF
SDA 31
2 VSYNCIN
PWM4
CC3
47pF
4
3
2
1
C39
22pF
+5V
IC4
TDA9109/SN
R17
270kΩ
R31
27kΩ
HFLY
R38
2.2Ω
3W
R19
270kΩ
Q1
Q2
BC557 BC557
J1
C11 220pF
E/W
R25
1kΩ
J9
10 FOCUS
DYN
FOCUS
R24
10kΩ
VOUT 23
R9
470Ω
+12V
L4
47µH
R33
4.7kΩ
R18
39kΩ
Q3
TIP122
C12
11 HGND
VCAP 22
R52
3.9kΩ
150nF
C16 ( *)
12 HFLY
J19
1
C27
47µF
2
C33
100nF
VREF 21
C3
47µF
HREF
13 HREF
VAGCCAP 20
3
470nF
4
JP1
CON4
C51
100nF
14 COMP
R50
1MΩ
C2
100nF
R2
5.6kΩ
7
C41
470pF
BGND 17
16 ISENSE
C47
100pF
TP6
J2
+12V
-12V
TP4 TP3
J3
TP7
6
J6
3
5
1
4
R1
12kΩ
BREATH 18
R57
82kΩ
ISENSE
IC1
TDA8172
C9
100nF
C10
100µF
35V
2
VGND 19
R40
36kΩ
15 REGIN
R51
1kΩ
C4
100nF
C46
1nF
REGIN
C14
470µF
D1
1n4001
C15
C10
-12V 470µF
1
C1
R3
220nF 1.5Ω
C8
100nF
R5
5.6kΩ
R11
V YOKE
220Ω
0.5W
2
3
J18
R4
1Ω
0.5W
VERTICAL DEFLECTION STAGE
GND
R58
10Ω
Q4
BC557
J17
B+OUT
TP8
EHT
COMP
R75
10kΩ
R76
47kΩ
P1
10kΩ
R77
15kΩ
HOUT
Q5
BC547
R74
10kΩ
R73
1MΩ
C60
100nF
L3
22µH
C50
10µF
9109SN59.EPS
+12V
( * ) Optional
The difference with standard TDA9109 Application Diagram is the resistor divider 2kΩ/2Ω o n
Pin 9 (HMOIRE).
29/30
TDA9109/SN
PMSDIP32.EPS
PACKAGE MECHANICAL DATA
32 PINS - PLASTIC SHRINK DIP
A
A1
A2
B
B1
C
D
E
E1
e
eA
eB
L
Min.
3.556
0.508
3.048
0.356
0.762
0.203
27.43
9.906
7.620
2.540
Millimeters
Typ.
3.759
3.556
0.457
1.016
0.254
27.94
10.41
8.890
1.778
10.16
3.048
Max.
5.080
4.572
0.584
1.397
0.356
28.45
11.05
9.398
Min.
0.140
0.020
0.120
0.014
0.030
0.008
1.080
0.390
0.300
12.70
3.810
0.100
Inches
Typ.
0.148
0.140
0.018
0.040
0.010
1.100
0.410
0.350
0.070
0.400
0.120
Max.
0.200
0.180
0.023
0.055
0.014
1.120
0.435
0.370
0.500
0.150
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No licence is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical comp onents in lifesupport devicesor systems
without express written approval of STMicroelectronics.
The ST logo is a trademark of STMicroelectronics
 1998 STMicroelectronics - All Rights Reserved
2
2
Purchase of I C Components of STMicroelectronics, conveys a license under the Philips I C Patent.
Rights to use these components in a I 2C system, is granted provided that the system conforms to
the I2C Standard Specifications as defined by Philips.
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30/30
SDIP32.TBL
Dimensions