STMICROELECTRONICS TDA9109A

TDA9109A
LOW-COST I2C CONTROLLED DEFLECTION PROCESSOR
FOR MULTISYNC MONITOR
FEATURES
General
■ SYNC PROCESSOR
■ 12V SUPPLY VOLTAGE
■ 8V REFERENCE VOLTAGE
■ HORIZONTAL LOCK/UNLOCK OUTPUT
2
■ READ/WRITE I C INTERFACE
■ VERTICAL MOIRE
■ B+ REGULATOR
- Internal PWM generator for B+ current mode
step-up converter
- Switchable to step-down converter
- I2C adjustable B+ reference voltage
- Output Pulses Synchronized on Horizontal
Frequency
- Internal Maximum Current Limitation
Horizontal
■ Self-adaptative
■ Dual PLL concept
■ 150kHz maximum frequency
■ X-ray protection input
2
■ I C controls:
Horizontal duty-cycle, H-position
Vertical
■ Vertical ramp generator
■ 50 to 185Hz AGC loop
■ Geometry tracking with Vpos & Vamp
2
■ I C controls:
Vamp, Vpos, S-corr, C-corr
■ DC breathing compensation
DESCRIPTION
The TDA9109A is a monolithic integrated circuit
assembled in a 32-pin shrink dual in line plastic
package. This IC controls all the functions related
to the horizontal and vertical deflection in multimode or multi-frequency computer display monitors.
The internal sync processor, combined with the
very powerful geometry correction block, make
the TDA9109A suitable for very high performance
monitors, using very few external components.
The horizontal jitter level is very low. It is particularly well-suited to high-end 15” and 17” monitors.
Combined with the ST7275 Microcontroller family,
TDA9206 (Video preamplifier) and STV942x (OnScreen Display controller), the TDA9109A allows
fully I2C bus-controlled computer display monitors
to be built with a reduced number of external components
.
SHRINK32 (Plastic Package)
ORDER CODE: TDA9109A
I2C Geometry corrections
■ Vertical parabola generator
(Pin Cushion - E/W, Keystone, Corner
Correction)
■ Horizontal dynamic phase
(Side Pin Balance & Parallelogram)
■ Horizontal
and vertical dynamic focus
(Horizontal focus amplitude, Horizontal focus
symmetry, Vertical focus amplitude)
Version 4.2
June 2000
1/47
1
TABLE OF CONTENTS
PIN CONNECTIONS
4
PIN CONNECTIONS
QUICK REFERENCE DATA
5
6
BLOCK DIAGRAM
8
ABSOLUTE MAXIMUM RATINGS
9
THERMAL DATA
I2C READ/WRITE
9
10
SYNC PROCESSOR
HORIZONTAL SECTION
10
11
VERTICAL SECTION
13
DYNAMIC FOCUS SECTION
15
GEOMETRY CONTROL SECTION
B+ SECTION
16
18
TYPICAL OUTPUT WAVEFORMS
I2C BUS ADDRESS TABLE
20
24
I2C BUS ADDRESS TABLE
25
OPERATING DESCRIPTION
27
1 GENERAL CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.1Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.2I2C Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.3Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.4Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.5Sync Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.6Sync Identification Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1.7IC status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1.8Sync Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1.9Sync Processor Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2 HORIZONTAL PART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.1Internal Input Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.2PLL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.3PLL2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.4Output Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.5X-RAY Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.6Horizontal and Vertical Dynamic Focus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3 VERTICAL PART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.1Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.2I2C Control Adjustments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.3Vertical Moiré . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.4Basic Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.5E/W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
. . . . 36
3.6Dynamic Horizontal Phase Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2/47
2
TABLE OF CONTENTS
4 DC/DC CONVERTER PART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.1Step-up Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.2Step-down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.3Step-up and Step-down Mode Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
INTERNAL SCHEMATICS
39
PACKAGE MECHANICAL DATA
46
3
3/47
TDA9109A
PIN CONNECTIONS
4/47
H/HVIN
1
32
5V
VSYNCIN
2
31
SDA
HLOCKOUT
3
30
SCL
PLL2C
4
29
VCC
C0
5
28
BOUT
R0
6
27
GND
PLL1F
7
26
HOUT
HPOSITION
8
25
XRAY
HFOCUSCAP
9
24
EWOUT
FOCUS-OUT
10
23
VOUT
HGND
11
22
VCAP
HFLY
12
21
VREF
HREF
13
20
VAGCCAP
COMP
14
19
VGND
REGIN
15
18
BREATH
ISENSE
16
17
B+GND
TDA9109A
PIN CONNECTIONS
Pin
Name
Function
1
H/HVIN
TTL compatible Horizontal sync Input (separate or composite)
2
VSYNCIN
TTL compatible Vertical sync Input (for separated H&V)
3
HLOCKOUT
First PLL Lock/Unlock Output (0 V: Unlocked - 5 V: Locked)
4
PLL2C
Second PLL Loop Filter
5
C0
Horizontal Oscillator Capacitor
6
R0
Horizontal Oscillator Resistor
7
PLL1F
First PLL Loop Filter
8
HPOSITION
Horizontal Position Filter (capacitor to be connected to HGND)
9
HFOCUSCAP
Horizontal Dynamic Focus Oscillator Capacitor
10
FOCUS OUT
Mixed Horizontal and Vertical Dynamic Focus Output
11
HGND
Horizontal Section Ground
12
HFLY
Horizontal Flyback Input (positive polarity)
13
HREF
Horizontal Section Reference Voltage (to be filtered)
14
COMP
B+ Error Amplifier Output for frequency compensation and gain setting
15
REGIN
Regulation Input of B+ control loop
16
ISENSE
Sensing of external B+ switching transistor current,or switch for step-down converter
17
B+GND
Ground (related to B+ reference adjustment)
18
BREATH
DC Breathing Input Control (compensation of vertical amplitude against EHV variation)
19
VGND
Vertical Section Ground
20
VAGCCAP
Memory Capacitor for Automatic Gain Control Loop in Vertical Ramp Generator
21
VREF
Vertical Section Reference Voltage (to be filtered)
22
VCAP
Vertical Sawtooth Generator Capacitor
23
VOUT
Vertical Ramp Output (with frequency independant amplitude and S or C Corrections if
any). It is mixed with vertical position voltage and vertical moiré.
24
EWOUT
Pin Cushion - E/W Correction Parabola Output
25
XRAY
X-RAY protection input (with internal latch function)
26
HOUT
Horizontal Drive Output (NPN open collector)
27
GND
General Ground (referenced to V CC)
28
BOUT
B+ PWM Regulator Output
29
VCC
Supply Voltage(12V typ)
30
SCL
I2C Clock Input
31
SDA
I2C Data Input
32
5V
Supply Voltage (5V typ.)
5/47
TDA9109A
QUICK REFERENCE DATA
Parameter
Value
Unit
Horizontal Frequency
15 to 150
kHz
Autosynch Frequency (for given R0 and C0. Can be easily increased by application)
1 to 4.5 f0
± Horizontal Sync Polarity Input
YES
Polarity Detection (on both Horizontal and Vertical Sections)
YES
TTL Composite Sync
YES
Lock/Unlock Identification (on both Horizontal 1st PLL and Vertical Section)
YES
I C Control for H-Position
±10
XRAY Protection
YES
2
2
I C Horizontal Duty Cycle Adjustment
I2C
Free Running Frequency Adjustment
30 to 65
%
%
NO
Stand-by Function
YES
Dual Polarity H-Drive Outputs
NO
Supply Voltage Monitoring
YES
PLL1 Inhibition Possibility
NO
Blanking Outputs
NO
Vertical Frequency
35 to 200
Hz
Vertical Autosync (for 150nF on Pin 22 and 470nF on Pin 20)
50 to 185
Hz
Vertical S-Correction (optimized for super flat tube)
YES
Vertical C-Correction
YES
Vertical Amplitude Adjustment
YES
DC Breathing Control on Vertical Amplitude
YES
Vertical Position Adjustment
YES
East/West (E/W) Parabola Output (also known as Pin Cushion Output)
YES
E/W Correction Amplitude Adjustment
YES
Keystone Adjustment
YES
Corner Correction with Amplitude Adjustment
YES
Internal Dynamic Horizontal Phase Control
YES
Side Pin Balance Amplitude Adjustment
YES
Parallelogram Adjustment
YES
Tracking of Geometric Corrections with Vertical Amplitude and Position
YES
Reference Voltage (both on Horizontal and Vertical)
YES
Dynamic Focus (both Horizontal and Vertical)
YES
2
I C Horizontal Dynamic Focus Amplitude Adjustment
YES
I2C
YES
2
Horizontal Dynamic Focus Symmetry Adjustment
I C Vertical Dynamic Focus Amplitude Adjustment
6/47
YES
TDA9109A
Parameter
Value
Detection of Input Sync (biased from 5V alone)
YES
Vertical Moiré
YES
Controlled V-Moiré Amplitude
YES
Frequency Generator for Burn-in
NO
2
Fast I C Read/Write
400
2
B+ Regulation adjustable by I C
YES
Horizontal Size Control
NO
Unit
kHz
7/47
7
8
6
Phase/Frequency
Comparator
H-Phase(7bits)
H/HVIN 1
VSYNCIN 2
Sync Input
Select
(1bit)
Sync
Processor
R0 C0
HFLY
5
PLL2C
12
VCO
4
Phase
Comparator
Lock/Unlock
Identification
HOUT
26
Phase
Shifter
11 HGND
19 VGND
17 BGND
29 VCC
25 XRAY
Hout
Buffer
H-Duty
(7bits)
Safety
Processor
SPin bal
7bits
28 BOUT
16 ISENSE
14 COMP
x2
B+
Controller
x
+
HLOCKOUT 3
15 REGIN
Paral
7bits
5V
Internal
reference
(7bits)
VDFAMP
7bits
Corner
7bits
Geometry
Tracking
SDA 31
SCL 30
GND 27
7 bits
7 bits
VAMP
7bits
I2C Interface
S and C
Correction
5V 32
HREF 13
Href
VREF 21
Vref
Vertical
Oscillator
Ramp Generator
VPOS
7bits
x4
E/Wpcc
7bits
Keyst.
7 bits
20
18 23
VCAP VAGCCAP BREATH VOUT
10 FOCUS
Amp
2
Symmetryx
2x7bits
9 HFOCUSCAP
24 EWOUT
x
VerticalMoire
Cancel
7bits+ON/OFF
VSYNC
22
x2
x2
TDA9109A
TDA9109A
POSITION
BLOCK DIAGRAM
8/47
PLL1F
TDA9109A
ABSOLUTE MAXIMUM RATINGS
Symbol
Value
Unit
VCC
Supply Voltage (Pin 29)
Parameter
13.5
V
VDD
Supply Voltage (Pin 32)
5.7
V
Max Voltage on
4.0
5.5
6.4
8.0
VCC
VDD
V
V
V
V
V
V
2
300
kV
V
V IN
VESD
Pin 4
Pin 9
Pin 5
Pins 6, 7, 8, 14, 15, 16, 20, 22
Pins 10, 18, 23, 24, 25, 26, 28
Pins 1, 2, 3, 30, 31
ESD susceptibility
through
Human Body Model, 100pF Discharge
1.5kΩ
EIAJ Norm, 200pF Discharge through 0Ω
Tstg
Storage Temperature
-40, +150
°C
Tj
Junction Temperature
+150
°C
Operating Temperature
0, +70
°C
Value
Unit
65
°C/W
Toper
THERMAL DATA
Symbol
R th(j-a)
Parameter
Max. Junction-Ambient Thermal Resistance
9/47
TDA9109A
I2C READ/WRITE
Electrical Characteristics (VDD = 5V, Tamb = 25°C)
Symbol
2
Parameter
Test Conditions
Min.
Typ.
Max.
Units
400
kHz
1
I C PROCESSOR (See )
Fscl
Maximum Clock Frequency
Pin 30
Tlow
Low period of the SCL Clock
Pin 30
1.3
Thigh
High period of the SCL Clock
Pin 30
0.6
Vinth
SDA and SCL Input Threshold
Pins 30, 31
VACK
Acknowledge Output Voltage on SDA
input with 3mA
Pin 31
0.4
V
Leakage current into SDA and SCL
with no logic supply
VDD = 0
Pins 30, 31 = 5 V
20
µA
Max.
Units
5
V
I 2C leak
Note: 1
µs
µs
2.2
V
See also I2 C Bus Address Table.
SYNC PROCESSOR
Operating Conditions (VDD = 5V, Tamb = 25°C)
Symbol
Parameter
Test Conditions
Min.
Typ.
HsVR
Voltage on H/HVIN Input
Pin 1
0
MinD
Minimum Horizontal Input Pulses Duration
Pin 1
0.7
Mduty
Maximum Horizontal Input Signal Duty
Cycle
Pin 1
VsVR
Voltage on VSYNCIN
Pin 2
0
VSW
Minimum Vertical Sync Pulse Width
Pin 2
5
VSmD
Maximum Vertical Sync Input Duty Cycle
Pin 2
15
%
VextM
Maximum Vertical Sync Width on TTL
H/Vcomposite
Pin 1
750
µs
Max.
Units
0.8
V
V
µs
25
5
%
V
µs
Electrical Characteristics (VDD = 5V, Tamb = 25°C)
Symbol
Parameter
Test Conditions
Horizontal and Vertical Input Logic
Level (Pins 1, 2)
High Level
Low Level
RIN
Horizontal and Vertical Pull-Up Resistor
Pins 1, 2
VoutT
Extracted Vsync Integration Time (%
of TH) on H/V Composite (see 2)
C0 = 820pF
VINTH
Note: 2
10/47
T H is the Horizontal period.
Min.
Typ.
2.2
26
250
kΩ
35
%
TDA9109A
HORIZONTAL SECTION
Operating Conditions
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Units
VCO
I0max
F(max.)
Max Current from Pin 6
Pin 6
Maximum Oscillator Frequency
1.5
mA
150
kHz
OUTPUT SECTION
I12m
Maximum Input Peak Current
Pin 12
5
mA
HOI
Horizontal Drive Output Maximum
Current
Pin 26, Sunk current
30
mA
Electrical Characteristics (VDD = 12V, Tamb = 25°C))
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Units
12
13.2
V
5
5.5
SUPPLY AND REFERENCE VOLTAGES
VCC
Supply Voltage
Pin 29
10.8
VDD
Supply Voltage
Pin 32
4.5
ICC
Supply Current
Pin 29
IDD
50
V
mA
Supply Current
Pin 32
V REF-H
Horizontal Reference Voltage
Pin 13, I = -2mA
7.6
8.2
8.8
VREF-V
Vertical Reference Voltage
Pin 21, I = -2mA
7.6
8.2
8.8
V
IREF-H
Max. Sourced Current on VREF-H
Pin 13
5
mA
Max. Sourced Current on VREF-V
1st PLL SECTION
Pin 21
5
mA
IREF-V
HpoIT
Delay Time for detecting polarity
change (see 3)
Pin 1
Vvco
VCO Control Voltage (Pin 7)
V REF-H = 8.2V
fH(Max.)
Vcog
VCO Gain (Pin 7)
Hph
Vbmi
Vbtyp
Vbmax
IPII1U
IPII1L
fo
dfo/dT
CR
HUnlock
5
0.75
fo
mA
V
ms
1.4
6.4
V
V
R 0 = 6.49kΩ,
C 0 =820pF
15.9
kHz/V
Horizontal Phase Adjustment
(see 4)
% of Horizontal
Period
±10
%
Horizontal Phase Setting Value (Pin 8)
(see 4)
Minimum Value
Typical Value
Maximum Value
Sub-Address 01
2.9
3.5
4.2
V
V
V
Byte x1111111
Byte x1000000
Byte x0000000
PLL1 Filter Current Charge
PLL1 is Unlocked
PLL1 is Locked
±140
±1
µA
mA
Free Running Frequency
R 0 = 6.49kΩ,
C 0 = 820pF
22.8
kHz
-150
ppm/
C
fo+0.5
4.5fo
kHz
kHz
5
V
Free Running Frequency Thermal Drift
(No drift on external components)
(see 5)
PLL1 Capture Range
DC level pin 3 when PLL1 is locked
fH(Min.)
fH(Max.) (See Note 6)
11/47
TDA9109A
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Units
0.65
0.75
V
2nd PLL SECTION AND HORIZONTAL OUTPUT SECTION
FBth
Hjit
HDmin
HDmax
XRAYth
Vphi2
VSCinh
HDvd
Flyback Input Threshold Voltage (Pin
12)
7
Horizontal Jitter (See )
At 31.4kHz
70
ppm
Horizontal Drive Output Duty-Cycle
(Pin 26) (see 8)
Sub-Address 00
Byte x1111111
Byte x0000000 (see 9)
30
65
%
%
X-RAY Protection Input Threshold
Voltage,
Pin 25, see Figure 14
Internal Clamping Levels on 2nd PLL
Loop Filter (Pin 4)
Low Level
High Level
1.6
4.2
V
V
Threshold Voltage to Stop H-Out, VOut, B-Out and Reset XRAY when VCC
< VSCinh (see Figure14)
Pin 29
7.5
V
Horizontal Drive Output (low level)
Pin 26, IOUT = 30mA
7.6
8.2
8.8
0.4
Note: 3
This delay is mandatory to avoid a wrong detection of polarity change in the case of a composite sync.
Note: 4
See Figure 10 for explanation of reference phase.
Note: 5
These parameters are not tested on each unit. They are measured during our internal qualification.
Note: 6
A larger range may be obtained by application.
Note: 7
Hjit = 106 x (Standard deviation/Horizontal period)
Note: 8
Duty Cycle is the ratio between the output transistor OFF time and the period. The power transistor is
controlled OFF when the output transistor is OFF.
Note: 9
Initial Condition for Safe Operation Start Up.
12/47
V
V
TDA9109A
VERTICAL SECTION
Operating Conditions
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Units
OUTPUTS SECTION
R LOAD
Minimum Load for less than 1% Vertical Amplitude Drift
Pin 20
65
MΩ
Electrical Characteristics (VCC = 12V, Tamb = 25°C)
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Units
VERTICAL RAMP SECTION
VRB
Voltage at Ramp Bottom Point
Pin 22
2.1
V
VRT
Voltage at Ramp Top Point (with Sync)
Pin 22
5.1
V
VRTF
Voltage at Ramp Top Point (without
Sync)
Pin 22
VRT0.1
V
VSTD
Vertical Sawtooth Discharge Time
Pin 22, C22 = 150nF
70
µs
VFRF
Vertical Free Running Frequency
(See 11)
C 22 = 150nF
100
Hz
ASFR
AUTO-SYNC Frequency (See 12)
C 22 = 150nF ±5%
RAFD
Ramp Amplitude Drift Versus
Frequency at Maximum Vertical
Amplitude (see 10)
C 22 = 150nF
50Hz< f < 185Hz
200
ppm/
Hz
Ramp Linearity on Pin 22 (See 11)
2.5V < V27 < 4.5V
0.5
%
Vertical Position Adjustment Voltage
(Pin 23 - VOUT mean value)
Sub Address 06
Byte 00000000
Byte 01000000
Byte 01111111
3.2
3.6
4.0
V
V
V
VOR
Vertical Output Voltage
(peak-to-peak on Pin 23)
Sub Address 05
Byte 10000000
Byte 11000000
Byte 11111111
2.15
3.0
3.9
V
V
V
VOI
Vertical Output Maximum Current
(Pin 23)
±5
mA
dVS
Max Vertical S-Correction Amplitude
(See 13)
0xxxxxxx inhibits S-CORR
11111111 gives max S-CORR
Sub Address 07
Byte 11111111
∆V/VPP at TV/4
∆V/VPP at 3TV/4
-3.5
3.5
%
%
Vertical C-Corr Amplitude
0xxxxxxx inhibits C-CORR
Sub Address 08
∆V/VPP at TV/2
Byte 10000000
Byte 11000000
Byte 11111111
-3
0
3
%
%
%
Vertical Moiré
Sub Address 0C
Byte 01X11111
6
mV
Rlin
VPOS
Ccorr
VMOIRE
50
185
Hz
13/47
TDA9109A
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Units
12
V
BREATHING COMPENSATION
BRRANG
BRADj
DC Breathing Voltage Range
(See 14)
V18
Vertical Output Variation versus DC
Breathing Control (Pin 23)
V18 > VREF-V
1V<V18< VREF-V
1
0
-2.5
%/V
%/V
Note: 10 These parameters are not tested on each unit. They are measured during our internal qualification procedure.
Note: 11 With Register 07 at Byte 0xxxxxxx (S correction is inhibited) and Register 08 at Byte 0xxxxxxx (C correction
is inhibited), the vertical sawtooth has a linear shape.
Note: 12 This is the frequency range for which the vertical oscillator will automatically synchronize, using a single
capacitor value on Pin22 and Pin 20, and with a constant ramp amplitude.
Note: 13 TV is the vertical period.
Note: 14 When not used, the DC breathing control pin must be connected to 12V.
14/47
TDA9109A
DYNAMIC FOCUS SECTION
Electrical Characteristics (VCC = 12V, Tamb = 25°C)
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Units
HORIZONTAL DYNAMIC FOCUS FUNCTION
HDFst
Horizontal Dynamic Focus Sawtooth
Minimum Level
Maximum Level
Pin 9, capacitor on
HFOCUSCAP and
C0 = 820pF, TH =
20µs
HDFdis
Horizontal Dynamic Focus Sawtooth
Discharge Width
Start by HDFstart
HDFstart
Internal Fixed Phase Advance versus
HFLY middle
Independent of
frequency
HDFDC
Bottom DC Output Level
R LOAD = 10kΩ, Pin 10
TDFHD
DC Output Voltage Thermal Drift
(see 15)
2.2
4.9
V
V
400
ns
1
µs
2.1
V
200
ppm/
C
HDFamp
Horizontal Dynamic Focus Amplitude
Min Byte
xxx11111
Typ Byte
xxx10000
Max Byte
xxx00000
Sub-Address 03,
Pin 10, fH = 50kHz,
Symmetric Wave
Form
1
1.5
3.5
VPP
VPP
VPP
HDFKeyst
Horizontal Dynamic Focus Position
Advance for Byte
xxx11111
Delay for Byte
xxx00000
Sub-address 04
For time reference
see Figure 15
16
16
%
%
0
0.5
1
VPP
VPP
VPP
0.6
1
1.5
VPP
VPP
VPP
VERTICAL DYNAMIC FOCUS FUNCTION (positive parabola)
AMPVDF
Vertical Dynamic Focus Parabola
(added to horizontal) Amplitude with
VAMP and VPOS Typical
Min. Byte xx000000
Typ. Byte xx100000
Max. Byte xx111111
VDFAMP
Parabola Amplitude Function of VAMP
(tracking between VAMP and VDF)
with VPOS Typ. (see Figure 1 and 16)
VHDFKeyt
Parabola Asymmetry Function of
VPOS Control (tracking between
VPOS and VDF) with VAMP Max.
A/B Ratio
B/A Ratio
Sub-Address 0F
Sub-Address 05
Byte x0000000
Byte x1000000
Byte x1111111
Sub-Address 06
Byte x0000000
Byte x1111111
0.52
0.52
Note: 15 These parameters are not tested on each unit. They are measured during our internal qualification.
Note: 16 S and C correction are inhibited so the vertical output sawtooth has a linear shape.
15/47
TDA9109A
GEOMETRY CONTROL SECTION
Electrical Characteristics (VCC = 12V, Tamb = 25°C)
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Units
East/West E/W FUNCTION
DC Output Voltage with:
- typical VPOS
- Keystone inhibited
Pin 24, see Figure 2
2.5
V
TDEWDC
DC Output Voltage Thermal Drift
See 15
100
ppm/
C
EWpara
Parabola Amplitude with:
- Max. VAMP,
- Typ. VPOS,
- Keystone and Corner inhibited
Subaddress 0A
Byte 11111111
Byte 11000000
Byte 10000000
2.5
1.25
0
VPP
VPP
VPP
Subaddress 05
EWtrack
Parabola Amplitude Function of VAMP
Control (tracking between VAMP and
E/W) with:
- Typ. VPOS,
- Typ. E/W Amplitude,
- Corner and Keystone inhibited (17)
0.45
0.80
1.45
VPP
VPP
VPP
Subaddress 09
KeyAdj
Keystone Adjustment Capability with: - Typ. VPOS,
- E/W inhibited,
- Corner inhibited and
- Max. Vertical Amplitude
(see 17 and Figure 4)
1
1
VPP
VPP
Corner Adjustment Capability with:
- Typ. VPOS,
- E/W inhibited,
- Keystone inhibited
- Max. Vertical Amplitude
Subaddress 10
+3
0
−3
VPP
VPP
VPP
Intrinsic Keystone Function of VPOS
Control (tracking between VPOS and
E/W) with:
- Max. E/W Amplitude
- Max. Vertical Amplitude
A/B Ratio
B/A Ratio
Subaddress 06
EW DC
EW
Corner
KeyTrack
16/47
Byte 10000000
Byte 11000000
Byte 11111111
Byte 10000000
Byte 11111111
Byte 11111111
Byte 11000000
Byte 10000000
Byte 00000000
Byte 01111111
0.52
0.52
TDA9109A
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Units
INTERNAL DYNAMIC HORIZONTAL PHASE CONTROL
SPBpara
SPBtrack
ParAdj
Partrack
Side Pin Balance Parabola Amplitude
(Figure 3) with:
- Max. VAMP,
- Typ. VPOS
- Parallelogram inhibited (see 17 & 19)
Subaddress 0D
Side Pin Balance Parabola Amplitude
function of VAMP Control (tracking between VAMP and SPB) with
- Max. SPB,
- Typ. VPOS
- Parallelogram inhibited (see 17 & 19)
Subaddress 05
Parallelogram Adjustment Capability
with:
- Max. VAMP,
- Typ. VPOS
- Max. SPB (see 17 & 19)
Subaddress 0E
Intrinsic Parallelogram Function of
VPOS Control (tracking between
VPOS and DHPC) with:
- Max. VAMP,
- Max. SPB
- Parallelogram inhibited (see 17 & 19)
A/B Ratio
B/A Ratio
Subaddress 06
Byte 11111111
Byte 10000000
Byte 10000000
Byte 11000000
Byte 11111111
Byte 11111111
Byte 11000000
Byte x0000000
Byte x1111111
+2.8
-2.8
%TH
%TH
1
1.8
2.8
%TH
%TH
%TH
+2.8
-2.8
%TH
%TH
0.52
0.52
Note: 17 With Register 07 at Byte 0xxxxxxx (S correction is inhibited) and Register 08 at Byte 0xxxxxxx (C correction
is inhibited), the vertical sawtooth has a linear shape.
Note: 18 T H is the horizontal period.
Note: 19 When not used, the DC breathing control pin must be connected to 12V.
17/47
TDA9109A
B+ SECTION
Operating Conditions
Symbol
FeedRes
Parameter
Minimum Feedback Resistor
Test Conditions
Resistor between
Pins 15 and 14
Min.
Typ.
Max.
5
Units
kΩ
Electrical Characteristics (VCC = 12V, Tamb = 25°C)
Symbol
OLG
UGBW
Parameter
Error Amplifier Open Loop Gain
Test Conditions
Min.
At low frequency ( 15)
15
)
Typ.
Max.
Units
85
dB
6
MHz
0.2
µA
1.4
mA
Unity Gain Bandwidth
(see
Regulation Input Bias Current
Current sourced by
Pin 15 (PNP base)
EAOI
Error Amplifier Output Current
Current sourced by
Pin 14
Current sunk by Pin 14
(See 20)
CSG
Current Sense Input Voltage Gain
Pin 16
3
Max Current Sense Input Threshold
Voltage
Pin 16
1.3
V
ISI
Current Sense Input Bias Current
Current sunk by Pin 16
(PNP base)
1
µA
Tonmax
Maximum ON Time of the external
power transistor
% of horizontal period
fo = 27kHz (See 21)
100
%
B+OSV
B+Output Saturation Voltage
V 28 with I28 = 10mA
0.25
V
Internal Reference Voltage
On error amp (+) input
for Subaddress OB
Byte 1000000
5
V
V REFADJ
Internal Reference Voltage Adjustment
Range
Byte 01111111
Byte 00000000
+20
-20
%
%
PWMSEL
Threshold for step-up/step-down
selection
Pin 16
6
V
Fall Time
Pin 28
100
ns
IRI
MCEth
IVREF
tFB+
2
mA
Note: 20 0.5mA are sunk when B+ section is disabled. the purpose is to discharge the soft-start capacitor.
Note: 21 The external power transistor is OFF during 400ns of the HFOCUSCAP discharge
18/47
TDA9109A
Figure 1. Vertical Dynamic Focus Function
Figure 2. E/W Output
Figure 3. Dynamic Horizontal Phase Control Output
Figure 4. Keystone Effect on E/W Output (PCC Inhibited)
19/47
TDA9109A
TYPICAL OUTPUT WAVEFORMS
Function
Sub
Address
Pin
Byte
Specification
10000000
Vertical
Size
05
23
11111111
VOUTDC = 3.2V
00000000
Vertical
Position
DC Control
VOUTDC = 3.6V
06
23
01000000
V OUTDC = 4.0V
01111111
0xxxxxxx:
Inhibited
Vertical
S
Linearity
07
23
11111111
=
20/47
Effect on Screen
TDA9109A
Function
Sub
Address
Pin
Byte
Specification
Effect on Screen
0xxxxxxx :
Inhibited
Vertical
C
Linearity
08
23
10000000
= -3%
11111111
= +3%
Horizontal
Dynamic
Focus
with:
03
10
Amplitude
Horizontal
Dynamic
Focus
with:
04
10
X000 0000
—
X111 1111 --
X000 0000
—
X111 1111 --
Symmetry
21/47
TDA9109A
Function
Sub
Address
Pin
Byte
Specification
Effect on Screen
(E/W + Corner
Inhibited)
Keystone
(Trapezoid)
Control
09
10000000
0.4V
EWDC
11111111
0.4V
EWDC
24
(Keystone
+ Corner
Inhibited)
E/W
(Pin
Cushion)
Control
0A
24
10000000
EWDC
0V
1.4V
11111111
EW DC
(Keystone+E/W Inhibited)
1.25V
11111111
Corner
Control
10
EW DC
24
EW DC
10000000
1.25V
Parallelogram
Control
22/47
0E
Internal
(SPB Inhibited)
10000000
2.8% T H
11111111
2.8% T H
TDA9109A
Function
Sub
Address
Pin
Byte
Specification
Effect on Screen
Side Pin
Balance
Control
Vertical
Dynamic
Focus
with
Horizontal
0D
0F
Internal
(Parallelogram Inhibited)
10
10000000
2.8% TH
11111111
2.8% TH
X111 1111
—X000
0000 ---
23/47
TDA9109A
I2C BUS ADDRESS TABLE
Slave Address (8C): Write Mode
Sub Address Definition
D8
D7
D6
D5
D4
D3
D2
D1
0
0
0
0
0
0
0
0
0
Horizontal Drive Selection/Horizontal Duty Cycle
1
0
0
0
0
0
0
0
1
X-ray Reset/Horizontal Position
2
0
0
0
0
0
0
0
0
3
0
-
-
1
0
0
1
1
Sync. Priority/Horizontal Focus Amplitude
4
0
-
-
1
0
1
0
0
Refresh/Horizontal Focus Keystone
5
0
0
0
0
0
1
0
1
Vertical Ramp Amplitude
6
0
0
0
0
0
1
1
0
Vertical Position Adjustment
7
0
0
0
0
0
1
1
1
S Correction
8
0
0
0
0
1
0
0
0
C Correction
9
0
0
0
0
1
0
0
1
E/W Keystone
A
0
0
0
0
1
0
1
0
E/W Amplitude
B
0
0
0
0
1
0
1
1
B+ Reference Adjustment
C
0
0
0
0
1
0
0
0
Vertical Moiré
D
0
0
0
0
1
0
0
1
Side Pin Balance
E
0
0
0
0
1
0
1
0
Parallelogram
F
0
0
0
0
1
0
1
1
Vertical Dynamic Focus Amplitude
10
0
0
0
1
0
0
0
0
E/W Corner
Slave Address (8D): Read Mode
No sub address needed.
24/47
TDA9109A
I2C BUS ADDRESS TABLE
D8
D7
D6
[HDrive
0, off
[1], on0]
[0]
D5
D4
D3
D2
D1
[0]
[0]
[0]
[0]
WRITE MODE
00
01
Xray
1, reset
[0]
Horizontal Duty Cycle
[0]
[0]
[0]
Horizontal Phase Adjustment
[1]
[0]
[0]
[0]
[0]
02
03
Sync
0, Comp
[1], Sep
04
Detect
Refresh
[0], off
05
Vramp
0, off
[1], on
Horizontal Focus Amplitude
[1]
[0]
[0]
[0]
[0]
Horizontal Focus Time Position
[1]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
Vertical Ramp Amplitude Adjustment
[1]
[0]
[0]
[0]
[0]
Vertical Position Adjustment
06
07
08
[1]
S Select
1, on
[0]
E/W Key
0, off
[1]
0A
E/W Sel
0, off
[1]
0B
Test H
1, on
[0], off
0C
Test V
1, on
[0], off
0D
0E
SPB Sel
0, off
[1]
Parallelo
0, off
[1]
[0]
[0]
[0]
S Correction
[1]
C Select
1, on
[0]
09
[0]
[0]
[0]
[0]
C Correction
[1]
[0]
[0]
[0]
E/W Keystone
[1]
[0]
[0]
E/W Amplitude
[1]
[0]
[0]
[0]
B + Reference Adjustment
[1]
[0]
[0]
[0]
[0]
Vertical Moiré
Moiré
1, on [0]
[0]
[0]
[0]
Side Pin Balance
[1]
[0]
[0]
[0]
Parallelogram
[1]
[0]
[0]
[0]
25/47
TDA9109A
D8
0F
Eq. Pulse
1, on
[0], off
10
Corner
1, on
[0], off
D7
D6
D5
D4
D3
D2
D1
[0]
[0]
[0]
[0]
Vertical Dynamic Focus Amplitude
[1]
[0]
[0]
[0]
Corner Amplitude Adjustment
[1]
[0]
[0]
[0]
READ MODE
Hlock
0, on
[1], no
Polarity Detection
Vlock
0, on
[1], no
Xray
1, on
[0], off
H/V pol
[1], negative
V pol
[1], negative
Sync Detection
Vext det
[0], no det
H/V det
[0], no det
V det
[0], no det
[x] Initial value
Data is transferred with vertical sawtooth retrace.
We recommend setting the unspecified bit to [0] in order to ensure compatibility with future devices.
26/47
TDA9109A
OPERATING DESCRIPTION
1 GENERAL CONSIDERATIONS
1.1 Power Supply
1.3 Write Mode
The typical values of the power supply voltages
VCC and VDD are 12 V and 5 V respectively. Optimum operation is obtained for VCC between 10.8
and 13.2 V and VDD between 4.5 and 5.5 V.
In order to avoid erratic operation of the circuit during the transient phase of VCC switching on, or off,
the value of V CC is monitored: if VCC is less than
7.5 V typ., the outputs of the circuit are inhibited.
Similarly, before VDD reaches 4 V, all the I2 C register are reset to their default value (see I 2C Control Table).
In order to have very good power supply rejection,
the circuit is internally supplied by several voltage
references (typ. value: 8.2 V). Two of these voltage references are externally accessible, one for
the vertical and one for the horizontal part. They
can be used to bias external circuitry (if ILOAD is
less than 5 mA). It is necessary to filter the voltage
references by external capacitors connected to
ground, in order to minimize the noise and consequently the “jitter” on vertical and horizontal output
signals.
In write mode the second byte sent contains the
subaddress of the selected function to adjust (or
controls to affect) and the third byte the corresponding data byte. It is possible to send more
than one data byte to the IC. If after the third byte
no stop or start condition is detected, the circuit increments automatically by one the momentary
subaddress in the subaddress counter (auto-increment mode). So it is possible to transmit immediately the following data bytes without sending the
IC address or subaddress. This can be useful to
reinitialize all the controls very quickly (flash manner). This procedure can be finished by a stop condition.
The circuit has 18 adjustment capabilities: 3 for the
horizontal part, 4 for the vertical, 3 for the
E/W correction, 2 for the dynamic horizontal phase
control, 2 for the vertical and horizontal Moiré options, 3 for the horizontal and the vertical dynamic
focus and 1 for the B+ reference adjustment.
18 bits are also dedicated to several controls (ON/
OFF, Horizontal Forced Frequency, Sync Priority,
Detection Refresh and XRAY reset).
1.2 I2 C Control
TDA9109A belongs to the I2C controlled device
family. Instead of being controlled by DC voltages
on dedicated control pins, each adjustment can be
done via the I2C Interface.
The I2C bus is a serial bus with a clock and a data
input. The general function and the bus protocol
are specified in the Philips-bus data sheets.
The interface (Data and Clock) is a comparator
whose threshold is 2.2 V with a 5 V supply. Spikes
of up to 50 ns are filtered by an integrator and the
maximum clock speed is limited to 400 kHz.
The data line (SDA) can be used bidirectionally. In
read-mode the IC sends reply information
(1 byte) to the micro-processor.
The bus protocol prescribes a full-byte transmission in all cases. The first byte after the start condition is used to transmit the IC-address (hexa 8C
for write, 8D for read).
1.4 Read Mode
During the read mode the second byte transmits
the reply information.
The reply byte contains the horizontal and vertical
lock/unlock status, the XRAY activation status
and, the horizontal and vertical polarity detection.
It also contains the sync detection status which is
used by the MCU to assign the sync priority. A
stop condition always stops all the activities of the
bus decoder and switches to high impedance both
the data and clock line (SDA and SCL).
See I2C subaddress and control tables.
1.5 Sync Processor
The internal sync processor allows the TDA9109A
to accept:
•
•
separated horizontal & vertical TTLcompatible sync signal
composite horizontal & vertical TTLcompatible sync signal
27/47
TDA9109A
1.6 Sync Identification Status
The MCU can read (address read mode: 8D) the
status register via the I2C bus, and then select the
sync priority depending on this status.
Among other data this register indicates the presence of sync pulses on H/HVIN, VSYNCIN and
(when 12 V is supplied) whether a Vext has been
extracted from H/HVIN. Both horizontal and vertical sync are detected even if only 5 V is supplied.
In order to choose the right sync priority the MCU
may proceed as follows (see I 2C Address Table):
•
•
•
refresh the status register
wait at least for 20ms (Max. vertical period)
read this status register
Of course, when the choice is made, we can refresh the sync detections and verify that the extracted Vsync is present and that no sync type
change has occurred. The sync processor also
gives sync polarity information.
1.7 IC status
The IC can inform the MCU about the 1st horizontal PLL and vertical section status (locked or not)
and about the XRAY protection (activated or
not).Resetting the XRAY internal latch can be
done either by decreasing the VCC supply or directly resetting it via the I2C interface.
1.8 Sync Inputs
Both H/HVIN and VSYNCIN inputs are TTL compatible triggers with hysteresis to avoid erratic detection. Both inputs include a pull up resistor connected to VDD.
Sync priority choice should be:
Vextd
et
HV
det
V
det
Sync
priority
Subaddress
03 (D8)
No
Yes
Yes
1
Separated H&V
Yes
Yes
No
0
Composite TTL H&V
Comment
Sync type
1.9 Sync Processor Output
The sync processor indicates on the D8 bit of the
status register whether 1st PLL is locked to an incoming horizontal sync. Its level goes to low when
locked. This information is also available on pin 3
when sub-address 02 D8 is equal to 1. When PLL1
is unlocked, pin 3 output voltage goes to 5V.
2 HORIZONTAL PART
2.1 Internal Input Conditions
A digital signal (horizontal sync pulse or TTL composite) is sent by the sync processor to the horizontal input. It may be positive or negative (see
Figure 5).
28/47
Using internal integration, both signals are recognized if Z/T < 25%. Synchronization occurs on the
leading edge of the internal sync signal.
The minimum value of Z is 0.7 µs.
Another integration is able to extract the vertical
pulse from composite sync if the duty cycle is higher than 25% (typically d = 35%),
(see Figure 6).
TDA9109A
Figure 5.
Figure 6.
The last feature performed is the removal of equalization pulses to avoid parasitic pulses on the
phase comparator (which would be disturbed by
missing or extraneous pulses). This last feature is
switched on/off by sub-address 0F D8. By default
[0], equalization pulses will not be removed.
2.2 PLL1
The PLL1 consists of a phase comparator, an external filter and a voltage-controlled oscillator
(VCO).The phase comparator is a “phase frequency” type designed in CMOS technology. This kind
of phase detector avoids locking on wrong frequencies. It is followed by a “charge pump”, composed of two current sources : sunk and sourced
(typically I =1 mA when locked and I = 140 µA
when unlocked). This difference between lock/unlock allows smooth catching of the horizontal frequency by PLL1. This effect is reinforced by an internal original slow down system when PLL1 is
locked, avoiding the horizontal frequency changing too quickly. The dynamic behavior of PLL1 is
fixed by an external filter which integrates the current of the charge pump. A “CRC” filter is generally
used (see Figure 7)
Figure 7.
PLL1F
7
1.8k Ω
10nF
4.7µF
29/47
TDA9109A
The PLL1 is internally inhibited during extracted
vertical sync (if any) to avoid taking in account
missing pulses or wrong pulses on phase
comparator. Inhibition is obtained by stopping high
and low signals at the entry of the charge pump
block (see Figure 8).
Figure 8.
Figure 9.
The VCO uses an external RC network. It delivers
a linear sawtooth obtained by the charge and the
discharge of the capacitor, with a current proportional to the current in the resistor. The typical
thresholds of the sawtooth are 1.6 V and 6.4 V.
The control voltage of the VCO is between 1.4 V
and 6.4 V (see Figure 9). The theoretical frequency range of this VCO is in the ratio of 1 to 4.5. The
effective frequency range has to be smaller (1 to
4.2) due to clamp intervention on the filter lowest
value.
30/47
The sync frequency must always be higher than
the free running frequency. For example, when using a sync range between 24.8 kHz and 100 kHz,
the suggested free running frequency is 23 kHz.
PLL1 ensures the coincidence between the leading edge of the sync signal and a phase reference
obtained by comparison between the sawtooth of
the VCO and an internal DC voltage which is I2C
adjustable between 2.9 V and 4.2 V (corresponding to ±10 %) (see Figure 10).
TDA9109A
The TDA9109A also includes a Lock/Unlock identification block which senses in real time whether
PLL1 is locked or not on the incoming horizontal
sync signal.
The lock/unlock information is available through
the I2C read and the pin 3 voltage level
PLL1 Timing Diagram
Figure 11. PLL2 Timing Diagram
HOsc
Sawtooth
7/8TH
1/8 TH
6.4V
4.0V
Figure 10.
H O SC
Sawtooth
1.6V
7/8 TH
1/8 TH
6.4V
Ref. for H Position
Vb
(2.9V<Vb<4.2V)
1.6V
Flyback
Internally
shaped Flyback
REF1
HDrive
HSync
Phase REF1 is obtained by comparison between
the sawtooth and a DC voltage adjustable between
2.9 V and 4.2 V.
The PLL1 ensures the exact coincidence between the
signal phase REF and HSYNC. A ±10% TH phase
adjustment is possible around the 3.4V point.
2.3 PLL2
PLL2 ensures a constant position of the shaped
flyback signal in comparison with the sawtooth of
the VCO, taking into account the saturation time
Ts (see Figure 11)
Ts
Duty Cycle
The phase comparator of PLL2 (phase type comparator) is followed by a charge pump (typical output current: 0.5 mA).
The flyback input consists of an NPN transistor.
This input must be current driven. The maximum
recommended
input
current
is
5 mA
(see Figure 12).
Figure 12. Flyback Input Electrical Diagram
500Ω
HFly
Q1
12
20kΩ
GND 0V
The duty cycle is adjustable through I2C from 30 %
to 65 %. For a safe start-up operation, the initial
duty cycle (after power-on reset) is 65% in order to
avoid having too long a conduction period of the
horizontal scanning transistor.
The maximum storage time (Ts Max.) is (0.44THTFLY/2). Typically, TFLY/TH is around 20 % which
means that Ts max is around 34 % of TH.
31/47
TDA9109A
2.4 Output Section
The H-drive signal is sent to the output through a
shaping stage which also controls the H-drive duty
cycle (I2C adjustable) (see Figure 11). In order to
secure the scanning power part operation, the output is inhibited in the following cases:
•
•
•
•
when VCC or VDD are too low
when the XRAY protection is activated
during the Horizontal flyback
when the HDrive I2C bit control is off
The output stage consists of a NPN bipolar transistor. Only the collector is accessible
(see Figure 13).
Figure 13.
Figure 14. Safety Functions Block Diagram
32/47
This output stage is intended for “reverse” base
control, where setting the output NPN in off-state
will control the power scanning transistor in offstate.
The maximum output current is 30mA, and the
corresponding voltage drop of the output VCEsat is
0.4V Max.
Obviously the power scanning transistor cannot be
directly driven by the integrated circuit. An interface has to be added between the circuit and the
power transistor either of bipolar or MOS type.
2.5 X-RAY Protection
The X-Ray protection is activated by application of
a high level on the X-Ray input (8.2V on Pin 25). It
inhibits the H-Drive and B+ outputs.
This activation is internally delayed by 2 lines to
avoid erratic detection (short parasitics).
This protection is latched; it may be reset either by
VCC switch off or by I2C (see Figure 14).
TDA9109A
2.6 Horizontal and Vertical Dynamic Focus
The TDA9109A delivers a horizontal parabola
which is added on a vertical parabola waveform on
Pin 10. This horizontal parabola comes from a
sawtooth in phase advance with flyback pulse middle. The time advance versus horizontal flyback
middle is kept constant versus frequency (about
1µs).
Symmetry and amplitude are I2C adjustable (see
Figure 15). The vertical dynamic focus is tracked
with VPOS and VAMP. Its amplitude can be adjusted. It is also affected by S and C corrections.
This positive signal once amplified is to be sent to
the CRT focusing grids.
Figure 15. Phase of HFocus Parabola
33/47
TDA9109A
3 VERTICAL PART
3.1 Function
3.2 I2C Control Adjustments
When the synchronization pulse is not present, an
internal current source sets the free running frequency. For an external capacitor, COSC = 150nF,
the typical free running frequency is 100Hz.
The typical free running frequency can be calculated by:
1
fo(Hz) = 1.5 . 10-5 .
S and C correction shapes can then be added to
this ramp. These frequency-independent S and C
corrections are generated internally. Their amplitudes are adjustable by their respective I2C registers. They can also be inhibited by their ”select”
bits.
Finally, the amplitude of this S and C corrected
ramp can be adjusted by the vertical ramp amplitude control register.
The adjusted ramp is available on Pin 23 (VOUT) to
drive an external power stage.
The gain of this stage can be adjusted (± 25%) depending on its register value.
The mean value of this ramp is driven by its own
I2C register (vertical position). Its value is
VPOS = 7/16 . VREF-V ± 400mV.
Usually VOUT is sent through a resistive divider to
the inverting input of the booster. Since VPOS derives from VREF-V, the bias voltage sent to the noninverting input of the booster should also derive
from VREF-V to optimize the accuracy (see Application Diagram).
COSC
A negative or positive TTL level pulse applied on
Pin 2 (VSYNC) as well as a TTL composite sync
on Pin 1 can synchronize the ramp in the range
[fmin, fmax] (See Figure 16). This frequency range
depends on the external capacitor connected on
Pin 22. A 150nF (± 5%) capacitor is recommended
for 50Hz to 185Hz applications.
If a synchronization pulse is applied, the internal
oscillator is synchronized immediately but with
wrong amplitude. An internal correction then adjusts it in less than half a second. The top value of
the ramp (Pin 22) is sampled on the AGC capacitor (Pin 20) at each clock pulse and a transconductance amplifier modifies the charge current of
the capacitor in such a way to make the amplitude
constant again.
The read status register provides the vertical LockUnlock and the vertical sync polarity information.
We recommend the use of an AGC capacitor with
low leakage current. A value lower than 100nA is
mandatory.
A good stability of the internal closed loop is
reached by a 470nF ± 5% capacitor value on Pin
20 (VAGC).
34/47
3.3 Vertical Moiré
By using the vertical moiré, VPOS can be modulated from frame to frame. This function is intended
to cancel the fringes which appear when the line to
line interval is very close to the CRT vertical pitch.
The amplitude of the modulation is controlled by
register VMOIRE on sub-address 0C and can be
switched-off via the control bit D8.
TDA9109A
Figure 16. AGC Loop Block Diagram
Charge Current
Transconductance Amplifier
REF
22
Discharge.
VSYNCIN 2
Synchro
OSC
CAP
Sampling
Oscillator
Sampling
Capacitance
S Correction
VS Amp
Polarity
sub-add 07/7bits
Cor_C
sub-add 08/7bits
C Correction
Vlow
18 BREATH
sawth.
disch.
23 VOut
Vert. Amp
VMoiré
sub-.05/7bits
sub.0C/7bits
V Position
sub.06/7bits
3.4 Basic Equations
In first approximation, the amplitude of the ramp
on Pin 23 (VOUT) is:
VOUT - VPOS = (VOSC - VDCMID) . (1 + 0.3 (VAMP ))
where:
VDCMID = 7/16 VREF (middle value of the ramp on
Pin 22, typically 3.6V)
VOSC = V22 (ramp with fixed amplitude)
VAMP = -1 for minimum vertical amplitude register
value and +1 for maximum
VPOS is calculated by:
VPOS = VDCMID + 0.4 VP
where VP = -1 for minimum vertical position register value and +1 for maximum.
The current available on Pin 22 is:
3 .
IOSC =
VREF . C OSC . f
8
where COSC = capacitor connected on Pin 22 and
f = synchronization frequency.
Geometric Corrections
The principle is represented in Figure 17.
Starting from the vertical ramp, a parabola-shaped
current is generated for E/W correction (also
known as Pin Cushion correction), dynamic horizontal phase control correction, and vertical dynamic focus correction.
The parabola generator is made by an analog multiplier, the output current of which is equal to:
∆I = k . (VOUT - VDCMID)2
where VOUT is the vertical output ramp (typically
between 2 and 5V) and VDCMID is 3.6V
(for VREF-V = 8.2V). The VOUT sawtooth is typically centered on 3.6V. By changing the vertical position, the sawtooth shifts by ± 0.4V.
To provide good screen geometry for any end user
adjustment, the TDA9109A has the “geometry
tracking” feature which allows generation of a dissymetric parabola depending on the vertical position.
Due to the large output stage voltage range (E/W
Pin Cushion, Keystone, E/W Corner), the combination of the tracking function, maximum vertical
amplitude, maximum or minimum vertical position
and maximum gain on the DAC control may lead
to output stage saturation. This must be avoided
by limiting the output voltage with appropriate I2C
register values.
35/47
TDA9109A
For the E/W part and the dynamic horizontal
phase control part, a sawtooth-shaped differential
current in the following form is generated:
∆I’ = k’ . (VOUT - VDCMID)
Then ∆I and ∆I’ are added and converted into voltage for the E/W part.
Each of the two E/W components or the two dynamic horizontal phase control components may
be inhibited by their own I2C select bit.
The E/W parabola is available on Pin 24 via an
emitter follower output stage which has to be biased by an external resistor (10kΩ to ground).
Since stable in temperature, the device can be DC
coupled with external circuitry.
The vertical dynamic focus is combined with the
horizontal focus on Pin 10.
The dynamic horizontal phase control drives internally the H-position, moving the HFLY position on
the horizontal sawtooth in the range of ± 2.8 %TH
both for side pin balance and parallelogram.
Figure 17. Geometric Corrections Principle
3.5 E/W
3.6 Dynamic Horizontal Phase Control
EWOUT = EWDC + K1 (VOUT - VDCMID) +
K2 (VOUT - VDCMID)2+ K3 (VOUT - VDCMID)4
K1 is adjustable by the keystone I2C register.
K2 is adjustable by the E/W amplitude I2C register.
K3 is adjustable by the E/W corner I2C register.
IOUT= K4 (VOUT - VDCMID) + K5 (VOUT - VDCMID)2
K4 is adjustable by the parallelogram I2C register.
K5 is adjustable by the side pin balance I2C register.
36/47
TDA9109A
4 DC/DC CONVERTER PART
This unit controls the switch-mode DC/DC converter. It converts a DC constant voltage into the
B+ voltage (roughly proportional to the horizontal
frequency) necessary for the horizontal scanning.
This DC/DC converter can be configured either in
step-up or step-down mode. In both cases it operates very similarly to the well known UC3842.
4.1 Step-up Mode
4.2 Step-down Mode
In step-down mode, the ISENSE information is not
used any more and therefore not sent to the
Pin16. This mode is selected by connecting Pin16
to a DC voltage higher than 6V (for example VREFV).
Operating Description
•
Operating Description
•
•
•
The power MOS is switched-on during the
flyback (at the beginning of the positive slope
of the horizontal focus sawtooth).
The power MOS is switched-off when its
current reaches a predetermined value. For
this purpose, a sense resistor is inserted in its
source. The voltage on this resistor is sent to
Pin16 (ISENSE).
The feedback (coming either from the EHV or
from the flyback) is divided to a voltage close
to 5.0V and compared to the internal 5.0V
reference (IVREF). The difference is amplified
by an error amplifier, the output of which
controls the power MOS switch-off current.
•
The power MOS is switched-on as for the
step-up mode
The feedback to the error amplifier is done as
for the step-up mode
•
The power MOS is switched-off when the
HFOCUSCAP voltage get higher than the
error amplifier output voltage
Main Features
•
•
•
Switching synchronized on the horizontal
frequency
B+ voltage always lower than the DC source
No current limitation
4.3 Step-up and Step-down Mode Comparison
Main Features
In step-down mode the control signal is inverted
compared with the step-up mode.
The reason for this, is the following:
•
•
•
•
Switching synchronized on the horizontal
frequency
B+ voltage always higher than the DC source
Current limited on a pulse-by-pulse basis
The DC/DC converter is disabled:
•
•
•
when VCC or VDD are too low
when X-Ray protection is latched
directly through I2C bus
When disabled, BOUT is driven to GND by a
0.5mA current source. This feature allows to implement externally a soft start circuit.
•
In step-up mode, the switch is a N-channel
MOS referenced to ground and made
conductive by a high level on its gate.
In step-down, a high-side switch is necessary.
It can be either a P- or a N-channel MOS.
– For a P-channel MOS, the gate is controlled
directly from Pin 28 through a capacitor (this
allows to spare a Transformer). In this case, a
negative-going pulse is needed to make the
MOS conductive. Therefore it is necessary to
invert the control signal.
– For a N-channel MOS, a transformer is
needed to control the gate. The polarity of the
transformer can be easily adapted to the negative-going control pulse.
37/47
TDA9109A
Figure 18. DC/DC Convertor
I2 C
DAC
7bits
Horizontal Dynamic
Focus Sawtooth
±Iadjust
Σ
85dB
A
1/3
22kΩ
up
C3
1.3V
EHV
Feedback
VB+
38/47
COMP ISENSE
16
14
1M Ω
down
C2
8V
REGIN
down
1.3V
inhibit
Soft
start
15
12V
+
C1
-
6.2V
5V±20%
HDF Disc
400ns
L
S
R
Q
BOUT
28
up
inhibit
6V
C4
Command step-up/down
TDA9109A
TDA9109A
INTERNAL SCHEMATICS
Figure 19.
Figure 22.
Figure 20.
Figure 23.
HREF
13
12V
R0 6
Figure 21.
Figure 24.
39/47
TDA9109A
Figure 25.
Figure 28.
Figure 26.
Figure 29.
Figure 27.
Figure 30.
40/47
TDA9109A
Figure 31.
Figure 34.
Figure 32.
Figure 35.
Figure 33.
Figure 36.
41/47
TDA9109A
Figure 37.
Figure 38.
Figure 39.
42/47
TDA9109A
Figure 40. Demonstration Board
J14
J16 J15
1
+12 V
DYN
FOCUS
L
47µH
R24
10kΩ
HFOCUSEWOUT 24
CAP
10 FOCUS
OUT
VOUT 23
11 HGND
VCAP 22
C12
12 HFLY
C16 (*)
C27
47µF
1
2
3
4
JP1
C46
1nF
R50
1M Ω
RE GIN
R89
33kΩ
R51
1kΩ
ISENSE
1
R43
10kΩ
C37
33pF
R45 33kΩ
R15
1kΩ
16 ISENSE
B+GND 17
R17
43kΩ
(* *)
C11220 pF
R33
4.7k Ω
R18
10kΩ
(**)
E/W
Q3
TIP122
R5 2
3.9k Ω
C3
47µF
C4
100nF
C2
470nF 100nF
R2
5 .6kΩ
R1
12kΩ
C14
470µF
D1
1n40 04
C1 0
100µF
35V
IC1
TDA81 72
C 41
470pF
C47
100pF
R58
10Ω
TILT
J13
E/W POWER STAGE
TP22
R 31
27 k (**) R38
R19
2.2Ω
J1
270kΩ
3W
Q1
Q2
BC557 BC557
R9
470Ω
R40
36kΩ
BR EATH 18
+5V
C42
1µF
C 43 +5V R30
47µF
10kΩ
C9
100nF
TP6
+12V
-1 2V
TP4 TP3
TP7
C1
R3
220nF 1.5Ω
C10
-12V 470µF
C8
100nF R5
5.6Ω
J2
J3
J6
VGND 19
15 REGIN
R49
22kΩ
C36
1µF
R37
27kΩ
R34
1kΩ
D10
1N4148
C51
22µF
GND
14 COMP
2
+12V
C15
13 HREF VAGCCAP 20
3
D2
1N4148
R7 10kΩ
VR EF 21
C 33 HREF
1 00nF
CON4
C38
33pF
+12V
150nF
J19
PWM0
9
C34
820pF 5%
4
C45
10µF
IC3-STV9422
C49
10 0nF
8 H
XRAY 25
C17 47 0nF POSITION
8MHz
R56
560kΩ
C4 8
10µF
HOUT
TP14
R25
1kΩ
PWM7
C31 4.7µF
FBLK
R 36 1.8kΩ
HOUT
5
PWM1
R53
1kΩ
C13 10 nF
R8
10kΩ
6
VSYNC
+12V
HOUT 26
7
X1
R23
(***)
7 PL L1F
8
PWM6
GND 27
9
TEST
6 R0
12 11 10
B
B+OUT 28
+12V
G
5 C0
C5
100µF
PXCK
C28
820pF 5%
HSYNC
V DD
VCC 29
C6
100nF
C7 22nF
R
R78
10Ω
CKOUT
4 PL L2C
13 14 1 5 16 17 18 19 20 21 22 23 24
GND
SCL 30
SDA
RST
3 HLock o ut
SCL
SDA XTALOUT
SDA 31
PWM2
2 VSYNCIN
C40
22pF
XTALIN
8
R35
+12V 10kΩ
J9
R41
100Ω
C32
100nF
SCL
7
C 25
3 3pF
HFLY
R29
R 42
4.7kΩ 1 00Ω
PWM3
GND
6
PC2
47kΩ
J8
R39
4.7kΩ
PWM5
QA
5
R90
10k
(∗∗)
+12 V R10
1 0kΩ
C22
33p F
C39
22 pF
PWM4
ICC1
MC1 4528
QB
IA
QA
4
9
QB
3
IB
2
L1
22µH
TP10
IB
TA2
TA1
IA
CDB
TB2 CDA
TB1
VCC
1
3 4
+5V
+5V
+5V 32
C30
100µF
TP16
TP17 J12
-12V
1 6 15 14 13 12 11 10
CC4
47pF
TP1
1 H/HVIN
PC1
47kΩ
CC 3
47p F
CC1
100nF
J11
TP13
CC2
10µF
IC4
TDA9109A
2
1
R11
VYOKE 2
220Ω
0.5W
3
R4
1Ω
0.5W
J18
VER TICA L D EFLECTION STAGE
Q4
BC5 57
J17
B+OUT
+12V
TP8
EHT
COMP
R73
R75 1MΩ
10kΩ
R76
47kΩ
R74
10kΩ
P1
10kΩ
R77
15kΩ
D9
1N4148
C 60
1 00nF
D8
1N4148
Q5
BC547
HOUT
L3
22µH
+12V
C50
10µF
(*) op tional
(**) see table
9109A
9111
R7 8
Shorted
Mount ed
R9 0
Removed
Mount ed
R3 1
Mou nted
Re moved
R1 7
270kΩ
43kΩ
R1 8
39kΩ
10kΩ
(***)
For R23=6.49kΩ f 0=22.8 kHz typ
For R 23=5.23kΩ f 0=28.3 kHz typ
43/47
TDA9109A
Figure 41. PCB Layout
44/47
TDA9109A
Figure 42. Components Layout
45/47
TDA9109A
PACKAGE MECHANICAL DATA
32 PINS - PLASTIC SHRINK
E
A
A1
A2
E1
L
C
B
e
B1
Stand-off
eA
eB
D
32
17
1
16
Dimensions
Millimeters
Typ.
Max.
3.759
5.080
Min.
Typ.
Max.
0.140
0.148
0.200
A
3.556
A1
0.508
A2
3.048
3.556
4.572
0.120
0.140
0.180
B
0.356
0.457
0.584
0.014
0.018
0.023
B1
0.762
1.016
1.397
0.030
0.040
0.055
C
.203
0.254
0.356
0.008
0.010
0.014
D
27.43
27.94
28.45
1.080
1.100
1.120
E
9.906
10.41
11.05
0.390
0.410
0.435
E1
7.620
8.890
9.398
0.300
0.350
0.370
0.020
e
1.778
eA
10.16
eB
L
46/47
Inches
Min.
0.070
0.400
12.70
2.540
3.048
3.810
0.500
0.100
0.120
0.150
TDA9109A
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no
responsibility for the consequences of use of such information nor for any infringement of patents or other
rights of third parties which may result from its use. No license is granted by implication or otherwise under any
patent or patent rights of STMicroelectronics. Specifications mentioned in this public ation are subject to change
witho ut notice. This publication supersedes and replaces all information previously supplied.
STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.
The ST logo is a trademark of STMicroelectronics.
 2000 STMicroelectronics - All Rights Reserved
Purchase of I2C Components of STMicroelectronics, conveys a license under the Philip s I2C Patent.
Rights to use these components in a I2C system, is granted provided that the system conforms to the I2C
Standard Specifications as defined by Philip s.
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47/47