STV2001 I2C SINGLE FREQUENCY DEFLECTION PROCESSOR AND 120 MHz RGB PREAMPLIFIER TARGET SPECIFICATION FEATURES ■ Horizontal deflection ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Single Frequency, Self Adaptive Oscillator. TTL compatible positive going sync. Chip does not accept sync on RGB or any video signal. I2C controlled: H-position, pin cushion, keystone, parallelogram, side pin balance. I2C controlled EW corner : top and bottom corrections. I2C controlled corner: top and bottom phase corrections. EW output I2C controlled H-amplitude DC controlled H-width breathing compensation with I2C controlled gain (0.5x to 2x). Xray shut-down on ABL, H output latch, reset by power OFF/ON. Soft start on H-duty. Vertical deflection ■ ■ ■ ■ ■ ■ ■ Vertical ramp generator. Wide range AGC loop. TTL compatible positive going sync, no extra pulses. I2C controlled vertical position. I2C controlled S linearity correction. DC controlled height breathing compensation with I2C controlled gain (0.5X TO 2X). Vertical dynamic focus output with fixed amplitude (1Vpp). Video preamplifier ■ ■ ■ ■ ■ 3-Channel 120MHz bandwidth video amplifier. 3.5ns typical rise and fall time at 2.5VPP. I2C controlled individual RGB contrast (8bit)>8db I2C controlled overall brightness. Activation of ABL results in contrast gain decrease. ■ ■ Gain window (1.5X) controlled by input pulse and I2C. Pulse height controls the gain variation from 1x to 1.5x. 0.514V typical video input signal for normal display. I2C controlled contrast (7bits) update during vertical retrace time. I2C main features ■ ■ ■ I2C interface (slave) 100kHz max. All I2C controlled DAC are 7 bits, except RGB gain. Power on reset on 5 V (VDD). Supply voltage & power ■ ■ 5 V/10.5 V dual supply. Max power consumption: 1.2W DESCRIPTION The STV2001 is an I2C-controlled monolithic integrated circuit assembled in a TQFP44 plastic package. It combines both a deflection block (horizontal and vertical, single frequency with very powerful geometry correction) and a 120MHz RGB pre-amplifier. TQFP44/SLUG DOWN ORDER CODE : Version 1.2 May 2000 This is preliminary information on a new product now in development. Details are subject to change without notice. 1/46 1 TABLE OF CONTENTS 1 - PIN CONNECTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 - PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 - BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 - ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 - THERMAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6 - SYNC INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 7 - I2C READ/WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 8 - HORIZONTAL SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 9 - VERTICAL SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 10 - VIDEO PRE-AMP SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 11 - LOGIC SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 12 - I2C BUS ADDRESS TABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 13 - TYPICAL OUTPUT WAVEFORMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 14 - OPERATING DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 14.1 -GENERAL CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 14.1.1 -Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 14.1.2 -I2C Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 14.1.3 -Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 14.1.4 -Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 14.1.5 -Sync Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 14.1.6 -IC Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 14.1.7 -Sync Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 14.1.8 -Sync Processor Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 14.2 -HORIZONTAL PART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 14.2.1 -Internal Input Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 14.2.2 -PLL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 14.2.3 -PLL2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 14.2.4 -Output Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 14.2.5 -X-RAY Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 14.3 -VERTICAL PART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 14.3.1 -Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 14.3.2 -I2C Control Adjustments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 14.3.3 -Basic Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 14.3.4 -Geometric Corrections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 14.3.5 -E/W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 14.3.6 -Dynamic Horizontal Phase Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 14.3.7 -Vertical Dynamic Focus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 14.3.8 -Corner Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 14.3.9 -Horizontal Breathing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 14.3.10 -Vertical Breathing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 14.4 -GENERAL CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 14.4.1 -Input Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 14.4.2 -Contrast Adjustment (7 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 14.4.3 -ABL Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 14.4.4 -Brightness Adjustment (6 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 14.4.5 -Drive Adjustment (3 x 8 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 . . . . 33 14.4.6 -Output Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 14.4.7 -Bright Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2/3 2 14.4.8 -Blanking Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.5 -GENERAL CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.5.1 -POR (Power On Reset) - Subad. 11-D8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.5.2 -Supply Voltage Threshold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.5.3 -Video Off (I2C control) - Subad. 00-D8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.5.4 -Vertical Output Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.5.5 -X-Ray, Set Operation - Subad. 09-D8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 - INTERNAL SCHEMATICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 - PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 36 36 36 36 36 36 37 45 3/3 STV2001 4/46 3 VBCAP PLL2C HGND Hfly Href Hout PVCC GAINWIN IN1 VBDC IN2 ABLin IN3 VFLYin 44 43 42 41 40 39 38 37 36 35 34 33 1 32 2 31 3 30 4 29 5 28 6 27 7 26 8 25 9 10 24 11 23 12 13 14 15 16 17 18 19 20 21 22 OUT2 PGND OUT3 Hin Vin Vref VAGCCAP VGND VCAP Vout VRB VAVcc OUT1 AGND Co Ro PLL1F FILTER FC1 1 - PIN CONNECTIONS HDGND LGND SAVcc SCL SDA VDD(5V) EWout FCAP HBRTHin VBRTHin VFOCUS STV2001 2 - PIN DESCRIPTION Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Name Hin Vin Vref VAGCCAP VGND VCAP Vout VRB VAVcc OUT1 AGND OUT2 PGND OUT3 PVcc GAINWIN IN1 VBDC IN2 ABLin IN3 VFLYin VFOCUS VBRTHin HBRTHin FCAP EWout VDD SDA SCL SAVcc LGND HDGND Hout Href Hfly HGND PLL2C VBCAP PLL1F Ro Co FC1 FILTER Function Horizontal Sync Input Vertical Sync Input Vertical Section Reference Voltage Vertical AGC Loop Capacitor Vertical Section Ground Vertical Sawtooth Generator Capacitor Vertical Output Vertical Ramp Filter Video Section Analog Supply (10.5V typ) Video Output 1 Video Analog Ground Video Output 2 Video Section Power Ground Video Output 3 Video Section Power Supply (10.5V typ) Gain Window Input Video Input 1 Vertical Blanking Output with DC Level adjusted by DAC Video Input 2 Video Automatic Beam Current Compensation Input Video Input 3 Vertical Fly Back Pulse Input Vertical Dynamic Focus Output Vertical Breathing DC Input Horizontal Breathing Compensation DC Input Filter Capacitor EW Output Bus, Scanning Logic and Video Logic Supply (5V typ) I2C Data Input I2C Clock Input Scanning Section Analog Supply (10.5Vtyp) Bus and Scanning Power Ground H Driver Output Ground Horizontal Driver Output, open collector Horizontal Section Reference Voltage Horizontal Flyback Input, Positive Horizontal Section Ground PLL2 Loop Filter PLL2 Top Comparator Filter PLL1 Loop Filter Horizontal Oscillator Resistor Horizontal Oscillator Capacitor PLL1 Filter Capacitor Horizontal Filter Capacitor (HPOS) 5/46 SAVCC 31 43 Phase Freq Comp Vref 3 Hin 1 Vin 2 Vpos HGND 37 VGND 5 VOSC RAMP Generator 42 36 VCO Vamp Scorr 38 Hout VBCAP HDGND 34 39 33 Corner Phase SPB Tracking VAGCCAP 4 VRB 8 Safety EW OUTPUT EWPCC X2 + Geometry HOUT Buffer Phase Shifter Phase Comp X2 VCAP 6 KeyBal H Breathing + KEYST VFBack EW Corner VFOCUS 23 VDF SDA 29 SCL 30 I2C BUS DECODER Hsync IN1 17 Blanking 22 VFLYin 18 VBDC LATCHES & DACs Contrast Clamp HFly Hsync Vsync 27 EWout 26 FCAP X Vout 7 VDD 28 LGND 32 41 PLL2C Href Href 35 Vref 44 Co HFly Brightness Drive BPCP EHTcomp AMP 25 HBRTHin 24 VBRTHin 9 VAVCC 10 OUT 1 11 AGND Output Stage 15 PVCC IN2 19 GAINWIN 16 Gain WIndow 12 OUT 2 ABL IN3 21 STV2001 20 ABLin 13 PGND 14 OUT 3 STV2001 40 FILTER FC1 Ro 3 - BLOCK DIAGRAM 6/46 PLL1F STV2001 4 - ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit SAVcc Scanning Section Analog Supply Voltage 13.5 V VAVcc Video Section Analog Supply Voltage 13.5 V PVcc Supply Voltage for Video Pre-Amp Section 13.5 V Vdd Logic Section Supply Voltage 5.5 V ESD susceptibility HBM model 100pF & 1.5kΩ 2 300 kV V oC VESD EIAJ Norm 200pF & 0Ω Tstg Storage Temperature -40 to 150 Tj Junction Temperature 150 o 0 to 70 o Toper Operating Temperature (Device ambient) C C 5 - THERMAL DATA Symbol RTH(j-a) Parameter Junction to Ambient Thermal Resistance (MAX) Value 46 Unit oC/W 6 - SYNC INPUT Operating Conditions (V DD = 5V, Tamb = 25°C) Symbol Parameter Test Conditions Min HSVR Voltage on Hin MinD Min Hin pulse duration Mduty Max Hin Duty Cycle VSVR Voltage on Vin 0 VSW Min Vin pulse duration 5 VSD Max Vin Duty Cycle Typ 0 Max Unit 5 V 0.7 us 25 % 5 V us 15 % 0.8 V V Electrical Characteristics (V DD = 5V, Tamb = 25°C) VINTH RIN Horizontal & Vertical Input Logic Level Horizontal & Vertical Pull-Up Resistor Low Level High Level 2.2 200 kΩ 7/46 STV2001 7 - I2C READ/WRITE Electrical Characteristics (V DD = 5V, Tamb = 25°C) Symbol Parameter Test Conditions Min Typ Max Unit 100 kHz FSCL Maximum Clock Frequency TLOW Low Period of the SCL Clock 1.3 us THIGH High Period of SCL Clock 0.6 us VINL SDA & SCL Input Low Level Voltage VINH SDA & SCL Input High Level Voltage VACK Acknowledge Output Voltage on SDA input with 3mA 1.5 3 V V 0.4 V Max Unit 8 - HORIZONTAL SECTION Operating Conditions Symbol Parameter Test Conditions Min Typ VCO Ro(min) Minimum Oscillator Resistor Co(min) Minimum Oscillator Capacitor Fmax 6 kΩ 390 pF Maximum Oscillator Frequency 150 kHz Horizontal FlyBack Input Maximum Current 5 mA Horizontal Drive Output Maximum Sink Current 15 mA OUTPUT SECTION IHFB IHOUT Electrical Characteristics (V DD = 5V, Tamb = 25°C) Symbol Parameter Test Conditions Min Typ Max Unit SUPPLY AND REFERENCE VOLTAGES Vcc Supply Voltage 9.5 10.5 11.5 V Vdd Supply Voltage 4.5 5 5.5 V Icc Supply Current 30 mA Idd Supply Current 5 mA VHREF Horizontal Reference Voltage I=-2mA 7.4 8 8.6 V VVREF Vertical Reference Voltage I=-2mA 7.4 8 8.6 V 8/46 IHREF Horizontal Reference Maximum Source Current 5 mA IVREF Vertical Reference Maximum Source Current 5 mA STV2001 Operating Conditions Symbol Parameter Test Conditions Min Typ Max Unit 3.8 V 1st PLL SECTION Vclamp VCO clamp Voltage range VHREF =8V VVCO VCO clamp Voltage, at POR VHREF =8V 3.8 V AVCO VCO Gain Ro=4868Ω, Co=820pF, dF/dV=1/11RoCo 23 kHz/V HPHASE Horizontal Phase Adjustment Range % of Horizontal Period +/-10 % VPMIN VPTYP VPMAX Horizontal Phase Setting Minimum Typical Maximum SubAdd 07 X1111111 X1000000 X0000000 2.8 3.4 4.0 V V V IPLL1-UL IPLL1-L1 IPLL1-L2 PLL1 Charge Pump Current Unlocked Locked Locked Sub-Address 11 +/-40 +/-1 ±300 µA mA µA 86 kHz fO dfo/dT Free Running Frequency, no input at POR, lower clamp voltage at max. 3.0 x1xx xxxx x0xx xxxx Ro=4868Ω, Co=820pF Free Running Frequency Thermal Drift -150 ppm/oC 2nd PLL SECTION & HORIZONTAL OUTPUT SECTION VTHFB Flyback Input Threshold Voltage JitterH Horizontal Jitter HDC Vphi2 0.65 At 80KHz Horizontal Drive Output Duty Cycle (Ratio of Power Transistor OFF time to Period) Internal Clamp Level on PLL2 Filter VSCinh Threshold Voltage to Stop H-Out, V-Out, Reset ABL when Vcc<VSCinh VsatHD Horizontal Drive Output Saturation Voltage Low Level High Level Iout=15mA 0.75 V 70 ppm 55 % 1.6 4.0 V V 6.9 V 0.4 V 9/46 STV2001 9 - VERTICAL SECTION Symbol Parameter Test Conditions Min Typ Max Unit Electrical Characteristics (V DD = 5V, Tamb = 25°C) VERTICAL RAMP SECTION VRBOT Voltage at Ramp Bottom Point VVREF=8V 2 V VRTOP Voltage at Ramp Top Point with Sync VVREF=8V 5 V VRTOPF Voltage at Ramp Top Point without Sync VVREF=8V VRTOP0.1 V TVDIS Vertical Sawtooth Discharge Time COSC=150nF 70 µs FFRV Vertical Free Running Frequency (S correction inhibited) COSC=150nF 100 Hz ASFR Auto-Sync Frequency Range COSC=150nF RAFD Ramp Amplitude Drift Versus Frequency at Maximum Vertical Amplitude COSC=150nF 50Hz 165Hz 200 ppm/Hz RLIN Ramp Linearity at Vcap pin with S Correction inhibited 2.5V < VOSC < 4.5V 0.5 % VPOS Vertical Position Adjustment Voltage with VOUT mean value Sub-Add=09 X0000000 X1000000 X1111111 3.3 3.65 3.2 3.5 3.8 V V V 2.5 3.5 2.25 3 3.75 V V V VOR Vertical Output Peak to Peak Voltage IVOUT Vertical Output Maximum Current VVRB Vertical Ramp Filter Voltage dVS Max Vertical S-Correction Amplitude S-Correction inhibited, DV/Vpp at TV/4 S-correction Maximum, DV/Vpp at 3TV/4 10/46 Sub-Add=08 10000000 11000000 11111111 50 165 Hz +/-5 mA 2 V Sub-Add 0A 0XXXXXXX -4 % 11111111 +4 % STV2001 Symbol Parameter Test Conditions Min Typ Max Unit EAST/WEST FUNCTION (available without feedback connection) DC Output Voltage with: -Typical VPOS and Keystone inhibited -External driver connected as unity gain buffer 2.0 V TDEWDC DC Output Voltage Thermal Drift (Non-test Parameter) 100 ppm/oC EWPARA Parabola Amplitude with: -Max VAMP -Typ VPOS -Keystone inhibited Sub-add 0C 11111111 11000000 10000000 1.0 0.5 0 V V V Sub-address 08 EWtrack Parabola Amplitude Function of VAMP Control (tracking between VAMP & EW) with: -Typ VPOS=typ. -Keystone=typ. -EW Amplitude=typ. 0.18 0.35 0.57 V V V Sub-address 0B KeyAdj Keystone Adjustment Capability with: -VPOS=typ. -EW= inhibited -Vertical Amplitude= Max. 0.2 0.2 Vpp Vpp Sub-address 09 KeyTrack Intrinsic Keystone Function of VPOS Control (tracking between VPOS and EW) with : -EW Amplitude= Max -Vertical Amplitude=Max A/B Ratio B/A Ratio Sub-address 04 EW Corner Top Corner Adjustment capability with : -VPS=typ, -EW = inhibited -VAMP = max -HSize = Min -HBreath>VREF -Keystone = inhibited Sub-address 15 EW Corner Bottom Corner Adjustment capability with : -VPS=Typ, -EW = inhibited -VAMP = Max -HSize = Min -HBreath>VREF -Keystone = inhibited EWDC 10000000 11000000 11111111 10000000 11111111 X0000000 X1111111 1111 1111 1100 0000 1000 0000 1111 1111 1100 0000 1000 0000 0.52 0.52 +1.25 0 -1.25 Vpp Vpp Vpp +1.25 0 -1.25 Vpp Vpp Vpp 11/46 STV2001 Symbol Parameter Test Conditions Min Typ Max Unit INTERNAL DYNAMIC HORIZONTAL PHASE CONTROL SBPpara SPBtrack ParAdj Partrack Side Pin Balance Parabola Amplitude with: -VAMP=Max, -VPOS=typ. -Parallelogram inhibited Sub-add 0E Side Pin Balance Parabola Amplitude function of VAMP Control (tracking between VAMP & SPB) with -SPB=Max -VPO=typ. -Parallelogram= inhibited Sub-add 08 Parallelogram Adjustment Capability with: -VAMP=Max -POS =Typ -SPB=Max Sub-add 0F Intrinsic Parallelogram Function of VPOS Control (tracking between VPOS and DHPC) with -VAMP=Max -SPB=Max -Parallelogram= inhibited A/B Ratio B/A Ratio Sub-add 09 11111111 10000000 10000000 11000000 11111111 11111111 10000000 X0000000 X1111111 +1.4 -1.4 %TH %TH 0.5 0.9 1.4 %TH %TH %TH +1.4 -1.4 %TH %TH 0.52 0.52 VERTICAL BREATHING COMPENSATION VBRrng Input DC Breathing Control Range Vertical Size Compensation Variation of V output vs full range of VBRrng 1 Sub-address 14 XX00 0000 X100 0000 XX11 1111 10.5 -20 % % % DC Output Level RL=10kΩ 4 V VDFamp VDF Parabola Amplitude with: Vamp = typ VPOS = typ. 1 Vpp VFOCPOL Parabola Polarity at Output = Inverted “U” 1 V VSC -5 V VERTICAL DYNAMIC FOCUS OUTPUT VDFDC VERTICAL FLYBACK INPUT VFLYTH Vertical Flyback Threshold VFLYINH Inhibition of Vertical Flyback input (id pulse in action instead of VFlyback) 6.5 V HORIZONTAL SIZE CONTROL Hsize 12/46 Hsize output DC voltage sitting on top of EWDC=2.0V sub-add 0D X0000000 X1111111 0 2.4 V V STV2001 Symbol Parameter Test Conditions Min Typ Max Unit 10.5 V HORIZONTAL BREATHING COMPENSATION HBRrng HSC Breathing input DC Control Range Horizontal size compensation, EW DC voltage variation under full range of HBRrng 1 Sub-address 12 X000 0000 X100 0000 X111 1111 0.2 V 0.8 V -2.8 +2.8 % % -2.8 +2.8 % % CORNER PHASE CORRECTION Corner Phase Top Corner Phase Bottom Corner Phase Top Adjustment with: Vamp = max Vpos = Typ. SPB = OFF Parrallelogram = OFF Sub-address 05 Corner Phase Bottom Adjustment with: Vamp = max Vpos = Typ. SPB = OFF Parrallelogram = OFF Sub-address 06 1000 0000 1111 1111 0000 0000 0111 1111 10 - VIDEO PRE-AMP SECTION Symbol Parameter Test Conditions Min Typ Max Unit 9.5 10.5 11.5 V 9.5 10.5 11.5 V DC Electrical Characteristics (VAVCC = PVCC = 10.5V, Tamb = 25oC) VAVcc Video Section Analog Supply Voltage PVcc Power Section Supply Voltage IS Supply Current of VAVcc & PVcc 63 VIN Video Input Voltage Amplitude 0.7 VOUT Typical Output Voltage Range VBlack Output (Black level) 0.5 mA 1 Vpp 7 V 1.5 V o AC Electrical Characteristics (VAVCC = PVCC = 10.5V, CL = 5pF, RL = 1KΩ, Tamb = 25 C) Symbol AV Parameter Maximum Gain Condition Max Contrast and Drive I2C Gainwin = 1 VIN = 0.7Vpp Contrast and Drive at POR Min Typ Max Unit 18 dB 30 dB 30 dB CAR Contrast Attenuation Range DAR Drive Attenuation Range GM Gain Match VIN = 0.7Vpp, VOUT = 4Vpp, Contrast and Drive= 0.87Max +-0.1 dB Large Signal Bandwidth VIN=0.7Vpp, VOUT = 2.5Vpp, Contrast and Drive = 0.87Max At -3dB 120 MHz BW 13/46 STV2001 Symbol Parameter DIS Video Output Distortion tR, tF Video Output Rise and Fall Time dVo Overshoot of output with respect to actual output amplitude BRT Brightness max DC level Brightness min DC level RL Tsample Thold CT Equivalent Load on Video Output Test Conditions f=1MHz, VIN=1Vpp, VOUT = 1Vpp CLOAD=5pF Tj<TjMAX Sample time VIN = 0.7Vpp, VOUT = 2.5Vpp, Contrast and Drive=0.7Max f=1MHz Typ Max 0.3 VIN = 0.7Vpp, VOUT =2.5Vpp,Contrast and Drive=0.87Max Hold time Crosstalk Between Video Channels Min Unit % 3.5 4 ns 5 7 % 2.5 0 V V 1 kΩ 100 ms 1 µs 44 dB ABL COMPENSATION RABL ABL Input resistor GABL ABL minimum Attenuation ABL maximum Attenuation THABL ABL latch function activation threshold (High beam current detection) VABL=5.3V VABL=2.8V 10 kΩ 0 12 dB dB 0 1 V 0.7 V GAIN WINDOW VINL Input Low Level Voltage VINH Input High Level Voltage Gain Contrast Gain Increase during High Input VIN = 1.5V VIN = 5.0V TD 14/46 Total Delay Time 1.5 V 1 1.5 V/V V/V 100 ns STV2001 11 - LOGIC SECTION DC Electrical Characteristics (VAVCC = PVCC = 10.5V, Tamb = 25oC) Symbol Parameter Condition Min Typ Max Unit VBDC OUTPUT SECTION Blanking output high voltage VBDC Blanking output low voltage I2C adjustable IBLK Output sink current TBLK Vertical blanking time (start by VSync 2 and by VFly) 7 sub-add10 1X000000 1X111111 V 1 4.5 V V 0.3 mA SUPPLY VOLTAGE THRESHOLD VTHPD1 Supply first threshold voltage 8.5 V VTHPD2 Supply second threshold voltage 6.9 V 15/46 STV2001 12 - I2C BUS ADDRESS TABLE [0] denotes POR value, X denotes unused data bit and must be set to 0. D8 D7 D6 WRITE MODE (SLAVE ADDRESS= 8C) Video 00 1, on [1] [0] [0], off 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 16/46 D5 [1] [0] [1] [1] [1] [0] [1] [1] [1] EWCorner Top/Bottom 0 off [1], on Corner phase Top/Bottom 1, on [0],off Ipump2 1, high [0], low Hout 0, off [1], on Vramp 0, off [1], on Xray 1, reset [0] S Select 1, on [0], off EW Key 0, off [1], on EW Select 0, off [1], on [0] [1] [1] [1] [0] [0] SPB Sel 0, off [1], on Parallelog 0, off [1], on VBDC 1, on [0], off D3 D2 D1 [0] [1] [0] [1] [0] [0] [1] [0] [0] [1] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] Horizontal Amplitude [0] [0] Side Pin Balance [0] [0] [0] [0] [0] [0] [0] [0] [1] [1] Contrast [1] x D4 [1] Drive 1 [0] Drive 2 [0] Drive 3 [0] EW Corner Top [0] Corner Phase Top [1] [0] [0] [0] Corner Phase Bottom [1] [0] [0] [0] Horizontal Phase Adjustment [1] [0] [0] [0] [0] Vertical Ramp Amplitude Adjustment [1] [0] [0] [0] [0] Vertical Position Adjustment [1] [0] [0] [0] S Correction [1] [0] [0] [0] Keystone [1] [0] [0] [0] EW Amplitude [1] [0] [0] [1] [0] [0] [1] [0] [0] [0] [0] Parallelogram [1] Gainwin [0], 1X 1, 1.5X [0] [0] [0] Vertical Blanking DC level [1] [1] [1] [1] STV2001 11 D8 POR [0], off 1, reset 12 13 14 15 x D7 Ipump 1, 1mA [0], 0.3mA D6 D5 D4 D3 Brightness D2 D1 [1] [0] [1] [0] [1] [1] [0] [0] x x x [1] [0] [1] HEHT Comp Gain [0] [0] [0] PLL1 filter voltage clamp (FVC) [0] [0] [0] VEHT Comp Gain [0] [0] [0] EWCorner Bottom [0] [0] [0] [1] [0] [0] READ MODE (SLAVE ADDRESS = 8D) Xray Hlock 1, on 0, lock [0], off [1], unlock Note: Both EW Corner Top and EW Corner Bottom are switched ON/OFF by reg (sub-address 04/D8). [0] [0] [0] [0] 17/46 STV2001 Figure 1. EW Output Referred Voltage B EWPARA A EWDC Figure 2. Dynamic Horizontal Phase Control Output EWPARA B A DHPC DC SPBPARA Figure 3. Keystone Effect on EW Output (PCC Inhibited) Keyadj Figure 4. Vertical Dynamic FOcus Output 4Vdc 18/46 STV2001 13 - TYPICAL OUTPUT WAVEFORMS Function Sub Address Pin Byte Specification 1000 0000 Effect on Screen 2.25V Vertical Size 3.75V 1111 1111 Vertical Position Vertical S Linearity x000 0000 x100 0000 x111 1111 VOUTDC = 3.2 V VOUTDC = 3.5 V VOUTDC = 3.8 V 0000 0000 Inhibited ∆V 1111 1111 Vpp Keystone, EW Inhibited 2V EW Corner Top (Symmetrical) 1000 0000 1.25Vpp 1111 1111 1.25Vpp 2V 19/46 STV2001 Function Sub Address Pin Byte Specification Effect on Screen Keystone, EW Inhibited 2V EW Corner Bottom (Symmetrical) 1000 0000 1.25Vpp 1111 1111 1.25Vpp 2V Keystone, EW Inhibited 2V Corner Phase Bottom (Asymmetrical) 2.8%TH 1000 0000 1111 1111 2V 2.8%TH Keystone, EW Inhibited 2V Corner Phase Top (Asymmetrical) 1000 0000 2.8%TH 1111 1111 2.8%TH EW Inhibited 1000 0000 2V 2.0V 0.2Vpp 2.0V 0.2Vpp Keystone 1111 1111 20/46 STV2001 Function EW Pin Cushion Sub Address Pin Byte EW Inhibited Specification Effect on Screen 2.0 V 1000 0000 1.0 V 2.0 V 1111 1111 1000 0000 H Amplitude 1111 1111 0000 0000 2.5V H Phase 0111 1111 2.5V Parallelogram Inhibited Side Pin Ballance Control 3.7 V 1.4% 1000 0000 1.4% 1111 1111 3.7 V SPB Inhibited Parallelogram Control 1000 0000 3.7 V 1.4% 1111 1111 3.7 V 1.4% 21/46 STV2001 Contrast Register (Video IN = 0.5VPP, Drive at maximum, I 2C Gainwin=1) Hex b7 b6 b5 b4 b3 b2 b1 b0 Vpp G(dB) 0 0 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 1 0.015 -30 0 0 0 0 0 0 1 0 0.031 -24 0 0 0 0 0 1 0 0 0.062 -18 0 0 0 0 1 0 0 0 0.125 -12 0 0 0 1 0 0 0 0 0.25 -6 0 0 1 0 0 0 0 0 0.5 0 0 0 1 1 0 0 0 1 0 1 0 0 0 1 0 0 2 2.812 12 15 0 1 1 1 1 1 1 1 4 18 POR X Brightness Register (Drive at maximum) Hex b5 b4 b3 b2 b1 b0 Vpp 0 0 0 0 0 0 0 POR 0 0 0 0 0 1 0.010 0 0 0 0 0 0 0 1 1 0 0 0 0.020 0.040 0 0 1 0 0 0 0.08 0 1 1 0 0 0 0 0 0 0 0 0 0.16 0.32 0 0 0 0 0 0 0.64 0 1 0 0 0 1 0 1 0 0 0 1 1.28 1.8 1 1 1 1 1 1 2.56 X Drive1, Drive2, Drive3 Registers (Video IN = 0.5VPP, Contrast at maximum, I2C Gainwin=1) Hex 00 b7 0 b6 0 b5 0 b4 0 b3 0 b2 0 b1 0 b0 0 Vpp 0 G(dB) - 01 0 0 0 0 0 0 0 1 0.015 -30 02 0 0 0 0 0 0 1 0 0.031 -24 04 08 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0.062 0.125 -18 -12 10 0 0 0 1 0 0 0 0 0.25 -6 20 40 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0.5 1 0 6 80 1 0 0 0 0 0 0 0 2 12 B4 FF 1 1 0 1 1 1 1 1 0 1 1 1 0 1 0 1 2.812 4 15 18 22/46 4 POR X STV2001 Vertical Blanking Output DC voltage Hex b5 b4 b3 b2 b1 b0 Output dc 0 0 0 0 0 0 1.0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 1 1 1 1 1 1 4.5 POR X 23/46 STV2001 14 - OPERATING DESCRIPTION SCANNING PART 14.1 - GENERAL CONSIDERATIONS 14.1.1 - Power Supply Typical power supply voltages are 10.5 V for the Deflection and Preamplifier sections (SAV CC, VAV CC and PVCC) and 5.0 V for the logic section (Vdd). Optimum operation is obtained between 9.5 and 11.5 for VCC, and between 4.5 and 5.5 V for VDD. VCC is monitored during the transient phase when switched either on or off, to avoid erratic operation of the circuit. If V CC is inferior to 5.0 V typ., the circuit outputs are inhibited. Similarly, before VDD reaches 4 V, all the I2C registers are reset to their default value (see I2C Control Table). The circuit is internally supplied by several voltage references (typ. value: 8 V) to ensure a good power supply rejection. Two of these voltage references are externally accessible respectively for the vertical and horizontal parts. They can be used to bias external circuitry if ILOAD is inferior to 5 mA. To minimize the noise and consequently the "jitter" on vertical and horizontal output signals, the reference voltages must be filtered by external capacitors connected to the ground. To further improve the jitter on both vertical and horizontal sections, FCAP and FILTER pins are used to filter the internal 5V regulator with external decoupling capacitors. 14.1.2 - I2C Control STV2001 belongs to the I 2C-controlled device family. Each adjustment can be made via the I2C Interface, instead of being controlled by DC voltages on dedicated control pins. The I 2C bus is a serial bus with a clock and a data input. General function and bus protocol are specified in the Philips-bus data sheets. The interface (Data and Clock) is TTL-compatible. Spikes up to 50 ns are filtered by an integrator and the maximum clock speed is limited to 100 kHz. The data line (SDA) can be used bidirectionally. In read mode, the IC sends reply information (1 byte) to the micro-processor. The bus protocol prescribes a full-byte transmission in all cases. The first byte after the start condition is used to transmit the IC address (hexa 8C for write, 8D for read). 24/46 5 All bytes are sent MSB bit first and the write data transfer is closed by a stop. 14.1.3 - Write Mode In write mode, the second byte contains the subaddress of the selected function to adjust (or controls to effect) and the third byte the corresponding data byte. More than one data byte can be sent to the IC. If after the third byte no stop or start condition is detected, the circuit automatically increments the momentary subaddress in the subaddress counter (auto-increment mode) by one. Thus it is possible to immediately transmit the following data bytes without sending the IC address or subaddress. This can be useful for reinitializing all the controls very quickly (flash manner). This procedure is ended with a stop condition. There are 22 adjustment capabilities for the circuit: 3 for the horizontal part, 3 for the vertical, 3 for the E/W correction, 2 for the dynamic horizontal phase control, 5 for the preamplifier, 4 for the corners, 2 for EHT compensation and 1 for the blanking DC. 14 bits are also dedicated to several controls (ON/ OFF). 14.1.4 - Read Mode In the read mode the second byte transmits the reply information. The reply byte contains the horizontal and vertical lock/unlock status, the XRAY activation status. A stop condition always stops all the activities of the bus decoder and switches both the data and clock line (SDA and SCL) to high impedance. See I2C subaddress and control tables. 14.1.5 - Sync Processor The internal sync processor allows the device to receive separate horizontal & vertical TTL-compatible sync signals. 14.1.6 - IC Status The IC informs the MCU about both the 1st horizontal PLL (locked or not) and the XRAY protection (activated or not). The XRAY internal latch is reset either directly via the I2C interface or by decreasing the VCC supply. 14.1.7 - Sync Inputs Both HIN and VIN inputs are TTL compatible triggers with hysterisis to avoid erratic detection. Both inputs include a pull-up resistor connected to VDD. Synchro pulses must be positive. STV2001 14.1.8 - Sync Processor Output The sync processor indicates whether 1st PLL is locked to an incoming horizontal sync or not. This is indicated on the D8 bit of the status register . PLL1 level is low when locked. 14.2 - HORIZONTAL PART 14.2.1 - Internal Input Conditions A digital signal (horizontal sync pulse) is sent by the sync processor to the horizontal input. It must be positive (see Figure 5). Synchronization occurs on the leading edge of the internal sync signal. The minimum value of Z is 0.7 µs. Vertical synchro extraction is not allowed. (VCO). The phase comparator is a "phase frequency" type designed in CMOS technology. This kind of phase detector avoids locking on wrong frequencies. It is followed by a "charge pump", composed of two current sources: sunk and sourced (typically I =1 mA when locked and I = 40 µA when unlocked). This difference between lock/unlock allows smooth catching of the horizontal frequency by PLL1. This effect is reinforced by an internal original slow down system when PLL1 is locked, preventing the horizontal frequency from changing too quickly. The dynamic behaviour of PLL1 is fixed by an external filter which integrates the current of the charge pump. A "CRC" filter is generally used (see Figure 6). One bit I2C Ipump is used to set the pump current to 1mA or 0.3mA in locked condition. Figure 5. Figure 6. PLL1F 40 Z T 1.8kΩ 10nF 4.7µF 14.2.2 - PLL1 The PLL1 consists of a phase comparator, an external filter and a voltage-controlled oscillator Figure 7. Block Diagram ²& Lock/Unlock Status I2C Ipump PLL1F 40 R0 41 C0 42 FC1 43 LOCKDET High 1 CHARGE PUMP COMP1 VCO Low OSC 44 FILTER 2 PHASE ADJUST I C HPOS Adj. 25/46 STV2001 Figure 8. Details of VCO I0 I0 2 6.4V PLL1F 40 (Loop Filter) RS FLIP FLOP 1.6V 4 I0 41 (1.4V<V7<6.4V) 42 R0 6.4V C0 1.6V 0 0.875TH TH The VCO uses an external RC network. It delivers a linear sawtooth resulting from the capacitor charge and discharge . The current is proportional to the one in the resistor. Typical thresholds for the sawtooth are 1.6 V and 6.4 V. The VCO control voltage varies between 3.0 V and 3.8 V (see Figure 8). This VCO frequency range is very small. The small effective frequency is due to clamp intervention on the lowest filter value. The PLL1F filter voltage is set by a 4-bit DAC with a voltage range of 3.0 to 3.8 V. The sync frequency must always be higher than the free running frequency. For example, when using a 60 kHz synchro range, the suggested free running frequency is 56 kHz. PLL1 ensures the coincidence between the leading edge of the sync signal and a phase reference resulting from the comparison of: – the VCO sawtooth – an internal DC voltage I2C adjustable within the range of 2.9V to 4.2V (corresponding to ±10%) (see Figure 9). A Lock/Unlock identification block, also included, detects in real time whether PLL1 is locked on the incoming horizontal sync signal or not. The lock/unlock information is available through the I2C read. The FC1 Pin (Pin 43) is used for decoupling the internal 6.4 V reference by a capacitor. Figure 9. PLL1 Timing Diagram H O SC Sawtooth 7/8 TH 1/8 TH 6.4V 3.4V (Reference for H Position) Vb (2.8V<Vb<4.2V) 1.6V Phase REF1 HSynchro Phase REF1 is obtained by comparison between the sawtooth and a DC voltage adjustable between 2.9 V and 4.2 V. The PLL1 ensures the exact coincidence between the signal phase REF and HSYNC. A ±10% TH phase adjustment is possible around the 3.5V point. 26/46 STV2001 14.2.3 - PLL2 PLL2 ensures a constant position of the shaped flyback signal in comparison with the sawtooth of the VCO, taking into account the saturation time Ts (see Figure 10). Figure 10. PLL2 Timing Diagram H Osc Sawtooth 1/8TH 7/8TH 6.4V 4.0V 1.6V Flyback Internally Shaped Flyback H Drive set) is 85% in order to avoid having too long a conduction period of the horizontal scanning transistor. The maximum storage time (Ts Max.) is : 0.44TH- TFLY/2). Typically, TFLY/TH corresponds to around 20 % which means that Ts max represents approxim tively 34 % of TH. 14.2.4 - Output Section The H-drive signal is sent to the output through a shaping stage which also controls the fixed Hdrive duty cycle (see Figure 10). In order to secure the scanning power part operation, the output is inhibited in the following cases : -when VCC is too low, -when the ABL protection is activated, -during the Horizontal flyback, -when the HDrive I2C bit control is off. The output stage consists of a NPN bipolar transistor. Only the collector is accessible (see Figure 12). Emitter is connected directly to a separate ground pin. Figure 12. V CC Ts Duty Cycle The phase comparator of PLL2 (phase type comparator) is followed by a charge pump (typical output current: 0.5 mA). VBCAP pin is used to filter noise on PLL2 top comparator via an external capacitor. The flyback input consists of an NPN transistor. This input must be current driven. The maximum recommended input current is 5 mA (see Figure 11). Figure 11. Flyback Input Electrical Diagram 400Ω HFLY Q1 36 20kΩ GND 0V The duty cycle is fixed at 55%. For a safe start-up operation, the initial duty cycle (after power-on re- 34 Hout 33 HDGND This output stage is intended for "reverse" base control, where setting the output NPN in off-state will control the power scanning transistor in offstate. The maximum output current is 15 mA, and the corresponding voltage drop of the output VCEsat is 0.4 V Max. Obviously, the power scanning transistor cannot be directly driven by the integrated circuit. An interface either bipolar or MOS type has to be added between the circuit and the power transistor. 27/46 STV2001 14.2.5 - X-RAY Protection X-Ray protection is activated when the ABL input (1 V on Pin 20) is at a low level. It inhibits both H-Drive, and Vout while Video goes into off-mode. This activation is internally delayed by 2 lines to avoid erratic detection (short parasitics). This protection is latched; it may be reset either by switching V CC off or by I2C (see Figure 13). Figure 13. Safety Functions Block Diagram VCC Checking HORIZONTA L OUTPUT INHIBITION VCC VSCinh +1V XRAY Protection + ABL 20 I2C Drive on/off VCC off or I2C Reset S R Q I2C Ramp on/off VERTICAL OUTPUT INHIBITION Horizontal Flyback 0.7V Video-off 14.3 - VERTICAL PART 14.3.1 - Function When the synchronization pulse is not present, an internal current source sets the free running frequency. For an external capacitor, COSC = 150nF, the typical free running frequency is 100Hz. The typical free running frequency can be calculated according to: 1 fo(Hz) = 1.5 . 10-5 . COSC A positive TTL level pulse applied on Pin 2 (Vin) is used to synchronize the ramp in the range [fmin, fmax] (see Figure 14). This frequency range depends on the external capacitor connected on Pin 6 (VCAP). A 150nF (± 5%) capacitor is recommended for 50 Hz to 165 Hz applications. The typical maximum and minimum frequency, at 25oC and without any correction (S correction), can be calculated as follows: f(Max.) = 3.5 x fo and f(Min.) = 0.33 x fo When an S correction is applied, these values are slightly modified. With a synchronization pulse, the internal oscillator is synchonized immediately but its amplitude 28/46 changes. An internal correction then adjusts it in less than half a second. The ramp top value (Pin 6) is sampled on the AGC capacitor (Pin 4) at each clock pulse. A transconductance amplifier modifies the charge current of the capacitor so as to make the amplitude constant again. We recommend using an AGC capacitor with a low leakage current. A value lower than 100nA is mandatory. A good level of stability for the internal closed loop is obtained by a 470nF ± 5% capacitor value on Pin 4 (VAGC). VRB (Pin 8) is used for decoupling the internal 2V reference voltage by a capacitor. 14.3.2 - I2C Control Adjustments S correction shapes can then be added to this ramp. This frequency-independent S correction is generated internally. Its amplitudes is adjustable via the I2C. S correction can be inhibited by applying the selected bits. Finally, the amplitude of the S corrected ramp is adjustable via the vertical ramp amplitude control register.The adjusted ramp is available on Pin 7 (VOUT) to drive an external power stage. STV2001 The gain of this stage can be adjusted ( ± 25%) depending on its register value. The mean value of this ramp is driven by its own I2C register (vertical position) with : VPOS = 7/16 x VREF-V = ± 300 mV. Usually VOUT is sent through a resistive divider to the inverting input of the booster. Since VPOS derives from VREF-V, the bias voltage sent to the noninverting input of the booster should also derive from VREF-V to optimize the accuracy (see Figure 14). Figure 14. AGC Loop Block Diagram CHARGE CURRENT TRANSCONDUCTANCE AMPLIFIER REF 6 4 DISCH. VSYNCIN 2 SYNCHRO OSC CAP SAMPLING SAMPLING CAPACITANCE OSCILLATOR S CORRECTION VS AMP SUB0A/7bits Vlow 24 BREATH Sawth Disch. VERT AMP SUB08/7bits VPOSITION SUB09/7bits I2C sub14 /6bits 7 VOUT 14.3.3 - Basic Equations As a first approximation, the amplitude of the ramp on Pin 7 (VOUT) is calculated as follows: VOUT - VPOS = (VOSC - VDCMID) x (1 + 0.25 (VAMP)) where : VDCMID = 7/16 x VREF (middle value of the ramp on Pin 5, typically 3.6V) VOSC = V5 (ramp with fixed amplitude) VAMP = -1 as minimum vertical amplitude register value and +1 as maximum value. VPOS is calculated according to: VPOS = VDCMID + (0.4x V P ) where VP = -1 and +1 as respectively minimum and maximum vertical position register value. The current available on Pin 6 is: 3 x VREF x C OSC x f IOSC = 8 where COSC = capacitor connected on Pin 6 f = synchronization frequency. 14.3.4 - Geometric Corrections The principle is represented in Figure 15. Starting from the vertical ramp, a parabola-shaped current is generated for E/W correction (also known as Pin Cushion correction), dynamic horizontal phase control correction. The parabola generator consists of an analog multiplier, the output current of which is equal to : ∆I = k x (VOUT - VDCMID )2 where VOUT is the vertical output ramp (typically between 2 and 5 V) and VDCMID is 3.6 V (for VREF-V = 8.2V). The VOUT sawtooth is typically centered on 3.6 V. By changing the vertical position, the sawtooth shifts by ±0.4 V. The "geometry tracking" feature ensures a correct screen geometry for any end user adjustment. It generates non-symmetric parabola dependent on the vertical position. To avoid Vertical EHT compensation (VBreathing) from affecting the geometry correction, an additional Buffer Amplifier is used for VBreathing. 29/46 STV2001 Due to the large output stage voltage range (E/W Pin Cushion, Keystone), the combination of the tracking function, maximum vertical amplitude, maximum or minimum vertical position and maximum gain on the DAC control may lead to output stage saturation. This must be avoided by limiting the output voltage with appropriate I 2C register values. For the E/W part and the dynamic horizontal phase control part, a sawtooth-shaped differential current in the following form is generated: ∆I’ = k’ . (VOUT - VDCMID). Then ∆I and ∆I’ are added and converted into voltage for the E/W part. 30/46 Each of the two E/W components or the two dynamic horizontal phase control components may be inhibited by their own I2C select bit. EW output voltage is available at EWout pin directly. External buffer circuit is required to drive Darlington pair transistor, which is sinking the DIODE MODULATOR current in order to achieve EW correction. Additionally, an I2C controlled DC shift is used for H-width. The dynamic horizontal phase control drives the H-position internally, moving the HFLY position on the horizontal sawtooth in the range of ± 2.8 %TH both for side pin balance and parallelogram. STV2001 Figure 15. Geometric Corrections Principle VPOS VAMP From VBreath VOSC VOUT VOUT 7 3.5V VDCMID VDFocus I-V 23 EWAMP 2 3.5V 1 R X Keystone 3.5V EWOUT EWDC 3.5V 1 R + I-V 27 Corner Top X2 Corner Bot. Corner Top 3.5V 1 R X2 Corner Bot. S.P.B. + To Horizontal Phase Parallelog. 3.5V 31/46 STV2001 14.3.5 - E/W EWOUT = EW DC + K1 (VOUT - VDCMID) +K2 (VOUT - VDCMID)2 K1 is adjustable via the keystone I2C register. K2 is adjustable via the E/W amplitude I2C register. 14.3.6 - Dynamic Horizontal Phase Control IOUT= K4 (VOUT - VDCMID) + K5 (VOUT - VDCMID)2 K4 is adjustable via the parallelogram I 2C register. K5 is adjustable via the side pin balance I2C register. Corner Phase Top and Corner Phase Bottom cor14.3.7 - Vertical Dynamic Focus rections add a half parabola current to the HoriVertical Dynamic Focus waveform is available on zontal Phase. Top and Bottom Corrections can be Pin 23. It is the parabolic waveform with downadjusted separately by I2C with 7 Bits DAC. wards concavity, at vertical frequency. Its amplitude is fixed at 1 Vpp. 14.3.9 - Horizontal Breathing 14.3.8 - Corner Correction Horizontal breathing is performed through the EW stage with V-I Converter and an I2C controlled varThere are 4 types of corner correction in the deiable gain stage. This DC controlled input provides vice: EW Corner Top, EW Corner Bottom, Corner the Horizontal Width correction required to offset Phase Top and Corner Phase Bottom. EW Corner width changes due to EHT variation. Gain attenuTop and EW Corner Bottom are used to modulate ation is set by a 7 bits DAC with I2C. the EW amplitude. Corner Phase Top and Corner Phase Bottom are used to modulate the Horizontal 14.3.10 - Vertical Breathing Phase. These 4 types of correction are used to Vertical breathing compensation is performed compensate the distortion appearing at the corthrough gain modulation of the vertical ramp. This ners of the CRT. DC-controlled input allows the vertical height corEW Corner Top and EW Corner Bottom correcrections needed to offset height changes due to tions add a half parabola current to the EW voltEHT variations. Input is received at the output of age. Since the E/W output voltage range is limited, the EHT compensation Amplifier. Gain attenuation it was necessary to add EW Corner Correction to is set by 6 Bits DAC via I2C. decrease both EW amplitude and Keystone by I2C. PRE-AMPLIFIER PART 14.4 - GENERAL CONSIDERATIONS 14.4.1 - Input Stage The R, G and B signals must be supplied to the three inputs through coupling capacitors (100nF). The maximum input peak-to-peak video amplitude is 1 V. The input stage includes a clamping function. This clamp uses the input serial capacitor as "memory capacitor" and is gated by an internally generated "Back-Porch-Clamping-Pulse (BPCP)". The BPCP is synchronized on the second edge of the horizontal pulse HIN inputs on Pin 1. Figure 16. . HSYNC BPCP Internal pulse width is fixed at 1µs In both cases, BPCP width is fixed. 32/46 STV2001 14.4.2 - Contrast Adjustment (7 bits) The contrast adjustment is made by simultaneously controlling the gain of three internal variable gain amplifiers through the I2C bus interface. The contrast adjustment allows covering a range higher than 40 dB. This adjustment is refreshed during the vertical retrace time. 14.4.3 - ABL Control The STV2001 has an ABL input (automatic beam limitation) to attenuate RGB video signals according to beam intensity. The operating range is typically 2.5 V, from 5.3 V to 2.8 V. A typical 12 dB Max. attenuation is applied to the signal whatever the current gain. Refer to Figure 16 for ABL input attenuation range. In the case of software control, the ABL input must be pulled to AVCC through a resistor to limit power consumption. ABL input voltage must not exceed VAVCC. Input resistor is 10kΩ. Figure 17. 2 Attenuation (dB) 0 -2 -4 -6 -8 -10 -12 -14 VIN(V) 1 2 3 4 5 6 7 8 9 14.4.4 - Brightness Adjustment (6 bits) As with contrast adjustment, brightness is controlled by I 2C. The brightness function consists of adding the same DC offset to the three R, G, B signals after contrast amplification. This DC-Offset is present only outside the blanking pulse (see Figure 19). The DC output level is forced to "INFRA-BLACK" level (VDC) during the blanking pulse. 14.4.5 - Drive Adjustment (3 x 8 bits) To adjust the white balance, the device offers the possibility of separately adjusting the overall gain of each complete video channel. Each channel gain is controlled by I2C (8 bits each). The very large drive adjustment range (48dB) allows different standard or custom color temperatures. The drive adjustment is also used to adjust the output voltages at the optimum amplitude to drive the C.R.T drivers, keeping the whole contrast control for end-users only. The drive adjustment is made after the contrast and brightness so that the white balance remains correct when BRT is adjusted. 14.4.6 - Output Stage The three output stages (see Figure 18) incorporate three functions: • The blanking stage: when the internal generated blanking pulse is high, the three outputs are switched to a voltage which is 400 mV lower than the BLACK level. The black level is the output voltage with minimum brightness when the input signal video amplitude is equal to "0". • The output stage itself: a large bandwidth output amplifier which can deliver up to 5VPP on the three outputs (for 0.7 V video signal on the inputs). • The output CLAMP: the IC also incorporates three internal output clamps (sample and hold system) to fix the "INFRA-BLACK" level (VDC) at 1.1V during blanking. The overall waveforms of the output signal according to the different adjustments are shown in Figure 19. and Figure 20. 33/46 STV2001 Figure 18. 10 Vout CRT Driver S/H 1.5V STV2001 Figure 19. Waveforms VOUT, BRT, CONT HSYNC BPCP BLK Video IN VOUT1, VOUT2, VOUT3 VCONT (4) CONT VBRT (3) VBLACK (2) VDC (1) BRT 0.4V fixed Note : 1. VDC = 1.5V 2. VBLACK = VDC + 0.4V 3. VBRT = VBLACK + BRT (with BRT = 0 to 2.5V) 4. VCONT = VBRT + CONT with CONT = k x video (CONT = 5VPP max. for VIN = 0.7VPP) 34/46 STV2001 Figure 20. Waveforms (DRIVE adjustment) HSYNC BPCP HFly Video IN VOUT1 , V OUT2 , VOUT3 VCONT VBRT VBLACK two examples of drive adjustment (1) Note : 1. Drive adjustment modifies the following voltages : VCONT, VBRT . . Drive adjustment does not modify the following voltages : VDC and VBLACK. VDC 14.4.7 - Bright Window Contrast Gain can be increased by 1.5X when the I2C command “GainWin” is issued or GWIN (Pin 16) pulse value reaches its Turn-ON threshold. Bright Window gain can be controlled separately by I2C command or pulse voltage at “GAINWIN” pin. Although both controls are independent, max gain is still limited to 1.5x, not 1.5x + 1.5x. 14.4.8 - Blanking Generator A vertical blanking pulse is generated (see Figure 21). The output level is a positive going pulse of 9.5V. The vertical blanking is started by the vertical sync pulse and by the falling edge of VFly pulse. If there is no VFly pulse (VFly>6.5V), the vertical blanking the vertical blanking start coincides with the beginning of the vertical capacitor discharge time. The blanking output generates a superimposed variable DC voltage. The 6-bit adjustment range is 1 V to 4.5 V. This is used to allow brightness control through G1. Additionally, this pin is used for spot killer suppression. The 0.8 V of Vcc threshold will trigger the output into a high level state resulting from the Vcc decay. Figure 21. VBDC (Pin 18) Output Voltage Waveform DC level controlled by 6-bit DAC 9.5V 4.5 V 1.0 V 35/46 STV2001 Table 1: Logic Table Conditions Vcc at 0 to 6.9 V (PD2 mode) Vcc at 6.9 V to 8.5 V (PD1 mode) Hlock/unlock detection = unlock Video ABL input pin < 1 V 5 V POR or I2C POR=1, (default=0) I2C Hout on/off, (default=1=on) I2C Vout on/off, (default=1=on) I2C Video on/off, (default=0=video-off) Vcc at >8.5 V Vcc at >8.5 V, I2C video=1=on Hout no yes yes no yes on/off yes yes yes yes Vout no yes yes no yes yes on/off yes yes yes Video-off video-off video-off video-off video-off video-off on/off on/off on/off video-on (2) video-on (2) Low Power NA (1) NA(1) no no no no no no NA (1) no Note 1 NA= Not applicable. Note 2 I2C video=on will be reset by Low Vcc. STAND-BY MODE AND PROTECTIONS 14.5 - GENERAL CONSIDERATIONS 14.5.1 - POR (Power On Reset) - Subad. 11-D8 POR is activated on 5 V with default values for each adjustment and in addition video off (see 1.3). It can be activated via the I 2C command. 14.5.2 - Supply Voltage Threshold. Two built-in thresholds (see figure 21) are used to enter the following modes: • PDI mode: – Activated for Vcc < 8.5V – Video off (see 1.13) • PD2 mode: – Activated for Vcc < 5.0V – Video off (see 1.13) – HOUT and VOUT disabled 36/46 14.5.3 - Video Off (I2C control) - Subad. 00-D8 Activates blanking of the 3 video output stages. During this time the outputs are switched to VDC level, regardless of the presence of Hsync or Hflyback. Activation time is inferior to 1µs. This also activates the blanking output at pin 18 into a high level state close to 9.5V as long as “video off” is activated. When the device enters the “Video-off” mode, voltage on pin 8 is 8V. 14.5.4 - Vertical Output Off This command will switch off output VAMP. The vertical output swing is reduced to 0V. 14.5.5 - X-Ray, Set Operation - Subad. 09-D8 When ABL voltage is below 1 V threshold, Xray latch will be activated. This I2C command will reset the Xray latch. Activation time below 100ms. STV2001 15 - INTERNAL SCHEMATICS Figure 22. Figure 25. VDD 200kΩ SAVCC 200Ω Vgnd 1,2 Figure 23. 5 Figure 26. SAVCC SAVCC VCAP 6 Vref 3 22kΩ Figure 24. Figure 27. SAVCC VAGCCAP 4 SAVCC VOUT 7 37/46 6 STV2001 INTERNAL SCHEMATICS (continued) Figure 28. Figure 31. SAVCC Vref VAVCC R1 VRB 8 AGND 11 R2 Figure 29. Figure 32. VAVCC 9 12V BIPSWITCH PGND 13 AGND Figure 30. Figure 33. VAVCC PVCC VAVCC Pins 10, 12, 14 Agnd Pgnd 38/46 PVCC 15 STV2001 INTERNAL SCHEMATICS (continued) Figure 34. Figure 37. VAVCC VAVCC Internal 5V 10kΩ GainWin 16 ABLin 20 Agnd Agnd Figure 35. Figure 38. VAVCC Pins 17 19 21 10k VCC 8V SAVCC IN VFLYIN 22 Agnd AGND Agnd Figure 36. Figure 39. 8V SAVCC VAVCC VFOCUS VBDC 18 23 20 k LGND 39/46 STV2001 INTERNAL SCHEMATICS (continued) Figure 40. Figure 43. SAVCC SAVCC Vref 1.5k V BREATH 24 EWout 27 10k Figure 41. Figure 44. SAVCC 60KΩ VDD 28 HBreath 25 5V BIPSWITCH Vref Figure 42. Figure 45. SAVCC VDD 5V FCAP 10K 26 SDA 29 Internal 5V LGND 40/46 STV2001 INTERNAL SCHEMATICS (continued) Figure 46. Figure 49. SAVCC VDD 5V HOUT 34 10k SCL 30 HDGND 33 Figure 47. Figure 50. SAVCC SAVCC 31 12V Bipswitch Figure 48. Href 35 22kΩ Figure 51. Href 35 SAVCC Lgnd 32 HFLY 36 41/46 STV2001 INTERNAL SCHEMATICS (continued) Figure 52. Figure 55. SAVCC Href PLL1F 40 Hgnd 37 Figure 53. Figure 56. SAVCC Href SAVCC Href 35 PLL2C 38 42 Figure 54. Figure 57. Href Href 35 SAVCC SAVCC 41 VBCAP 39 Lgnd 42/46 STV2001 INTERNAL SCHEMATICS (continued) Figure 58. Figure 59. SAVCC SAVCC Href 1K _ 3 FILTER FC1 43 44 4K _ 3 43/46 Vcc OUT3 OUT2 OUT1 C18 100u L3 10uH VOUT R5 12K C19 100n C14 100n R0 PVCC C0 Out3 STV2001 VFOCUS 23 IN3 VFLYIN VBRTHin 24 HBRTHin 25 FCAP 26 EWout 27 VDD 28 SDA 29 SCL 30 SAVCC 31 LGND 32 Hout HDGND33 Vcc L1 10uH C20 100n C21 100u 12 13 14 15 16 17 18 19 20 21 22 Out2 11 Agnd 10 Out1 9 VAVCC 8 VRB 7 Vout 6 VCAP 5 Vgnd R13 75 C13 150n 820p C1 100n C2 FC1 PGND 4 VAGCCAP 3 Vref VBCAP In1 2 Vin PLL1F GANWIN FILTER ABLin 1 Hin R20 25K R16 75 IN3 IN2 IN1 R19 47 R15 75 R18 47 R14 75 R17 47 C22 100n 470n 6490 R2 1K8 R1 C5 4u7 10n C6 Hfly 1n* 44 43 42 41 40 39 38 37 36 35 34 1u Hgnd In2 C12 R11 1K C7 22n PLL2C VBDC C11 47u R10 1K 100n C8 C23 100n C10 100n R12 1K 47u C9 Href C24 100n VIN Vcc C25 1u C26 100n C28 100n HFLY Vcc Hout Vcc R30 10K Vfly in R32 10K R31 10K VFOCUS EW +5V Vcc (10.5V) R34 560 D1 1N4148 C31 10u R33 1K C27 100u C29 100u R22 1K R23 10K HREF R24 1K R25 10K C4 R26 10K C3 R29 10K HIN R21 10K C30 33p R28 1K R27 10K 44/46 R35 10K Vcc C36 33p R38 10K C35 47p R41 4K7 C37 22p R43 100 R42 100 22p C38 +5V Width C34 100n R39 47K C33 10u R40 4K7 QB 10 NQB 9 6 QA 7 NQA 1B 12 N1B 11 5 N1A 8 GND TB2 14 CDB 13 4 1A TB1 15 VCC 16 3 CDA MC14528 C32 1 TA1 47p 2 TA2 Vcc R37 10K Delay R36 47K GND SCL SDA 5V Vcc STV2001 Figure 60. Demonstration board schematic STV2001 16 - PACKAGE MECHANICAL DATA A A2 TQFP 44 L SLUG DOWN BODY A1 B C Slug down K L L1 D D1 D3 33 23 22 E3 E1 E H S1 34 44 12 Pin 1 Identification 1 e 11 S Dimensions A A1 A2 B c D D1 D3 e E E1 E3 H L L1 S S1 K Min. 1.420 0.065 1.360 0.325 11.900 9.975 7.950 0.750 11.900 9.975 7.950 5.840 0.450 0.938 6.000 6.000 1.5d Millimeters Typ. 0.100 1.400 0.350 12.000 10.000 8.000 0.800 12.000 10.000 8.000 5.890 1.000 3.5d Max. 1.540 0.135 1.440 0.375 0.165 12.100 10.025 8.050 0.850 12.100 10.025 8.050 5.940 1.063 6.100 6.100 5.5d Min. 0.056 0.003 0.054 0.013 0.469 0.393 0.313 0.030 0.469 0.393 0.313 0.230 0.018 0.037 0.236 0.236 1.5d Inches Typ. 0.004 0.055 0.014 0.472 0.394 0.315 0.031 0.472 0.394 0.315 0.232 0.039 3.5d Max. 0.061 0.005 0.057 0.015 0.006 0.476 0.395 0.317 0.033 0.476 0.395 0.317 0.234 0.042 0.240 0.240 5.5d 45/46 7 STV2001 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 2000 STMicroelectronics - All Rights Reserved. Purchase of I2C Components by STMicroelectronics conveys a license under the Philips I2C Patent. Rights to use these components in an I2C system is granted provided that the system conforms to the I 2C Standard Specification as defined by Philips. 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