STMICROELECTRONICS TDA9206

TDA9206
I2C BUS CONTROLLED 130MHz RGB PREAMPLIFIER
.
.
..
.
..
..
.
130MHz TYPICAL BANDWIDTH AT 2VPP
OUTPUT WITH 12pF CAPACITIVE LOAD
2.8ns TYPICAL RISE/FALL TIME AT 2VPP
OUTPUT WITH 12pF CAPACITIVE LOAD
POWERFULL OUTPUT DRIVE CAPABILITY
BRT, CONT, DRIVE, OUTPUT DC LEVEL,
OSD CONTRAST, BACK-PORCH CLAMPING
PULSE WIDTH ARE I2C BUS CONTROLLED
INTERNAL
BACK-PORCH
CLAMPING
PULSE GENERATOR
OSD WHITE BALANCE TRACKING
INTERNAL OSD SWITCHES
BLANKING AND FAST-BLANKING INPUTS
VERY LARGE DRIVE ADJUSTMENT RANGE
(48dB)
SEMI-TRANSPARENT BACKGROUND ON
OSD PICTURE
DIP24
(Plastic Package)
ORDER CODE : TDA9206
PIN CONNECTIONS
The TDA9206 is a digitaly controlled wideband
video preamplifier intended for use in high resolution color monitor. All controls and adjustments are
digitaly performed thanks to I2C serial bus. Contrast, brightness and DC output level of RGB signals are common to the 3 channels and drive
adjustment is separate for each channel. Three I2C
gain controlled OSD inputs can be switched with
RGB signals using fast blanking command. Clamping of RGB signals is performed thanks to a flexible
integrated system. The white balance adjustment
is effective on brightness, video and OSD signals.
The TDA9206works for application usingAC or DC
coupled CRT driver.
Because of its features and due to component
saving the TDA9206 leads to a very performantand
cost effective application.
September 1996
1
24
HSYNC
OSD1
2
23
PVCC1
AVDD
3
22
OUT1
IN2
4
21
PGND1
OSD2
5
20
PVCC2
AGND
6
19
OUT2
IN3
7
18
PGND2
OSD3
8
17
PVCC3
LVDD
9
16
OUT3
LGND
10
15
PGND3
SDA
11
14
BLK
SCL
12
13
FBLK
9206-01.EPS
DESCRIPTION
IN1
1/12
TDA9206
PIN DESCRIPTION
Name
Pin
Type
Function
Name
Pin
Type
IN1
1
I
1 Channel Main Picture Input
FBLK
13
I
Fast Blanking Input
OSD1
2
I
1st Channel OSD Input
Blanking Input
AVDD
3
I
12V Analog VDD
I
15
I/O
3rd Channel Power Ground
OUT3
16
O
3 Channel Output
nd
Channel OSD Input
PVCC3
17
I
3 Channel Power VCC
PGND2
18
I/O
2nd Channel Power Ground
OUT2
19
O
2
I
2
OSD2
5
I
2
AGND
6
I/O
Analog Ground
rd
3 Channel Main Picture Input
I
14
Channel Main Picture Input
4
7
BLK
PGND3
nd
IN2
IN3
Function
rd
rd
rd
nd
Channel Output
nd
Channel Power VCC
OSD3
8
I
3 Channel OSD Input
PVCC2
20
I
LVDD
9
I
12V Logic VDD
PGND1
21
I/O
2
1st Channel Power Ground
LGND
10
I/O
Logic Ground
OUT1
22
O
1 Channel Output
SDA
11
I/O
Serial Data Line
PVCC1
23
I
1 Channel Power VCC
SCL
12
I
Serial Clock Line
HSYNC
24
I
Horizontal Synch Input
st
st
9206-01.TBL
st
BLOCK DIAGRAM
BLK
FBLK
P VCC1
14
13
23
BRIGHTNESS
CLAMP
CO NTRAST
VREF
AVDD
3
IN1
1
AGND
6
BP C P
DRIVE
OUTPUT
STAGE
22 OUT1
21 PGND1
8 bits
IN2
20 PVCC2
BLUE CHANNEL
4
19 OUT2
18 PGND2
7
LVDD
9
GREEN C HANNEL
16 OUT3
17 PVCC3
LGND 10
15 PGND3
BP CP
LATCHES
I2 C
D/A
BUS
DECODER
OSD
CONT
I2 C
VREF
TDA9206
2/12
24
11
12
2
5
8
HS YNC
SDA
SCL
OSD1
OSD2
OSD3
O UTPUT
DC LEVEL
ADJ US T
9206-02.EPS
IN3
TDA9206
FUNCTIONAL DESCRIPTION
Input Stage
The R, G and B signals must be fed to the three
inputs through coupling capacitors (100nF).
The maximum input peak-to-peak video amplitude
is 1V.
The input stage includes a clamping function. This
clamp is using the input serial capacitor as ”memory capacitor” and is gated by an internally generated ”Back-Porch-Clamping-Pulse (BPCP)”.
The synchronization edge of the BPCP is selected
according bit 0 of register R8.
When B0R8 is set to 1, the BPCP is synchronized
on the leading edge of the blanking pulse BLK
inputs on Pin 14 (see Figure 1).
This DC-Offset is present only outside the blanking
pulse (see Figure 3).
The DC output level during the blanking pulse, is
forced to ”INFRA-BLACK” level (VDC).
Drive Adjustment (3 x 8 bits)
In order to adjust the white balance , the TDA9206
offers the possibility to adjust separately the overall
gain of each complete video channel.
The gain of each channel is controlled by I2C (8bits
each).
The very large drive adjustment range (48dB) allows
different standard or custom color temperature.
It can also be used to adjust the output voltages at
the optimum amplitude to drive the C.R.T drivers,
keeping the whole contrast control for end-user only.
The drive adjustment is located after the CONTRAST, BRIGHTNESS and OSD switch blocks, so
that the white balance will remains correct when
BRT is adjusted, and will also be correct on OSD
portion of the signal.
Figure 1
BLK
HSYNC
2
Internal pulse width is controlled by I C
9206-04.EPS
BPCP
When B0R8 is clear to 0, the BPCP is synchronized
on the second edge of the horizontal pulse HSYNC
inputs on Pin 24. An automatic function allows to
use positive or negative horizontal pulse on Pin 24
(see Figure 2).
Figure 2
BPCP
Internal pulse width is controlled by I2C
In both case BPCP width is adjustable by I 2C, B1
and B2 of register R8 (see R8 Table P8).
Contrast Adjustment (8 bits)
The contrast adjustment is made by controlling
simultaneously the gain of three internal variable
gain amplifiers through the I2C bus interface.
The contrast adjustment allows to cover a typical
range of 48dB.
Brightness Adjustment (8 bits)
As for the contrast adjustment, the brightness is
controlled by I2C.
The brightness function consists to add the same
DC offset to the three R, G, B signals after contrast
amplification.
9206-05.EPS
HSYNC
OSD Inputs
The TDA9206 includes all the circuitry necessary
to mix OSD signals into the RGB main-picture. Four
pins are dedicated to this function as follow.
Three TTL RGB On Screen Display inputs
(Pin 2, 5 and 8). These three inputs are connected
to the three outputs of the corresponding ONSCREEN-DISPLAY processor (ex : STV942x).
One Fast Blanking Input (FBLK, Pin 13) which is
also connected to the FBLK output of the same
ON-SCREEN-DISPLAY processor.
When a high level is present on FBLK, the IC will
acts as follow :
- The three main picture RGB input signals are
internally switched to the internal input clamp
reference voltage.
- The three output signals are set to voltages
corresponding to the state (0 or 1) on the three
OSD inputs (see Figure 3).
Example :
If FBLK = 1 and OSD1, OSD2, OSD3) = 1, 0, 1
respectively.
Then OUT1, OUT2, OUT3 will be equal to VOSD,
VBRT, VOSD,
where : VBRT = VBLACK + BRT
VOSD = VBRT + OSD
BRT is the brightness DC level I2C adjustable.
OSD is the On-Screen Display signal value I2C
adjustable from 0V to 4.68VPP by step of 0.312V.
Semi-transparent function is controlled thanks to
Bit 6 of R8 register (see Table 1).
When semi-transparent mode is activated, video
signal is divided by 2 (CONT).
3/12
TDA9206
FUNCTIONAL DESCRIPTION (continued)
Table 1
FBLK OSD1 OSD2 OSD3 B6R8
Output
Signal (OUTn)
0
x
x
x
0
Video
1
x
x
x
0
OSD (1)
0
x
x
x
1
Video
1
0
x
x
1
OSD
1
x
1
x
1
OSD
1
x
x
0
1
OSD
1
1
0
1
1
Semi-transparent (2)
Notes : 1. All OSD colors are displayed.
2. One OSD color is displayed as semi-transparent video
without effect on brightness and DC level adjustment.
- The output CLAMP : The IC also incorporates
three internal output clamp (sample and hold
system) which allow to DC shift the three output
signals. The DC output voltage is adjustable
through I2C with 4 bits. Practicaly, the DC output
level allow to adjust the BLK level
(VDC = 400mV under VBLACK) from 0.9V to 2.9V
with 12 x 165mV.
The overall waveforms of the output signal according to the different adjustment are shown in
Figures 3 and 4.
Serial Interface
The 2-wires serial interface is an I2C interface.
The slave address of the TDA9206 is DC (in hexadecimal).
A6
1
Output Stage
The three output stages incorporate three functions
which are :
- The blanking stage : When high level is applied
to the BLK input (Pin 14), the three outputs are
switched to a voltage which is 400mV lower than
the BLACK level. The black level is the output
voltage with minimum brightness when input
signal video amplitude is equal to ”0”.
- The output stage itself : It is a large bandwidth
output amplifier which allow to deliver up to 5VPP
on the three outputs (for 0.7V video signal on the
inputs). The typical bandwidth is 100MHz at -3dB
measured with 4VPP output signal on 12pF load.
A5
1
A4
0
A3
1
A2
1
A1
1
A0
0
W
0
Data Transfer
The host MCU can write data into the TDA9206
registers. Read mode is not available.
To write data into the TDA9206, after a start, the
MCU must send (see Figure 5) :
- The I2C address slave byte with a low level for the
R/W bit.
- The byte of the internal register address where
the MCU wants to write data(s).
- The data.
All bytes are sent MSB bit first and the write data
transter is closed by a stop.
Figure 3 : Waveforms VOUT, BRT, CONT, OSD
HSYNC
BPCP
BLK
Video IN
FBLK
OSD IN
VOUT1, VOUT2, VOUT3
(4)
VOSD (5)
VBRT (3)
VBLACK
VDC (1)
(2)
Notes : 1.
2.
3.
4.
5.
4/12
OSD
CONT
BRT
0.4V fixed
VDC = 0.5 to 2.5V
VBLACK = VDC + 0.4V
VBRT = VBLACK + BRT (with BRT = 0 to 2.5V)
V CONT = VBRT + CONT with CONT = k x Video IN (CONT = 5VPP max. for VIN = 0.7VPP)
VOSD = VBRT + OSD with OSD = k1 x OSDIN (OSD max. = 5VPP, OSD min. = 312mVPP)
9206-06.EPS
VCONT
TDA9206
FUNCTIONAL DESCRIPTION (continued)
Figure 4 : Waveforms (DRIVE adjustment)
HSYNC
BPCP
BLK
Video IN
FBLK
OSD IN
VOUT1, VOUT2, VOUT3
VCONT
VOS D
VBRT
VBLACK
VDC
9206-07.EPS
Two examples
of drive adjus tment (1)
Note : 1. Drive a djus tm ent modifies the following voltage s : VCONT, VBRT and VO S D.
Drive a djus tm ent do not modify the following voltage s : VDC a nd VBLACK.
Figure 5 : I2C Write Operation
W
SDA
Start
I2C Slave Address
A7
A6
A5
ACK
A4
A3
A2
Register Address
A1
A0
D7
ACK
D6
D5
D4
D3
D2
D1
D0
Data Byte
ACK
Stop
9206-08.EPS
SCL
QUICK REFERENCE DATA
Parameter
Min.
Typ.
Max.
Unit
Signal Bandwidth (2VPP/12pF load)
130
MHz
Rise and Fall Time (2VPP/12pF load)
2.8
ns
Drive Adjustment Range on the 3 Channels separately
48
dB
Maximum Output Voltage (V IN = 0.7 VPP)
5
Output Voltage Range (AC + DC)
V
8
V
5/12
9206-02.TBL
Symbol
TDA9206
Symbol
VS
Parameter
Supply Voltage (Pins 3-9-17-20-23)
Value
Unit
14
V
GND < VIN1 < VS
GND < VIN2 < 5.5
V
V
2
kV
- 40, + 150
°C
VIN1
VIN2
Voltage at any Input Pins (except SDA & SCL)
Voltage at any Input Pins (on SDA & SCL)
VESD
ESD Susceptability (Human body model ; 100pF Discharge through 1.5kΩ)
Tstg
Storage Temperature
Tj
Junction Temperature
150
°C
0, + 70
°C
Toper
Operating Temperature
9206-03.TBL
ABSOLUTE MAXIMUM RATINGS
Symbol
R th (j-a)
Parameter
Value
Junction-ambient Thermal Resistance
Unit
o
62
C/W
9206-04.TBL
THERMAL DATA
DC ELECTRICAL CHARACTERISTICS (Tamb = 25oC, VCC = 12V, unless otherwise specified)
Parameter
Test Conditions
Min.
Typ.
Max.
11.4
12
12.6
VS
Supply Voltage
Pins 3-9-17-20-23
IS
Supply Current (All VS Pin current)
R L = 1kΩ
90
VI
Video Input Voltage Amplitude
Pins 1-4-7
0.7
VO
Typical Output Voltage Range
Pins 16-19-22
VIL OSD
Low Level Inputs OSD, FBLK, BLK, HSYNC
Pins 2, 5, 8, 13, 14, 24
VIH OSD
High Level Inputs OSD, FBLK, BLK, HSYNC
Pins 2, 5, 8, 13, 14, 24
0.5
-
Unit
V
mA
1
VPP
8
V
0.8
V
2.4
V
9206-05.TBL
Symbol
AC ELECTRICAL CHARACTERISTICS
(Tamb = 25oC, VCC = 12V, CL = 12pF, RL = 1kΩ , unless otherwise specified)
Parameter
AV
Test Conditions
Min.
Typ.
Max.
Unit
Maximum Gain (20 log x VOUT AC/VIN AC)
Contrast & Drive at maximum
18
dB
CAR
Contrast Attenuation Range
VIN = 0.7V, BRT, Drive = POR
48
dB
DAR
Drive Attenuation Range
VIN = 0.7V, Contrast, Drive = POR
48
dB
GM
Gain Match
VOUT = 2.5VPP, VIN = 0.7VPP
Contrast = Drive = Maxi x 0.7 (POR)
± 0.1
dB
100
MHz
130
MHz
0.3
%
BW
Bandwidth Large Signal
Bandwidth Small Signal
At -3dB, VIN = 0.7VPP
VOUT = 4VPP,
Contrast = Drive = Maxi x 0.87
VOUT = 2VPP,
Contrast = Drive = Maxi x 0.62
DIS
Video Output Distorsion (see Note)
f = 1MHz, VOUT = 1VPP, VIN = 1VPP
tR, tF
Video Output Rise and Fall Time
(see Note)
VIN = 0.7VPP,
VOUT = 4VPP
Contrast = Drive = Maxi x 0.87
VOUT = 2VPP
Contrast = Drive = Maxi x 0.62
BRT
BRTM
Brightness Maximum DC Level
Brightness Minimum DC Level
Brightness Matching
Note : POR = Power-on Reset Value
6/12
BRT = 50%, Drive = POR
3.8
4.5
ns
2.8
ns
2.5
0
V
V
± 20
mV
9206-06.TBL
Symbol
TDA9206
AC ELECTRICAL CHARACTERISTICS
(Tamb = 25oC, VCC = 12V, CL = 12pF, RL = 1kΩ , unless otherwise specified)
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
OSD
CAR
Contrast Attenuation Range
for OSD Input
24
dB
DC
Output Maximum DC Level
Output Minimum DC Level
2.5
0.5
V
V
RL
Equivalent Load on Video Output
with Tj ≤ Tj Max.
1
kΩ
CT
Croostalk between Video Channels
(see Note 1)
VOUT = 2.5VPP, VIN = 0.7VPP
Contrast = Drive = Maxi x 0.7 (POR)
fIN = 1MHz
fIN = 50MHz
Notes : 1.
2.
0.47
44
34
dB
dB
9206-07.TBL
Symbol
These parameters are not tested on each unit. They are measured during an internal qualification procedure which includes
characterization on batches coming from corners of our processes and also from temperature characterization.
POR = Power-on Reset Value
I2C ELECTRICAL CHARACTERISTICS (Tamb = 25oC, VCC = 12V, unless otherwise specified)
Parameter
VIL
Low Level Input Voltage
VIH
High Level Input Voltage
IIN
Input Current
fSCL(Max.)
VOL
Test Conditions
Min.
Typ.
On Pins SDA, SCL
Max.
Unit
1.5
V
+10
µA
3
0.4V < VIN < 4.5V
V
-10
SCL Maximum Clock Frequency
200
Low Level Output Voltage
kHz
SDA Pin when ACK
Sink Current = 6mA
0.6
V
Max.
Unit
9206-08.TBL
Symbol
Symbol
Parameter
Min.
Typ.
tBUF
Time the bus must be free between 2 access
1300
ns
tHDS
Hold Time for Start Condition
600
ns
tSUP
Set-up Time for Stop Condition
600
ns
tLOW
The Low Period of Clock
1300
ns
tHIGH
The High Period of Clock
600
ns
tHDAT
Hold Time Data
300
ns
tSUDAT
Set-up Time Data
250
tR, tF
Rise and Fall Time of both SDA and SCL
20
ns
300
ns
9206-09.TBL
I2C INTERFACE TIMINGS REQUIREMENTS (See Figure 6)
Figure 6
tBUF
tHDAT
SDA
tHDS
tSUDAT
tSUP
tHIGH
9206-09.EPS
SCL
tLOW
7/12
TDA9206
REGISTER DESCRIPTION
Registers Sub-address
Address (Hex)
Register Names
Function
POR Value
01
Contrast
DAC 8-bit
B4
02
Brightness
DAC 8-bit
B4
03
Drive 1
DAC 8-bit
B4
04
Drive 2
DAC 8-bit
B4
05
Drive 3
DAC 8-bit
B4
06
Output DC Level
DAC 4-bit
08
07
OSD Contrast
DAC 4-bit
08
08
BP and Miscellaneous
See R8 Table
04
Contrast Register (R1) (Video IN = 0.5VPP, Brightness at minimum,Drive at maximum)
Hex
b7
b6
b5
b4
b3
b2
b1
b0
CONT (VPP)
G (dB)
00
0
0
0
0
0
0
0
0
0
-
01
0
0
0
0
0
0
0
1
0.015
-30
02
0
0
0
0
0
0
1
0
0.031
-24
04
0
0
0
0
0
1
0
0
0.062
-18
08
0
0
0
0
1
0
0
0
0.125
-12
10
0
0
0
1
0
0
0
0
0.25
-6
20
0
0
1
0
0
0
0
0
0.5
0
40
0
1
0
0
0
0
0
0
1
6
80
1
0
0
0
0
0
0
0
2
12
B4
1
0
1
1
0
1
0
0
2.812
15
FF
1
1
1
1
1
1
1
1
4
18
POR Value
X
Brightness Register (R2) (Drive at maximum)
Hex
b7
b6
b5
b4
b3
b2
b1
b0
BRT (V)
00
0
0
0
0
0
0
0
0
0
01
0
0
0
0
0
0
0
1
0.010
02
0
0
0
0
0
0
1
0
0.020
04
0
0
0
0
0
1
0
0
0.040
08
0
0
0
0
1
0
0
0
0.080
10
0
0
0
1
0
0
0
0
0.160
20
0
0
1
0
0
0
0
0
0.320
40
0
1
0
0
0
0
0
0
0.640
80
1
0
0
0
0
0
0
0
1.28
B4
1
0
1
1
0
1
0
0
1.8
FF
1
1
1
1
1
1
1
1
2.56
8/12
POR Value
X
TDA9206
REGISTER DESCRIPTION (continued)
Drive Registers (R3, R4, R5) (Video IN = 0.5VPP, Brightness at minimum, Contrast at maximum)
Hex
b7
b6
b5
b4
00
0
0
0
0
01
0
0
0
0
02
0
0
0
0
04
0
0
0
08
0
0
0
10
0
0
20
0
40
0
80
b3
b2
b1
b0
CONT (VPP)
G (dB)
0
0
0
0
0
-
0
0
0
1
0.015
-30
0
0
1
0
0.031
-24
0
0
1
0
0
0.062
-18
0
1
0
0
0
0.125
-12
0
1
0
0
0
0
0.25
-6
0
1
0
0
0
0
0
0.5
0
1
0
0
0
0
0
0
1
6
1
0
0
0
0
0
0
0
2
12
B4
1
0
1
1
0
1
0
0
2.812
15
FF
1
1
1
1
1
1
1
1
4
18
POR Value
X
Output DC Level Register (R6)
Hex
b7
b6
b5
b4
b3
b2
b1
b0
DC (V)
03
0
0
0
0
0
0
1
1
0.52
04
0
0
0
0
0
1
0
0
0.69
08
0
0
0
0
1
0
0
0
1.35
0F
0
0
0
0
1
1
1
1
2.5
POR Value
X
Code 00Hex, 01Hex and 02Hex : not to be used
OSD Contrast Register (R7) (VOSD IN = 2.4VMin.., Drive at maximum)
Hex
b7
b6
b5
b4
00
0
0
0
0
01
0
0
0
0
02
0
0
0
0
04
0
0
0
08
0
0
0
0F
0
0
0
b3
b2
b1
b0
OSD (V)
G (dB)
0
0
0
0
0
-
0
0
0
1
0.312
-24
0
0
1
0
0.625
-18
0
0
1
0
0
1.25
-12
0
1
0
0
0
2.5
-6
0
1
1
1
1
4.68
0
POR Value
X
BP and Miscellaneous Register (R8)
b7
b6
b5
b4
b3
b2
b1
b0
Function
0
BP Source = HSYNC
1
BP Source = BLK
0
0
BP Pulse Width = 0.33µs
0
1
BP Pulse Width = 0.66µs
1
0
BP Pulse Width = 1µs
1
1
BP Pulse Width = 1.3µs
POR Value
X
X
0
0
Test Purposes
X
0
0
0
Soft Blanking OFF
X
1
1
1
Soft Blanking ON
0
Semi Transparent OFF
1
Semi Transparent ON
X
Unused
9/12
TDA9206
INTERNAL SCHEMATICS
Figure 7
Figure 8
AVDD
AVDD
IN
P ins
1-4-7
OS D - BLK - FBLK
P ins 2-5-8-13-14
Figure 9
AGND
AGND
9206-11.EPS
AGND
9206-10.EPS
AGND
Figure 10
AVDD
AVDD
3
(20V)
6
Figure 11
9206-13.EPS
AGND
9206-12.EPS
LVDD 9
AGND
Figure 12
AVDD
S DA
S CL
P ins
11-12
LGND 10
(10V)
9206-14.EPS
AGND
AGND
Figure 13
LGND
9206-15.EPS
LGND
Figure 14
P VCC
AVDD
Pins 17-20-23
AVDD
HSYNC 24
OUT
P ins 16-19-22
10/12
AGND
P GND
Pins 15-18-21
9206-17.EPS
LGND
9206-16.EPS
AGND
TDA9206
APPLICATION DIAGRAM
BLK
HSYNC
VSYNC
S YNCHRO
EXTRACTO R
+12V
100nF
47Ω
B
GND B
1kΩ
75Ω
100nF
47Ω
R
GND R
1kΩ
75Ω
100nF
47Ω
100nF
1kΩ
G
GND G
75Ω
100nF
1
IN1
2
OS D1
HS YNC 24
P VC C 1 23
3
AVDD
OUT1 22
4
IN2
5
OS D2
6
AGND
7
IN3
8
OS D3
9
LVDD
T
D
A
9
2
0
6
BLUE OUT
P GND1 21
P VC C 2 20
OUT2 19
100nF
RED OUT
P GND2 18
P VC C 3 17
OUT3 16
100nF
GR EEN OUT
P GND3 15
10 LGND
11 S DA
BLK 14
12 S CL
FBLK 13
GND
100nF
1kΩ
GND
+5V
100nF
+5V
2
VSYNC
3
HS YNC
4
VDD
5
P XCK
6
CKOUT
7
XTAL OUT
8
XTAL IN
TEST 16
S
T
V
9
4
2
6
B 15
G 14
2.7k Ω
FBLK
R 13
GND 12
RES ET 11
100Ω
SDA 10
S DA
I2 C BUS
SCL
S CL
9
10µF
16V
9206-18.EPS
33pF
33pF
8MHz
1
22pF
11/12
TDA9206
PM-DIP24.EPS
PACKAGE MECHANICAL DATA
24 PINS - PLASTIC DIP
a1
b
b1
b2
D
E
e
e3
F
i
L
Min.
Millimeters
Typ.
0.63
0.45
0.23
Max.
Min.
0.31
0.009
1.27
Max.
0.012
0.050
32.2
16.68
15.2
Inches
Typ.
0.025
0.018
1.268
0.657
0.598
2.54
27.94
0.100
1.100
14.1
4.445
3.3
0.555
0.175
0.130
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility
for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result
from its use. No licence is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics.
Specifications mentioned in this publication are subject to change without noti ce. This publication supersedes and replaces all
information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life
support devices or systems without express written approval of SGS-THOMSON Microelectronics.
 1996 SGS-THOMSON Microelectronics - All Rights Reserved
Purchase of I2C Components of SGS-THOMSON Microelectronics, conveys a license under the Philips
I2C Patent. Rights to use these components in a I2C system, is granted provided that the system confo rms to
the I2C Standard Specifications as defined by Philips.
SGS-THOMSON Microelectronics GROUP OF COMPANIES
Australia - Brazil - Canada - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco
The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
12/12
DIP24.TBL
Dimensions