VS6552 VGA Color CMOS Image Sensor Module FEATURES ■ Small physical size ■ Ultra low power standby mode ■ SmOP (Small Optical Package) technology featuring integrated lens ■ Class leading low light performance ■ VGA resolution sensor ■ Compatible with STV0974 companion mobile processor ■ High frame rate to minimize image distortion ■ Low EMI link (VisionLink) to STV0974 ■ On-chip 10-bit ADC ■ Automatic dark calibration ■ I2C communications ■ On-chip PLL DESCRIPTION The VS6552 is a VGA resolution SmOP sensor module. SmOP technology combines the image sensor and fixed focus lens system in a single module. This approach provides a number of advantages: – SmOP technology is suitable for high volume manufacturing – SmOP can be plugged into a PCB mounted flow soldered socket – SmOP can be mounted close to noisy RF source as differential signalling used to transmit data has good immunity from radio interference. The sensor outputs raw Bayer colorized data to the STV0974 companion mobile processor. STV0974 then performs all color processing and exposure control functions before outputting the data in an appropriate interface format like YCbCr, RGB or JPEG. October 2004 VS6552 offers an ultra low power standby mode that consumes less than 15 µW. The SmOP lens has been designed to combine class leading low light performance with good depth of field to ensure excellent overall optical performance. The lens is a 2 element moulded plastic design. The output data and qualification clock are transmitted over low noise, low voltage and fully differential links. VS6552 configuration registers are controlled via a private I2C interface to STV0974. APPLICATIONS Mobile phone embedded camera system ■ ■ PDA embedded camera or accessory camera ■ Wireless security camera Table 1. Technical Specifications Pixel resolution 644 x 484 (VGA) Pixel size 5.6 µm x 5.6 µm Exposure control +81 dB Analog gain +24 dB (max) Dynamic range 60 dB (Typical) Signal to noise at 50cd.m2 37 dB (Typical) Supply voltage 2.8 V (analog supply) 1.8 V (digital supply) Power consumption <75 mW (@30 frame/s) <15 µW (standby mode) Package size 10.7mm x 8.7mm x 6mm:SmOP1.5 9.5mm x 8.5mm x 6.1mm :SmOP2 Lens 45o HFOV, f# 2.8 Package type 14 pad SmOP System attach Socket or flexible circuit Rev. 2 1/26 VS6552 Table 2. Order Codes Operating Temperature Package VS6552V015/T2 [ -25; +55 ] °C SmOP1.5 VS6552V02C/T2 [ -25; +55 ] °C SmOP2M VS6552V02D/T2 [ -25; +55 ] °C SmOP2ME Part Number 2/26 VS6552 TABLE OF CONTENT Overview ........................................................................................................................................... 4 Sensor Overview 4 Signal Description ........................................................................................................................... 5 Functional Description .................................................................................................................... 6 Analog Video Block 6 Digital Video Block 6 Device Operating Modes 7 Power Management 7 Clock and Frame Rate Timing 8 Control and Video Interface Formats 9 Electrical Characteristics ................................................................................................................ 9 DC Electrical Characteristics 10 AC Electrical Characteristics 10 ESD Handling Characteristics 13 Optical specification...................................................................................................................... 13 Defect Categorization .................................................................................................................... 13 Pixel Defects 13 Package Mechanical Data ............................................................................................................. 13 SmOP1.5 Module Outline 13 SmOP2 M Module Outline 13 SmOP2 ME Module Outline 13 Application Information................................................................................................................. 23 Socket 23 EMC and Shielding 23 Revision History............................................................................................................................. 25 3/26 VS6552 1 OVERVIEW 1.1 Sensor Overview The VS6552 VGA image sensor produces raw VGA digital video data at up to 30 frames per second. The image data is digitized using an internal 10-bit column ADC. The resulting 10-bit output data includes embedded codes for synchronization. The data is formatted and transmitted over a fully differential link. The data is accompanied by a qualifying clock that is transmitted over an identical fully differential link. The sensor is fully configurable using an I2C interface. The sensor is optimized for high volume mobile applications 1.1.1 Typical Application - Mobile Application The VS6552 is an image sensor, it should be used in conjunction with the STMicroelectronics STV0974 companion processor. The coprocessor and the sensor together form a complete imaging system. The sensors main function is to convert the viewed scene into a data stream. The companion processor function is to manage the sensor so that it can produce the best possible data and to process the data stream into a form which is easily handled by up stream mobile baseband or MMP chipsets. The sensor supplies high speed clock signal to the processor and provides the embedded control sequences which allow the co processor to synchronize with the frame and line level timings. The processor then performs the color processing on the raw image data from the sensor before supplying the final image data to the host. Figure 1. Camera System Using STV0974 STV0974 VS6552 Microprocessor Interface Logic MSCL ADC Digital Logic MSDA Pixel Array PCLKP PCLKN VP VC SCL SDA PDATAP PDATAN DIO[0:13] CLK PDN 4/26 VS6552 2 SIGNAL DESCRIPTION Table 3. Signal Description Pad Number Pad Name I/O Type Description Power supplies 1 CEXT PWR Connection to capacitora 2 AGND PWR Analog ground 3 AVDD PWR Analog power 8 GND PWR Digital ground 11 VDD PWR Digital power 4 PDN I Power down controlb 5 CLK I System clock input 6 MSCL I Serial communication clock 7 MSDA I/O Serial communication data 9 PCLKN vLVDS output Output qualifying clock 10 PCLKP vLVDS output Output qualifying clock 12 PDATAN vLVDS output Serial output data 13 PDATAP vLVDS output Serial output data System Control Data Not connected 14 Not connected NC Not connected a.Internally generated voltage that needs to be externally decoupled with a 100 nF, 5 V capacitor b.Signal is active low Note: The physical position of the signals on the package can be found by refering to the pinout information in Chapter 7: Package Mechanical Data. 5/26 VS6552 3 FUNCTIONAL DESCRIPTION 3.1 Analog Video Block The first sections of this chapter detail the main blocks in the device: ■ Analog video block 3.1.1 Features ■ Digital video block The later sections of this chapter describe other functional aspects of the device. Device level operating modes, including suspend, are detailed ■ ADC: 10-bit A/D converter - SRAM readout ■ Dynamic range 60 dB (typical) ■ SNR 37 dB @ 50 cd.m2 (typical) Figure 2. Analog Video Block SRAM readout raw sensor data Timing signals X-Address Column ADC Power management Digital logic VGA pixel array Timing signals Y address 3.1.2 Analogue Block Diagram ■ Fixed pattern noise (FPN) data gathering The analog video block from Figure 4, consists of a VGA resolution pixel array, power management circuitry. The digital block provides all timing signals to drive the analog block. Pixel voltage values are read out and digitized using the address decoders and column ADC ■ Line and frame statistics gathering ■ On-chip Power-On-Reset cell ■ Single video output format: VGA 640 x 480 ■ H - Scaler function to aid software only viewfinder implementations 3.2 Digital Video Block 3.2.1 Features ■ Frame rate: 30 frame/s max. (VGA) can be reduced down to less than 3 frame/s (VGA) ■ Automatic dark calibration to ensure consistent video level over varying scenes 6/26 3.2.2 Dark Calibration Algorithm VS6552 runs a dark calibration algorithm on the raw image data to control the video offsets caused by dark current. This ensures that a high quality image is output over a range of operating conditions. First frame dark level is correctly calibrated, for subsequent frames the adjustment of the dark level is damped by a leaky integrator function to avoid possible frame to frame flicker. VS6552 3.2.3 Image Statistics VS6552 generates image statistics which can be used by STV0974 as an input to an auto exposure controller (AEC), automatic gain controller (AGC) and automatic white balance (AWB). . 3.3 Device Operating Modes PLL power down. The internal video timing is reset to the start of a video frame in preparation for the enabling of active video. The values of the serial interface registers like exposure and gain are preserved. The system clock must remain active to allow communication with the sensor. 3.3.3 Clock Active Mode 3.3.1 Standby This is the lowest power consumption mode. I2C communications to STV0974 are not supported in this mode. The clock input pad, PLL and the video blocks are powered down. This mode is similar to ‘sleep mode’ except that the PLL is now powered up to permit a PCLKP/ PCLKN signal to be delivered to STV0974. The PDATAP/PDATAN pads remain inactive. The video block is powered down. 3.3.4 Idle Mode 3.3.2 Sleep Mode Sleep mode preserves the contents of the I2C register map. I2C communications to STV0974 are supported in this mode. The sleep mode is selected via a serial interface command sent by STV0974. The data pads go high at the end of the current frame. At this point the video block and VCAP is generated. The analog video block is now powered up but the array is held in reset and the output PDATAP/PDATAN pads remain high. 3.3.5 Video The VS6552 streams live video to the STV0974. Table 4. VS6552 Power-up Sequence Design block powered down Mode Video data inhibit I2C Digital PLL & CLK pinsa b Standby (PDN low) Yes Yes Yes Yes Yes Yes Sleep No Yes Yes Yes Yes Yes Clock active No No No Yes Yes Yes Idle No No No No No Yes Video No No No No No No Output pins Analog a.PLL (Phase Locked Loop) generates fast system clock for STV0974 b.PLL, PCLKP and PCLKN pins 3.4 Power Management 3.4.1 Power-up, Power-down Procedures VS6552 requires a dual power supply. The analog circuits are powered by a nominal 2.8 V supply while the digital logic and digital I/O are powered by a nominal 1.8 V supply. The power up and power down procedures are detailed in the following Figure 3. 7/26 VS6552 Figure 3. VS6552 Power-up Sequence Standby Sleep Clock active Streaming Idle VDD (1.8V) AVDD (2.8V) PDN CLK PCLKP/N PDATAP/N MSDA MSCL Mode Change: Sleep -> Clock active Mode Change: Clock active -> Idle and enable data qualification clock and general configuration 3.4.2 Active Signals with Unpowered VS6552 All signals going into the VS6552 must be either at a low state or high impedance when power is removed from the device. The exceptions to this rule are the I2C lines which may be at a low or high state and the clock which can be active. Mode Command: Idle -> Streaming also enable data output defined in Table 5. The input clock pad accepts up to 26 MHz signals. Table 5. System Input Clock Frequency Range System clock frequencya Min. (MHz) Max. (MHz) 6.5 26 3.5 Clock and Frame Rate Timing 3.5.1 Video Frame Rate Control The output frame rate of VS6552 can be reduced by extending the frame length. The extension is achieved by adding 'blank' video lines to act as timing padding. This is advantageous as it does not reduce the pixel readout rate and therefore does not introduce unwanted motion distribution effects to the image. The frame rate can be reduced from the default 30 frame/s at VGA resolution to less than 3 frame/s at VGA resolution. 3.5.2 PLL and Clock Input A PLL IP block is embedded. This block generates all necessary internal clocks from an input range 8/26 a.The standard supported input frequencies (in MHz) are as follows: 6.5, 8.4, 9, 9.6, 9.72, 12,13, 16.8, 18, 19.2, 19.44, 26. 3.5.3 Clock Input Type VS6552 can receive the following clock types: Single ended CMOS ■ ■ Single ended Sine wave ■ Clock can be AC or DC coupled The clock is fail-safe. VS6552 3.6 Control and Video Interface Formats 3.6.1 Overview Data is transferred from VS6552 to STV0974 via a high speed serial link (VisionLink). The serial data link comprises of two pairs of wires. The serial control data is transferred between the VS6552 to STV0974 via a private I2C bus. 3.6.2 VisionLink Physical Layer Data signals (PDATAP and PDATAN) and clock signals (PCLKP and PCLKN) are transferred from VS6552 to STV0974 via 2 pairs of balanced 100 Ω impedance transmission lines. The transmission line pairs and custom transmitters/receivers realize a very low voltage differential (vLVDS) signalling scheme that can transfer information in a potentially noisy environment. As implemented in VS6552, VisionLink supports the transmission of raw Bayer data at VGA resolution up to 30 frame/s. 3.6.3 Serial I2C Control Bus The internal registers in VS6552 can be configured by STV0974 via a private I2C bus. STV0974 is the bus master and VS6552 is the single slave. VS6552 sends and receives commands over this bus at up to 400 kHz. 4 ELECTRICAL CHARACTERISTICS Table 6. Absolute Maximum Ratings Symbol Parameter Values Unit VDIG Digital power supply -0.5 to 3.0 V VANA Analog power supply -0.5 to 3.6 V MSCL, MSDA CCI Signals -0.3 to VDIG + 0.3 V PDN, CLK Power Down Control, System Clock Input -0.3 to VDIG + 0.3 V TSTO Storage temperature -40 to + 85 oC Note: Caution: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 7. Operating Conditions Symbol ParTyp.ameter Min. Typ. Max. Unit Voltage VDD Digital power supply voltage 1.7 - 1.9 V AVDD Analog power supply voltage 2.5 - 3.3 V TAF Temperature (functional operating) -30 - +70 °C TAN Temperature (normal operating) -25 - +55 °C TAO Temperature (optimal operating) +5 - +30 °C Temperature Note: 1. 2. 3. 4. Storage temperature: Camera has no permanent degradation Functional operating temperature: Camera is electrically functional Normal operating temperature: Camera produces ‘acceptable’ images Optimum performance temperature: Camera produces optimal optical performance 9/26 VS6552 4.1 DC Electrical Characteristics Note: Typical values quoted for nominal voltage and temperature. Maximum values quoted for worse case operating conditions unless otherwise specified. Table 8. Power Supply VDIG, VANA Typ. Max. Typ. Max. Unit Parameter Digital Analogue Standby 1 5 NMa <2 µA Video, 30fps 15 20 9 15 mA a.Not Measurable - current is below the minimum calibrated measurement capabilities of the test system (1µA) Table 9. System Clock Symbol Parameter Min. Leakage current Typ. Max. Unit 8a 29b µA Typ. Max. Unit - 0.3 VDIG V a.With DC coupled square wave clock b.With DC 1V9 signal level applied Table 10. I2C Interface - MSDA, MSCL Symbol Parameter description Min. VIL Low level input voltage VIH High level input voltage VOL Low level output voltageb,c - 0.2 VDIG V IIL Low level input current - -10 µA IIH High level input current - 10 µA f Operating frequency range - 400d kHz 0.7 VDIGa 0 - V a.For positive electrostatic discharges above 500 V, a shift of VIH may happen. However, the device remains fully functional even for a stress up to 2000 V included, and VIH<0.9 VDIG. Refer to the STV0974 datasheet for recommendations on MSCL/MSDA usage. b.VOH not valid for CCI c.1 mA drive strength d.For external clock frequencies <19.2MHz Max limit is 200KHz 4.2 AC Electrical Characteristics Table 11. System Clock Symbol Parameter description VCL DC coupled square wave (low level) VCH DC coupled square wave (high level) VCAC AC coupled sine wave 10/26 a Min. Typ. Max. Unit - 0.3 VDIG V 0.7 VDIG 0.5 V 1.0 1.2 V VS6552 Symbol fCLK Parameter description Min. Typ. Max. Unit a 6.5 - 1%a - 26 + 1%b MHz Min. Max. Unit 400 kHz Clock frequency input a.Nominal frequencies are 6.5 to 26MHz with a 1% center frequency tolerance Table 12. Timing Characteristics Symbol Parameter description tMSCL MSCL clock frequency 0 tLOW Clock pulse width low 1.3 µs tHIGH Clock pulse width high 0.6 µs tSP Pulse width of spikes which are suppressed by the input filter tBUF Bus free time between transmissions 1.3 µs tHD.STA Start hold time 0.6 µs tSU.STA Start set-up time 0.6 µs tHD.DAT Data in hold time 0 tSU.DAT Data in set-up time tR MSCL/MSDA rise time 20+0.1Cba 300 ns tF MSCL/MSDA fall time 20+0.1 Cb 300 ns tSU.STO Stop set-up time Ci/o Input / Output capacitance (MSDA) 8 pF Cin Input capacitance (MSCL) 6 pF 0 50 0.9 100 ns µs ns µs 0.6 a.Cb = total capacitance on the lines Figure 4. CCI AC characteristics stop start start MSDA stop ... tBUF tLOW tR tHD.STA tF MSCL ... tHD.STA tHD.DAT tHIGH tSU.DAT tSU.STA tSU.STO Note: The VS6552 maximum I2C frequency of 400 kHz is only valid for external clock frequencies at or above 19.2 MHz. Due to a design issue, for external clock frequencies below 19.2MHz, the maximum guaranteed I2C frequency is limited to 200 kHz. 11/26 VS6552 Table 13. vLVDS Interface AC Electrical Characteristics Symbol Parameter description Min. Typ. Max. Unit Vod Differential voltage swinga,b 100 150 200 mV Vcm Common mode voltage (self biasing) 0.8 0.9 1.0 V RO Output Impedance 40 140 W IDR Drive current range (internally set by bias circuit) 0.5 1.5 2 mA Min. Typ. Max. Unit - - 120 MHz a.Supplies of VDIG = 1.8 V and VANA = 2.8 V, Temperature = 25 °C b.Measured over a 100 Ohm load Table 14. vLVDS TIming Characteristics Symbol Parameter fPCLKP/ PCLKN PCLKP/PCLKN clock frequency tPCLKP/ PCLKP/PCLKN clock period 8.3 - 100 ns PCLKP/PCLKN duty cycle 26 - 74 % PCLKN tLOW Low period of PCLKP/PCLKN 1.66 - ns tHIGH High period of PCLKP/PCLKN 1.66 - ns tRISE Rise time of PDATAP/PDATAN, PCLKP/ PCLKN 0.3 - 0.5 ns tFALL Fall time of PDATAP/PDATAN, PCLKP/ PCLKN 0.3 - 0.5 ns tHD;DAT Data hold time 3 - - ns tSU;DAT Data set-up time 1 - - ns Figure 5. VisionLink AC timing tPCLKP/PCLKN PCLKP/ PCLKN VDIG/2 tLOW tRISE tHIGH PDATAP/ PDATAN VDIG / 2 tSU;DAT 12/26 tFALL tHD;DAT VS6552 4.3 ESD Handling Characteristics 6 DEFECT CATEGORIZATION Table 15. ESD Handling Limits 6.1 Pixel Defects Test Method Criteria ESD Human Body Model JESD22 A114A 2kV ESD Machine Model JESD22 A115A 200V JESD78 1.5 * Vddmax, 150mA Latch Up 5 OPTICAL SPECIFICATION The small amount of lens relative illumination effects (field darkening) is corrected by the STV0974. Table 16. Optical Specifications Parameter A packaged CMOS image sensor will display visual imperfections caused either by electrical faults or optical blemishes which can be introduced in the product at various stages of the manufacturing process. These impurities can result in pixel defects, that is a pixel whose output is not consistent with the level of incident light falling on the image sensor. The ability to identify and correct these defects is central to both the design requirements and quality certification, via test of STMicroelectronics sensor products. The STMicroelectronics STV0974 co-processor implements defect correction algorithms which screens the presence of these defects in the final images. The defect correction algorithms ensure that the VS6552 sensor in conjunction with the STV0974 co-processor will produce a high quality final image. Value Effective Focal Length 4 mm ± 0.15 mm Aperture F2.8 aperture Horizontal Field of View 45o ± 2o TV Distortion (pin,cushion & barrel) -3% to 3% MTF (Figure 6.) @ 60 cm @ 45 cycle/mm – – – 7 PACKAGE MECHANICAL DATA 7.1 SmOP1.5 Module Outline – Figure 7 – Figure 8 – Figure 9 On axis: 45 % Horizontal field: 30% Diagonal field: 30% 7.2 SmOP2 M Module Outline – Figure 10 – Figure 11 Figure 6. MTF Points on the Image Field – Figure 12 7.3 SmOP2 ME Module Outline – Figure 13 on axis horizontal field – Figure 14 – Figure 15 diagonal field 13/26 15° B C (20 : 1) ±0 .05 3° draft Linear 0 Place Decimals 0 ±1.0 1 Place Decimals 0.0 ±0.10 2 Place Decimals 0.00 ±0.07 Angular ±0.25 degrees Diameter +0.10/-0.00 Position 0.10 Surface Finish 1.6 microns This drawing is the property of STMicroelectronics and will not be copied or loaned without the written permission of STMicroelectronics. All dimensions in mm Finish 1. Mass of module 0.50 grammes 2. Volume of Module 278 mm^3 3. 2 max draft angle on all moulded components unless otherwise stated. 4. Surface finish on external moulded surfaces is RA 16 (Charmille 24). 5. Surface finish on base of ceramic is TBD. 6. All gates on moulded parts will be sub flush. 7. All mouldings to be free from visible flash or mismatch. 8. Uniformly distributed load of 20N may be applied to datum surfaces A & B. 9. These numbers denote tool No. and cavity. 10. Edge of ceramic and glue bead will not protrude past edge of lensholder. CL Ceramic 11. Dimensions enclosed thus 0.25 are inspection dimensions. 12. Minimum breaking torque between lensholder and barrel is Note 10 40 Nmm. 13. These 3 depressions contain gates or are used for cavity & 4.05 ±0.08 tool identification and ejector pin locations. Tolerances, unless otherwise stated Interpret drawing per BS308, 3RD Angle Projection Material Notes: Gate Position 0.75 R0 .10 8.26 8.66 ±0.06 4.05 ±0.08 0.00 0.15 CL Lensholder B 0.80 3.26 C Drawn Checked Appd. Mech. Appd. Elect. Appd. Prod. Appd. Q.A. Note 10 A Note 9 3° 1.50 TYP 0.40 3.90 ±0.22 Sig. Date Part No. 5.42 ±0.08 0.00 0.15 CL Ceramic 7526498 Note 9 ECN No. 1.90 ±0.15 Date Checked AX 3.55 M 5 7.2 6 8.5 5 8.2 19/01/04 0.87 Do Not Scale 0.15 ±0.03 1 of 3 Scale Profile Camera Outline Consumer & Micro Group - Imaging Division Title SmOP 1.5, Ver 2.22 Low Sheet STMicroelectronics All dimensions in mm 4.58 ±0.08 0.06 B CL Lensholder 10.56 ±0.06 Note 13 5.70 ±0.035 0.60 ±0.03 See Sheet 2 for details 1.40 Revision note 3.05 ±0.19 B 4.33 14/26 5.80 ±0.22 RevNo VS6552 Figure 7. SmOP1.5 Module Outline Date Linear 0 Place Decimals 0 ±1.0 1 Place Decimals 0.0 ±0.10 2 Place Decimals 0.00 ±0.07 Angular ±0.25 degrees Diameter +0.10/-0.00 Position 0.10 Surface Finish 1.6 microns This drawing is the property of STMicroelectronics and will not be copied or loaned without the written permission of STMicroelectronics. All dimensions in mm Interpret drawing per BS308, 3RD Angle Projection Field of View Data. Edges of circular holes in customer's equipment must not intrude into the Cone. Edges of rectangular holes must not protrude into the Pyramid. Tolerances, unless otherwise stated Cone Pyramid B2 B ECN No. Checked Finish Material Note 10 First Release as 7526498. Previous version of camera was 7487715 Barrel flange increased. Diameter on lens holder increased. Laser weld recesses moved and length was 1.60, 0.30 feature on pin 1 12/05/03 was 0.50 Tolerance added. Pad 1 dimension changed from 0.5 to 0.3mm 19/01/04 Material changed from Noryl HB1525 to Makrolon 2405. 17/02/04 Exclusion Cone corrected was 60 , Now 61 B Drawn Checked Appd. Mech. Appd. Elect. Appd. Prod. Appd. Q.A. Sub flush gate posn See Note 6 E (16 : 1) B2 Sig. 50° max. (Pyramid) Revision note D B Date Part No. Do Not Scale D Profile Camera Outline Consumer & Micro Group - Imaging Division Title SmOP 1.5, Ver 2.22 Low Sheet 2 of 3 Scale Top of image x. ma ne) o 6 3.3 B (C tum a D At Ceramic: Alumina Dark Grey Silicon E Glass Coated with IR Filter Material Makrolon: 2405 Colour Black COP: Zeonex E48R COP: Zeonex E48R Makrolon: 2405 Colour Black STMicroelectronics All dimensions in mm D-D (8 : 1) 39° max. (Pyramid) 7526498 2.01 max. at Datum B (Pyramid) E 61° max. (cone) A 2.69 max. at Datum B (Pyramid) RevNo VS6552 Figure 8. SmOP1.5 Module Outline 15/26 1.4 min. Linear 0 Place Decimals 0 ±1.0 1 Place Decimals 0.0 ±0.10 2 Place Decimals 0.00 ±0.07 Angular ±0.25 degrees Diameter +0.10/-0.00 Position 0.10 Surface Finish 1.6 microns Tolerances, unless otherwise stated This drawing is the property of STMicroelectronics and will not be copied or loaned without the written permission of STMicroelectronics. All dimensions in mm Interpret drawing per BS308, 3RD Angle Projection 2.35 ±0.03 typ 0 1.40 ±0.05 2.80 ±0.05 4.20 ±0.05 5.60 ±0.05 7.00 ±0.05 8.40 ±0.05 0.48 ±0.22 0 Finish Material 1.00 ±0.03 4.05 ±0.05 2.65 ±0.05 See Sht 2 Revision note 0 Date 1.50 ±0.05 2.90 ±0.05 5.70 ±0.05 7.10 ±0.05 Sig. B Drawn Checked Appd. Mech. Appd. Elect. Appd. Prod. Appd. Q.A. 1.20 ±0.03 typ 7526498 Pad 1 Part No. Pad material is 0.30 microns gold on 2 microns nickel Part Marking in Hatched areas. Refer to Spec TBD for details. 2.65 ±0.03 5.35 ±0.05 Underside of module showing connector and test pad layout. B 0.30 ±0.03 16/26 0.48 ±0.22 RevNo Date Checked Profile Camera Outline Consumer & Micro Group - Imaging Division Title SmOP 1.5, Ver 2.22 Low Sheet 3 of 3 Scale 19/01/04 Do Not Scale STMicroelectronics All dimensions in mm ECN No. VS6552 Figure 9. SmOP1.5 Module Outline A (20 : 1) B (20 : 1) 0.50 Position 0.10 Surface Finish 1.6 microns All Dimensions 0 Place Decimals 0 ±1.0 1 Place Decimals 0.0 ±0.10 2 Place Decimals 0.00 ±0.07 Angular ±0.5 degrees Tolerances, unless otherwise stated This drawing is the property of STMicroelectronics and will not be copied or loaned without the written permission of STMicroelectronics. All dimensions in mm Finish Material 0.52 10° Interpret drawing per BS308, 3RD Angle Projection C Note 13 Notes: 1. Mass of module: <0.5 grammes. 2. Volume of module: 370.2 mm^3. 3. 2 deg max draft angle on all moulded components unless B otherwise stated. 4. Surface finish on all external moulded surfaces is Charmille 30 MAX. 5. Surfaces shown in silver to be conductively plated. See sheet 2 for plating information. 6. All gates to be sub flush. A 7. All mouldings to be free from flash or mismatch. 8. Uniformly distributed load of 20N to be applied to datum surfaces A & B. 9. These numbers denote tool number and cavity. Text will be subflush with surface. 10.These depressions may be used to indicate lens type, tool number and cavity. 11.Dimensions enclosed thus are inspection dimensions. 12.Breaking torque between lens barrel and holder > 20 Nmm. 13.Corners of the substrate will not protrude past the rectangular footprint of the lens holder. 14.Glue bead will not protrude past edge of substrate. Note 14 0.50 R0.10 1.50° 8.22 at Datum B If no radii C (20 : 1) Gate Location A 0.60 B 2.40 4.25 8.50 ±0.06 DBS 7540020 18/06/03 Part No. Date Drawn 2 TYP 9.50 ±0.06 See Sheet 3 0.50 At Datum A +0.1 R0.10 0 4.75 These cavities may contain glue. 0.80 0.40 0.40 R0.10 1.68 ±0.10 Revision note R5 7.20 5.46 Note 9 Do Not Scale Scale Initial OUTLINE DRAWING 1 of 3 Consumer & Micro Group - Imaging Division Title SMOP2-M Sheet STMicroelectronics All dimensions in mm 8.95 Note 10 Date 2.70 ±0.10 B2 6.10 ±0.10 RevNo VS6552 Figure 10. Module Outline (SmOP 2M) 17/26 These surfaces to be plated Scallops may contain US weld marks. Weld will not protrude past cylindrical surface. "Class A" Surface (Top face of barrel) SECTION A-A SCALE 6 : 1 120° Probe points to contact inside dotted lines. 5 Cosmetics not guaranteed outside this area. A These cavities may contain glue. Position 0.10 Surface Finish 1.6 microns All Dimensions 0 Place Decimals 0 ±1.0 1 Place Decimals 0.0 ±0.10 2 Place Decimals 0.00 ±0.07 Angular ±0.5 degrees Tolerances, unless otherwise stated This drawing is the property of STMicroelectronics and will not be copied or loaned without the written permission of STMicroelectronics. All dimensions in mm Interpret drawing per BS308, 3RD Angle Projection Finish Material Plating Notes 1. 4 point probe to be used to check resistance of the metalisation. 2. Probe to must not contact the lens mount in the scalloped areas. 3. Probe to contact the cylindrical section of the lens mount between any 2 of the 3 equi-spaced points around the diameter. 4. Plating Options: a.1 micron Copper, 0.1micron MIN Stainless Steel B2 b.1 micron Copper, 0.1micron MIN Nickel Chrome c.1 micron Copper, 0.1micron MIN TBD 5. Resistance to be less than 1 ohm. 6. Contact force to be 2N. +0.3 0.94 - 0.1 See Plating Notes 2 and 3 2.40 18/26 Pyramid See Table Dim C See Table Dim F At Datum B B B Silicon Substrate: Glass/epoxy pre-preg E Glass with IR filter Material COP or PC Noryl: N110 B Part No. Date Drawn 7540020 18/06/03 DBS E 3.2 3.32 Do Not Scale SMOP2-M OUTLINE DRAWING 2 of 3 Scale F 2.4 2.49 Consumer & Micro Group - Imaging Division Title Sheet STMicroelectronics All dimensions in mm MAX Exclusion Zones Dimensions A B C D 61 50.36 39.06 4 64 53.12 41.1 4.15 Note: If an upgrate path from 5.6 micron VGA to 4 micron SVGA is required then the 4 micron SVGA data should be used. Module 5.6 micron VGA 4 micron SVGA Initial Noryl: N110 COP or PC Date See Table Dim D At Datum B SECTION B-B SCALE 5 : 1 Pyramid See Table Dim B Cone See Table Dim A See Sheet 3 Exclusion Zones. Edges of circular holes in customer's equipment must not intrude into the cone. Edges of rectangular holes must not prodrude into the pyramid. Dimensions shown are maximums. Cone Pyramid RevNoB2 Revision note See Table Dim E At Datum B A 0° 12 VS6552 Figure 11. SmOP2 Module Outline Position 0.10 Surface Finish 1.6 microns All Dimensions 0 Place Decimals 0 ±1.0 1 Place Decimals 0.0 ±0.10 2 Place Decimals 0.00 ±0.07 Angular ±0.5 degrees Tolerances, unless otherwise stated This drawing is the property of STMicroelectronics and will not be copied or loaned without the written permission of STMicroelectronics. All dimensions in mm Interpret drawing per BS308, 3RD Angle Projection B2 Note: Minimum size shown for pad. Pad spacing will be maintained. Actual pad outlines may be extended. Refer to individual product substrate drawings. Pad 1 Pad Material is 0.3 microns minimum gold on 5 microns minimum nickel. Test Test CCP DATAN VANA CCP DATAP AGND Finish Material CCP CLKP EXTCLK VDIG XSHUT DOWN Pad 14 Area for test pads, additional tracks and part marking. No conductive contact or force allowed in this area. Test Test 0.20 TYP 1.10 ±0.03 2.20 ±0.03 3.30 ±0.03 4.40 ±0.03 5.50 ±0.03 6.60 ±0.03 18/06/03 7540020 Part No. Date Drawn DBS 0.10 TYP Area For Test Pads, Additional Tracking & Part Marking Scale OUTLINE DRAWING 3 of 3 Consumer & Micro Group - Imaging Division Sheet Title SMOP2-M STMicroelectronics Do Not Scale 160604 DBS Sheet 2, Note 5, Contact resistance changed to 1 ohm. Sheet 2, Note 3 reworded. Sheet 3, Pad outline note added. B2 All dimensions in mm 110604 DBS 6.10 1 ±0.03 TYP CCP CLKN CCISCL Initial Surface finish changed to Charmille 30 MAX. Top diameter re-defined. 2.75 3.85 DBS B1 Underside of module showing connector and test pad layout. 1.50 ±0.03 TYP DGND VCAP DGND CCISDA Date 010404 Revision note See ADCS Revision A for previous history Step in chamfer added. Note 4 corrected. Notes revised to remove TBD. Torque spec changed to 20Nmm. Inspection dimension moved. B RevNo VS6552 Figure 12. SmOP2 Module Outline 19/26 A (20 : 1) B (20 : 1) C 0.52 C (20 : 1) 8.50 ±0.06 8 ±0.15 0.50 All Dimensions 0 Place Decimals 0 ±1.0 1 Place Decimals 0.0 ±0.10 2 Place Decimals 0.00 ±0.07 Angular ±0.5 degrees Position 0.10 Surface Finish 1.6 microns Tolerances, unless otherwise stated This drawing is the property of STMicroelectronics and will not be copied or loaned without the written permission of STMicroelectronics. All dimensions in mm Interpret drawing per BS308, 3RD Angle Projection Finish Material Notes: 8.22 at datum B B 1. Mass of module: <0.5 grammes. If no radii 2. Volume of module: 384.7 mm^3. 3. 2 deg max draft angle on all moulded components unless 1.50° otherwise stated. 4. Surface finish on all external moulded surfaces is Charmille 30 MAX. 5. Surfaces shown in silver to be conductively plated. A See sheet 2 for plating information. 6. All gates to be sub flush. 7. All mouldings to be free from flash or mismatch. 8. Uniformly distributed load of 20N to be applied to datum surfaces A & B. 9. These numbers denote tool number and cavity. Text will be subflush with surface. 10.These depressions may be used to indicate lens type, tool number and cavity. 11.Dimensions enclosed thus are inspection dimensions. 12.Breaking torque between lens barrel and holder > 20 Nmm. 13.All translational and rotational placement tolerances are included in this area. 14.Glue bead will not protrude past edge of Lens Holder. Note 14 0.50 R0.10 1.68 ±0.10 R0.10 Gate Location A 2.40 0.40 0.80 0.40 4.25 0.30 (7.30) B 4.75 Part No. Date Drawn 7545055 30/06/03 DBS 8.95 R5 Scale OUTLINE DRAWING 1 of 3 Consumer & Micro Group - Imaging Division Title Sheet SMOP2-ME STMicroelectronics 6 5.4 Initial 7.20 Note 9 Date Do Not Scale Note 10 All dimensions in mm 2 TYP 14 ±0.15 9.50 ±0.06 See Sheet 3 0.50 at datum A +0.10 R0.10 0 Revision note 0.50 TYP Note 13 B4 2.70 ±0.10 20/26 6.10 ±0.10 RevNo VS6552 Figure 13. SmOP2 Module Outline A Probe point to contact inside dotted lines. 5 Cosmetics not guaranteed outside this area A These cavities may contain glue. All Dimensions 0 Place Decimals 0 ±1.0 1 Place Decimals 0.0 ±0.10 2 Place Decimals 0.00 ±0.07 Angular ±0.5 degrees Position 0.10 Surface Finish 1.6 microns Tolerances, unless otherwise stated This drawing is the property of STMicroelectronics and will not be copied or loaned without the written permission of STMicroelectronics. All dimensions in mm Interpret drawing per BS308, 3RD Angle Projection Finish Material SECTION A-A SCALE 5 : 1 Plating Notes 1. 4 point probe to be used to check resistance of the metalisation. 2. Probe to must not contact the lens mount in the scalloped areas. 3. Probe to contact the cylindrical section of the lens mount between any 2 of the 3 equi-spaced points around the diameter. 4. Plating Options: B4 a.1 micron Copper, 0.1micron MIN Stainless Steel b.1 micron Copper, 0.1micron MIN Nickel Chrome c.1 micron Copper, 0.1micron MIN TBD 5. Resistance to be less than 1 ohm. 6. Contact force to be 2N. +0.3 0.94 - 0.1 These areas to be plated. Scallops may contain US weld marks. Weld will not protrude past cylindrical surface. 120° 2.40 See Plating Notes 2 and 3 Revision note Pyramid See Table Dim C B4 See Table Dim F At Datum B B B Module 5.6 micron VGA 4 micron SVGA DBS 30/06/03 7545055 Part No. Date Drawn COP or PC E Glass with IR filter Material Silicon Substrate: Glass/epoxy pre-preg Noryl N110 E 3.2 3.32 OUTLINE DRAWING B 2 of 3 Scale F 2.4 2.49 Consumer & Micro Group - Imaging Division Title SMOP2-ME Sheet STMicroelectronics Do Not Scale D 4 4.15 All dimensions in mm MAX Exclusion Zones Dimensions A B C 61 50.36 39.06 64 53.12 41.1 Note: If an upgrate path from 5.6 micron VGA to 4 micron SVGA is required then the 4 micron SVGA data should be used. Initial Noryl N110 COP or PC Date See Table Dim D At Datum B SECTION B-B SCALE 5 : 1 Pyramid See Table Dim B Cone See Table Dim A See Sheet 3 Exclusion Zones. Edges of circular holes in customer's equipment must not intrude into the cone. Edges of rectangular holes must not prodrude into the pyramid. Dimensions shown are maximums. Cone Pyramid RevNo See Table Dim E At Datum B "Class A" Surface (Top face of barrel) ° 120 VS6552 Figure 14. SmOP2 Module Outline 21/26 Test Test All Dimensions 0 Place Decimals 0 ±1.0 1 Place Decimals 0.0 ±0.10 2 Place Decimals 0.00 ±0.07 Angular ±0.5 degrees Position 0.10 Surface Finish 1.6 microns Tolerances, unless otherwise stated Test Test This drawing is the property of STMicroelectronics and will not be copied or loaned without the written permission of STMicroelectronics. All dimensions in mm Interpret drawing per BS308, 3RD Angle Projection B4 CCP DATAN VANA Area for Part Marking. Pad 1 (Test Duplicate) No Force allowed in this area Note: Minimum size shown for pad. Pad spacing will be maintained. Actual pad outlines may be extended. Refer to individual product substrate drawings. VDIG XSHUT DOWN Area for Part Marking. Pad Material is 0.3 microns minimum gold on 5 microns minimum nickel. CCP CLKP EXT CLK 1 ±0.03 TYP CCP CLKN CCIS CL 1.45 1.50 ±0.03 TYP DGND VCAP CCP DATAP AGND DGND CCIS DA Finish Material 1.10 2.20 3.30 4.40 5.50 6.60 1.45 Area For Test Pads & Additional Tracking. 0.20 TYP 2.75 Pad 14 (Test Duplicate) 3.85 Underside of module showing connector and test pad layout. 6.10 B4 B3 B2 B1 B 1 ±0.03 TYP 22/26 Revision note VANA AGND VCAP CCP DATAN CCP DATAP DGND Part No. Date XSHUT DOWN VDIG Drawn EXT CLK CCP CLKP 1.50 ±0.03 TYP CCIS CL CCP CLKN 7545055 30/06/03 DBS DBS DBS 160604 DBS DBS 110604 040504 Initial DBS Date 230104 010404 Do Not Scale 3 of 3 Scale OUTLINE DRAWING Consumer & Micro Group - Imaging Division Sheet Title SMOP2-ME STMicroelectronics All dimensions in mm Any force applied to the topside of the substrate should be balanced by a counter force directly opposite on the underside of the substrate and vice versa. Pad 1 CCIS DA DGND Pad 14 12.10 Surface finish changed to charmille 30 MAX. Top diameter defined. Sheet 2, Note 5, Contact resistance changed to 1 ohm. Sheet 2, Note 3 reworded. Sheet 3, Pad outline note added. Released into ADCS Notes 4 and 10 corrected. Top edge radius changed from +0.05 to +0.1mm. Notes updated to remove TBD. Torque now aet to 20Nmm. Inspection dimension moved. 1.10 ±0.03 2.20 ±0.03 3.30 ±0.03 4.40 ±0.03 5.50 ±0.03 6.60 ±0.03 RevNo VS6552 Figure 15. SmOP2 Module Outline VS6552 8 APPLICATION INFORMATION 8.1 Socket ST has developed a low-profile socket for the SmOP 1.5 package, which is suitable for reflow soldering and manual / automatic insertion of the camera module. The socket has been designed to withstand mobile phone grade reliability tests (temperature, shocks, vibration, salt mist). Please contact ST for details on ST P/N XS0015. See Figure 16 for recommended PCB layout and mechanical footprint of the XS0015 socket. 8.2 EMC and Shielding The VS6552 is a low noise device and is highly tolerant of high levels of radio frequency (RF) radiation. However if this device is closely mounted to a sensitive receiver it is recommended that the VS6552 is shielded to prevent reducing the sensitivity or channel masking of the receiver. Recommended maximum field strength: 1kV/m. Maximum radiated power transferred from the VS6552 into a GSM monopole antenna mounted 15 mm away from the VS6552 has peaks of inter- ference at around -90 dBm. This is dependent on system design and layout. To minimized the coupling between the GSM antenna and the sensor the following guide lines should be observed. Camera should be positioned as far away from the GSM antenna as possible. The distance between the low frequency (below 1GHz) resonant antenna elements and the camera should also be maximized. The VS6552 and its associated decoupling capacitors should NOT be connected together using the antenna reference ground. The ground connections in the sub circuit should be connected either: ■ by a dedicated ground trace network, that is connected by a single point to the main ground of the system ■ by an internal ground plane, which is entirely covered and single point connected to a protective ground. The PCLKP and PCLKN lines can be filtered to reduce the induced noise. The protective ground should be flooded around the sensor socket pads to reduce the radiation aperture in the protective ground plane. 23/26 CLEARANCE FOR VACUUM P&P 11,7 24/26 - Tolérances Générales: Ra général: Vérifié par: - 5/1 Matière: Echelle: Dessiné par: Réf: Ensemble: Pièce: Modif: 7,3 FM Le: 04/02/03 SOCKET FOR CAMERA MODULE SMOP 1.5 Mise à jour version 1,4 RECOMMENDED SOLDER 1,1 1,5 par: 10 FM le: 03/11/03 VS6552 Figure 16. SmOP1.5 Socket Mechanical Data 10,5 VS6552 9 REVISION HISTORY Table 17. Revision History Date Revision May 2004 1 First Release of Product Preview 2 Second Release - Document status changed to datasheet. to reflect the product maturity level. Changes applied in Electrical Characteristics and Package Information with the addition of two packages (SmOP2M and SmOP2ME). 21 October 2004 Description of Changes 25/26 VS6552 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners © 2004 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 26/26