1 2 3 4 6 5 D D connector connector.sch core core.sch HRESET# HRESET# HRESET# HEN# HRW HDS# HADDR[0..3] HDATA[0..7] HREQ# HACK# HEN# HRW HDS# HADDR[0..3] HDATA[0..7] HREQ# HACK# HEN# HRW HDS# HADDR[0..3] HDATA[0..7] HREQ# HACK# WATCHDOG MUTE# WATCHDOG MUTE# WATCHDOG MUTE# UART_TX_OE UART_TXD UART_RXD UART_TX_OE UART_TXD UART_RXD UART_TX_OE UART_TXD UART_RXD MCLK_OUT MCLK_IN REFCLK_IN MCLK_OUT MCLK_IN REFCLK_IN MCLK_OUT MCLK_IN REFCLK_IN FS1 SSI_CLK SSI_DIN[0..3] SSI_DOUT[0..3] FS1 SSI_CLK SSI_DIN[0..3] SSI_DOUT[0..3] FS1 SSI_CLK SSI_DIN[0..3] SSI_DOUT[0..3] GPIO[0..1] RSVD[1..5] AUX_POWER[3..0] RSVD[1..5] AUX_POWER[0..3] RSVD[1..5] AUX_POWER[0..3] GPIO[0..1] is not used elsewhere. These pulldowns are used for test points and to keep these signals at valid levels. GPIO[0..1] GPIO0 GPIO1 R1 R2 10K Ohm GND C C This linear regulator is used to assure that the +1.8v rail quickly passes the 0.5v threshold at powerup, thus minimizing power sequencing issues and making sure that the DSP does not draw excessive power as the power rails ramp up. This linear regulator is set with Vout=1.22v, so it is effectively shut off once the switching regulator comes up. Further testing and characterization of the DSP is require to determine if this linear regulator is in fact required. mech mech.sch U9 1 IN OUT BYP 2 GND ADJ 4 C45 0.01 uF 3 5 LTC1761 U1 LTC3406-1.8 4 VCC_+3.3 1 RUN B SW Vout/FB 3 L1 VCC_+1.8 2.2 uH 5 C2 C3 2 C1 10 uF, X5R, 6.3 Volts VIN GND B 10 uF, X5R, 6.3 Volts This is a simple switching regulator. It produces 1.8V at >500 mA at about 90% efficency. A simple low drop out linear regulator would be a cheaper alternative at the expense of power. A linear regulator would dissapate about 0.75 watts max, This switching regulator dissapates about 0.10 watts max. Revision F A A Title: Cirrus Logic Confidential 1 2 3 4 5 CM-2 Main Page Filename: cm2_main.sch Sheet: 1 of 7 Date: 14-Jul-2005 PN: 600-00181-01 Cirrus Logic, Inc. 305 Interlocken Parkway Broomfield, CO 80021 (303) 466-5228 (C) 2002, Cirrus Logic, Inc. 6 1 2 3 4 6 5 2x Mounting holes for PCB standoffs B20 A20 4x 0.16 Hole, 0.3 pads D 3.500 2x Mounting holes for front faceplate. B1 Component Side = J3 Bottom Side = J4 A1 0.175 D B20 B1 0.175 A20 A1 Viewed from component side up. Component Side = J1 Bottom Side = J2 0.340 This distance accounts for the thickness of the faceplate 0.3 2.86 3.500 General PCB dimensions C C 3.343 Example Configuration, Side View Note: Mechanical dimensions for the CM-2 and CM-1 Rev F are identical. There are differences with earlier versions of the CM-1, however. For reference, earlier versions of the CM-1 dimensions are shown in RED. 3.150 3.500 4-40 PEM's, x2 0.150 B 0.300 0.700 0.125 dia, 2x 0.862 0.800 0.810 0.500 1.576 8x 0.047 Alignment holes 0.680 0.700 1.000 max, 0.9 typ. 0.125 dia, 2x 0.550 B 1.000 1.925 0.175 2.800 0.431 0.421 0.150 1.343 1.333 Case cutout for faceplate mounting 0.300 0.175 0.490 0.340 0.157 2x, Hole Diameter 0.160 Faceplate material is 20 guage, 0.037" thick, Cold Rolled Steel. Plating is electroless nickel. 0.208 0.039 A A Faceplate Dimensions Connector Detail Title: Note: Drawing not to scale. Note: All dimensions are in inches. Cirrus Logic Confidential 1 2 3 4 5 Filename: mech.sch Sheet: 0 of 0 Date: 14-Jul-2005 PN: 600-00181-01 Cirrus Logic, Inc. 305 Interlocken Parkway Broomfield, CO 80021 (303) 466-5228 (C) 2002, Cirrus Logic, Inc. 6 1 2 HRESET# HACK# HRW HDS# HREQ# HEN# HDATA[0..7] D HADDR[0..3] SSI_DOUT[0..3] SSI_DIN[0..3] HRESET# HACK# HRW HDS# HREQ# HEN# AUX_POWER[0..3] 6 5 J2 Note: Pull-ups/downs on SSI_DOUT[0..4] are located on the DSP schematic page. HDATA0 HDATA1 HDATA2 HDATA3 HDATA4 HDATA5 HDATA6 HDATA7 HADDR[0..3] HADDR0 HADDR1 HADDR2 HADDR3 SSI_DOUT[0..3] SSI_DOUT0 SSI_DOUT1 SSI_DOUT2 SSI_DOUT3 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 UART_TXD GND VCC_+3.3 GND VCC_+3.3 GND VCC_+3.3 GND VCC_+3.3 GND VCC_+3.3 GND VCC_+3.3 GND VCC_+3.3 GND VCC_+3.3 RSVD1 GND VCC_+3.3 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 UART_RXD UART_TX_OE HACK# HRW HDS# HREQ# HEN# HADDR0 HADDR1 HADDR2 HDATA0 HDATA1 HDATA2 HDATA3 HDATA4 HDATA5 HDATA6 HRESET# HDATA7 HADDR3 CNM_CONN40 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 UART_TXD GND VCC_+3.3 GND VCC_+3.3 GND VCC_+3.3 GND VCC_+3.3 GND VCC_+3.3 GND VCC_+3.3 GND VCC_+3.3 GND VCC_+3.3 D RN3 SSI_DIN3 SSI_DIN2 SSI_DIN1 SSI_DIN0 RSVD5 SSI_DOUT3 RSVD3 RSVD4 2 3 4 5 7 8 9 10 1 6 GND GND 10K Ohm, 8x Array RN4 SSI_CLK MCLK_IN FS1 RSVD2 HADDR3 HDATA7 HDATA6 HDATA5 RSVD1 GND VCC_+3.3 CNM_CONN40 2 3 4 5 7 8 9 10 1 6 GND GND 10K Ohm, 8x Array SSI_DIN[0..3] SSI_DIN0 SSI_DIN1 SSI_DIN2 SSI_DIN3 J3 RSVD2 MUTE# FS1 MCLK_OUT MCLK_IN REFCLK_IN SSI_CLK SSI_DOUT0 SSI_DOUT1 SSI_DOUT2 SSI_DOUT3 SSI_DIN0 SSI_DIN1 SSI_DIN2 SSI_DIN3 RSVD3 WATCHDOG RSVD4 AUX_POWER2 AUX_POWER0 SSI_CLK MCLK_IN MCLK_OUT FS1 REFCLK_IN UART_TX_OE UART_TXD UART_RXD AUX_POWER[0..3] AUX_POWER0 AUX_POWER1 AUX_POWER2 AUX_POWER3 WATCHDOG MUTE# WATCHDOG MUTE# RSVD[1..5] 4 J1 UART_RXD UART_TX_OE HACK# HRW HDS# HREQ# HEN# HADDR0 HADDR1 HADDR2 HDATA0 HDATA1 HDATA2 HDATA3 HDATA4 HDATA5 HDATA6 HRESET# HDATA7 HADDR3 HDATA[0..7] SSI_CLK MCLK_IN MCLK_OUT FS1 REFCLK_IN UART_TX_OE UART_TXD UART_RXD C 3 RSVD[1..5] J4 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 GND VCC_+3.3 GND VCC_+3.3 GND VCC_+3.3 GND VCC_+3.3 GND VCC_+3.3 GND VCC_+3.3 GND VCC_+3.3 GND GND VCC_+5 VCC_+5 AUX_POWER3 AUX_POWER1 RSVD2 MUTE# FS1 MCLK_OUT MCLK_IN REFCLK_IN SSI_CLK SSI_DOUT0 SSI_DOUT1 SSI_DOUT2 SSI_DOUT3 SSI_DIN0 SSI_DIN1 SSI_DIN2 SSI_DIN3 RSVD3 WATCHDOG RSVD4 AUX_POWER2 AUX_POWER0 RN5 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 CNM_CONN40 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 HDATA3 HDATA2 HDATA1 HDATA0 HADDR0 HADDR1 HADDR2 HDATA4 GND VCC_+3.3 GND VCC_+3.3 GND VCC_+3.3 GND VCC_+3.3 GND VCC_+3.3 GND VCC_+3.3 GND VCC_+3.3 GND GND VCC_+5 VCC_+5 AUX_POWER3 AUX_POWER1 2 3 4 5 7 8 9 10 1 6 GND GND 10K Ohm, 8x Array C RN6 HEN# HREQ# HDS# HACK# UART_TXD UART_RXD UART_TX_OE REFCLK_IN 2 3 4 5 7 8 9 10 1 6 VCC_+3.3 VCC_+3.3 10K Ohm, 8x Array CNM_CONN40 RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 These pullups/downs are used to assure a valid logic level if a signal is tri-stated or not connected. In some situations, these may not be required. M1 MOUNTING M3 MOUNTING These two mounting holes are located near the front panel of the CM-2. VCC_+3.3 C33 0.1 uF 1 1 B VCC_+5 C34 0.1 uF C35 0.1 uF C36 0.1 uF C37 0.1 uF C38 0.1 uF B C39 0.1 uF AC Signal Return Path Caps M2 MOUNTING M4 MOUNTING Note: Similar AC signal return path caps must be included on the motherboard near the connector. 1 1 These two mounting holes are located at the "back" of the CM-2, near the main interface connectors. R39 0 Ohm R40 0 Ohm VCC_+3.3 C10 10 uF, X5R, 6.3 Volts C11 C12 10 uF, X5R, 6.3 Volts 10 uF, X5R, 6.3 Volts C13 C14 10 uF, X5R, 6.3 Volts 10 uF, X5R, 6.3 Volts Power Decoupling Caps C50 SHIELD A Place near the Ethernet connectors. A 0.01 uF, 2KV Title: 1 2 3 4 Cirrus Logic Confidential 5 Host Interface Connector Cirrus Logic, Inc. 305 Interlocken Parkway Broomfield, CO 80021 (303) 466-5228 Filename: connector.sch Sheet: 7 of 7 Date: 14-Jul-2005 PN: 600-00181-01 (C) 2002, Cirrus Logic, Inc. 6 1 2 3 HRESET# HRESET# 4 4 6 5 U10B 6 GND 5 74LVC32 D D dsp dsp.sch REFCLK_IN WATCHDOG MUTE# RSVD[1..5] UART_TX_OE UART_TXD UART_RXD FS1 SSI_CLK SSI_DIN[0..3] SSI_DOUT[0..3] MAC_IRQ0 HRESET_BUF# GPIO[0..1] MAC_CS# OE# WE# IOWAIT ADDR[0..19] DATA[0..15] MAC_IRQ0 HRESET_BUF# CLK_25 CLK_25 MAC_CS# OE# WE# IOWAIT ADDR[0..19] DATA[0..15] MAC_IRQ1 MAC_IRQ1 RSVD[1..5] VCXO_CTRL MCLK_SEL MCLK_INTERNAL CLK_25 AUX_POWER[3..0] LED_CTRL[0..2] LED_BUF[0..7] LED_CTRL[0..2] LED_BUF[0..7] macphy2 macphy2.sch REFCLK_IN WATCHDOG MUTE# RSVD[1..5] AUX_POWER[3..0] AUX_POWER[0..3] MAC_IRQ0 GPIO[0..1] REFCLK_IN WATCHDOG MUTE# CLK_25 CLK_25 MAC_CS# OE# WE# IOWAIT ADDR[0..19] DATA[0..15] FS1 SSI_CLK SSI_DIN[0..3] SSI_DOUT[0..3] VCXO_CTRL MCLK_SEL MCLK_INTERNAL C MAC_CS# OE# WE# IOWAIT ADDR[0..19] DATA[0..15] HRESET_BUF# CLK_25 FLASH_CS# AUX_POWER[0..3] MAC_IRQ1 FLASH_CS# LED_BUF[0..7] LED_BUF[0..7] VCC_+3.3 flash flash.sch HRESET_BUF# 10 11 14 LED_CTRL0 LED_CTRL1 LED_CTRL2 12 13 RCK OE# GND GND SCLR# SCK DIN C16 0.1 uF R5 LED_BUF1 30.9 Ohm, 1% U2 VCC_+3.3 C LED_BUF0 30.9 Ohm, 1% VCC_+3.3 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 CASCADE R6 15 1 2 3 4 5 6 7 LED_BUF2 30.9 Ohm, 1% C17 0.1 uF R7 LED_BUF[0..7] FLASH_CS# OE# WE# ADDR[0..19] DATA[0..15] R4 C15 0.1 uF 16 GPIO[0..1] UART_TX_OE UART_TXD UART_RXD HRESET_BUF# VCC FS1 SSI_CLK SSI_DIN[0..3] SSI_DOUT[0..3] macphy1 macphy1.sch HEN# HRW HDS# HADDR[0..3] HDATA[0..7] HREQ# HACK# LED_CTRL[0..2] UART_TX_OE UART_TXD UART_RXD HEN# HRW HDS# HADDR[0..3] HDATA[0..7] HREQ# HACK# DATA[0..15] ADDR[0..19] HEN# HRW HDS# HADDR[0..3] HDATA[0..7] HREQ# HACK# LED_BUF3 30.9 Ohm, 1% R8 LED_BUF4 30.9 Ohm, 1% C18 0.1 uF R9 9 LED_BUF5 30.9 Ohm, 1% 74LV595 8 R10 LED_BUF6 30.9 Ohm, 1% C20 0.1 uF R11 LED_BUF7 30.9 Ohm, 1% LED Filters go close to the connector. B B RN2 VCXO_CTRL MCLK_SEL VCC_+3.3 VCC_+3.3 U3 C19 0.1 uF AB2 C2 D2 WATCHDOG CTRL CTRL CTRL CTRL VCC VCC VCC GND GND GND OUT OUT 24.576 MHz VCXO A4 B4 CD4 AB3 CD3 16 A1 B1 C1 D1 MCLK_IN GND MCLK_SEL MCLK_IN VCXO_OUT GND GND VCXO_OUT VCXO_OUT GND GND VCC_+3.3 G A/B 1A 2A 3A 4A 1B 2B 3B 4B 1Y 2Y 3Y 8 C21 0.1 uF 15 1 2 5 11 14 3 6 10 13 VCC R12 3.3K Ohm GND VCXO_CTRL 4Y 24.9 Ohm, 1% 4 R44 7 R16 24.9 Ohm, 1% 9 2 3 4 5 7 8 9 10 1 6 VCC_+3.3 VCC_+3.3 10K Ohm, 8x Array MCLK_INTERNAL MCLK_OUT MCLK_OUT MUTE# R3 10K Ohm GND IOWAIT R15 3.3K Ohm GND 12 U4 74LVC157 VCC_+3.3 C22 0.1 uF A A Title: 1 2 3 4 Cirrus Logic Confidential 5 Mamba Core Cirrus Logic, Inc. 305 Interlocken Parkway Broomfield, CO 80021 (303) 466-5228 Filename: core.sch Sheet: 2 of 7 Date: 14-Jul-2005 PN: 600-00181-01 (C) 2002, Cirrus Logic, Inc. 6 1 2 3 4 6 5 D D 37 VCC_+3.3 ADDR[0..19] U5 HRESET_BUF# HRESET_BUF# 12 10 NC/A19 NC/A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D15/A-1 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 VCC 9 16 17 48 1 2 3 4 5 6 7 8 18 19 20 21 22 23 24 25 BYTE# NC/VPP NC/WP# NC/RY/BY# RESET# NC GND ADDR19 ADDR18 ADDR17 ADDR16 ADDR15 ADDR14 ADDR13 ADDR12 ADDR11 ADDR10 ADDR9 ADDR8 ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 GND ADDR[0..19] C CE# WE# OE# ADDR0 45 43 41 39 36 34 32 30 44 42 40 38 35 33 31 29 47 13 14 15 C DATA[0..15] DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 DATA[0..15] GND VCC_+3.3 VCC_+3.3 26 11 28 FLASH_CS# WE# OE# FLASH_CS# WE# OE# B 46 27 FLASH_TSOP B VCC_+3.3 C23 0.1 uF A A Title: Cirrus Logic Confidential 1 2 3 4 5 Flash Memory Filename: flash.sch Sheet: 3 of 7 Date: 14-Jul-2005 PN: 600-00181-01 Cirrus Logic, Inc. 305 Interlocken Parkway Broomfield, CO 80021 (303) 466-5228 (C) 2002, Cirrus Logic, Inc. 6 1 2 3 4 6 5 FB2 VCC_+3.3 VCC_PHY1 FBEAD, 68 Ohm @ 100 MHz C6 C46 0.01 uF C7 10 uF, X5R, 6.3 Volts 10 uF, X5R, 6.3 Volts D D 6 2 4 5 LED_CTRL[0..2] LED_CTRL[0..2] ADDR[0..19] VCC_+3.3 VCC_+3.3 DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 DATA[0..15] B DATA[0..15] 6 7 8 9 10 11 12 13 89 88 87 86 85 84 83 82 CRS COL LINK_O LINK_I SD MDC MDIO 17 9 16 33 34 1 2 3 4 5 6 7 8 TXDRXD+ 29 30 15 RXD+ C28 11 12 RXD- FB3 AUX_POWER0 FB4 AUX_POWER1 FB5 AUX_POWER2 FB6 AUX_POWER3 FBEAD, 68 Ohm @ 100 MHz H2006A R18 R17 49.9 Ohm, 1% C25 0.1 uF SHIELD SHIELD J5 RJ45 13 RXD- 49 50 51 52 53 54 S1 S2 14 0.1 uF 47 38 39 40 41 45 46 75 Ohm, 1% 75 Ohm, 1% Note: See Text Warning 43 44 78 37 24 C48 0.01 uF, 2KV AUX_POWER[0..3] SHIELD AUX_POWER[0..3] 57 56 Warning: Failure to properly install and configure the aux. Ethernet signals can result in very bad things (i.e., fire, smoke, bad hair days). If power is supplied via the RJ-45 connector then only the ferrite beads are installed (not the resistors). If power is not supplied via the RJ-45 then the resistors are installed and the beads are not. 64 65 66 67 26 25 59 CLK_25 21 22 74 75 77 31 32 15 23 42 58 63 76 81 99 C 0.1 uF DM9000 CLK_25 LED_BUF1 GPIO3 GPIO2 GPIO1 GPIO0 TX_CLK TXD0 TXD1 TXD2 TXD3 TX_EN LED_BUF0 62 61 60 LINKACT# DUP# SPEED# TEST5 TEST4 TEST3 TEST2 TEST1 AVDD AVDD AVDD SA4 SA5 SA6 SA7 SA8 SA9 SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 SD8 SD9 SD10 SD11 SD12 SD13 SD14 SD15 GND GND RX_CLK RXD0 RXD1 RXD2 RXD3 RX_DV RX_ER 18 R27 R28 ADDR[0..19] 93 94 95 96 97 98 RXI+ RXI- TXD+ 8 EEDI EEDO EECK EECS ADDR2 ADDR3 ADDR1 ADDR4 TXD+ C27 10 IOR# IOW# AEN IOWAIT IO16 CMD BGRES BGGND ADDR0 1 2 3 4 91 92 TXO+ TXO- CLK20MO WE# MAC_CS# IOWAIT R20 49.9 Ohm, 1% T1B 7 TXD- INT WAKEUP X2_25M X1_25M IOWAIT 100 79 NC NC NC WE# MAC_IRQ0 AGND AGND MAC_IRQ0 HRESET_BUF# RST PW_RST# DGND DGND DGND DGND DGND DGND DGND DGND HRESET_BUF# 14 80 DVDD DVDD DVDD DVDD DVDD DVDD DVDD U7 C VCC_PHY1 GND 0.1 uF L1 C26 VCC_PHY1 L2 VCC_PHY1 GND 5 20 36 55 72 73 90 VCC_+3.3 48 19 18 17 16 74LVC32 R19 49.9 Ohm, 1% LED_BUF3 VCC_+3.3 LED_BUF2 3 R29 R30 R31 R32 2 LED_CTRL2 LED_CTRL1 LED_CTRL0 1 MAC_CS# 71 70 69 68 OE# 27 28 35 OE# MAC_CS# L3 LED_BUF[0..7] LED_BUF[0..7] U10A L4 3 7 1 CN8 0.1 uF, 4x Array 5 3 7 CN7 0.1 uF, 4x Array 1 5 3 7 1 CN6 0.1 uF, 4x Array 8 4 6 VCC_PHY1 2 8 4 VCC_+3.3 6 2 8 VCC_+3.3 RN7 R25 2 3 4 5 7 8 9 10 6.8K Ohm, 1% Keep res close to chip pins. 1 6 B GND GND 3.3K Ohm, 8x Array 14 VCC_+3.3 U10E VCC_+3.3 A C51 0.1 uF 7 74LVC32 GND VCC A Title: 1 2 3 4 Cirrus Logic Confidential 5 Primary Ethernet Cirrus Logic, Inc. 305 Interlocken Parkway Broomfield, CO 80021 (303) 466-5228 Filename: macphy1.sch Sheet: 5 of 7 Date: 14-Jul-2005 PN: 600-00181-01 (C) 2002, Cirrus Logic, Inc. 6 1 2 3 4 6 5 FB7 VCC_+3.3 VCC_PHY2 FBEAD, 68 Ohm @ 100 MHz C8 C47 0.01 uF C9 10 uF, X5R, 6.3 Volts 10 uF, X5R, 6.3 Volts D D 6 4 5 3 7 1 CN11 0.1 uF, 4x Array 5 3 7 CN10 0.1 uF, 4x Array 1 5 3 7 1 CN9 0.1 uF, 4x Array 2 8 4 6 VCC_PHY2 2 8 4 VCC_+3.3 6 2 8 VCC_+3.3 LED_BUF[0..7] LED_BUF[0..7] DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 B DATA[0..15] DATA[0..15] 6 7 8 9 10 11 12 13 89 88 87 86 85 84 83 82 TX_CLK TXD0 TXD1 TXD2 TXD3 TX_EN CRS COL LINK_O LINK_I SD MDC MDIO RXD+ 29 30 RXD+ 24 C32 2 3 R21 FB8 AUX_POWER0 AUX_POWER1 FB9 AUX_POWER2 FB10 AUX_POWER3 FB11 FBEAD, 68 Ohm @ 100 MHz H2006A 75 Ohm, 1% 75 Ohm, 1% Note: See Text Warning 43 44 78 37 24 C49 0.01 uF, 2KV SHIELD AUX_POWER[0..3] AUX_POWER[0..3] 57 56 B Warning: Failure to properly install and configure the aux. Ethernet signals can result in very bad things (i.e., fire, smoke, bad hair days). If power is supplied via the RJ-45 connector then only the ferrite beads are installed (not the resistors). If power is not supplied via the RJ-45 then the resistors are installed and the beads are not. 64 65 66 67 26 25 59 21 22 CLK_25 74 75 77 31 32 15 23 42 58 63 76 81 99 LED_BUF5 RXD- C29 0.1 uF VCC_+3.3 SHIELD SHIELD J6 RJ45 22 RXD- R52 3.3K Ohm S1 S2 23 0.1 uF 47 38 39 40 41 45 46 49 50 51 52 53 54 1 2 3 4 5 6 7 8 DM9000 RN8 R26 2 3 4 5 7 8 9 10 6.8K Ohm, 1% CLK_25 L1 GPIO3 GPIO2 GPIO1 GPIO0 LINKACT# DUP# SPEED# TEST5 TEST4 TEST3 TEST2 TEST1 AVDD AVDD AVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD SA4 SA5 SA6 SA7 SA8 SA9 SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 SD8 SD9 SD10 SD11 SD12 SD13 SD14 SD15 19 TXD- R33 R34 VCC_+3.3 VCC_+3.3 6 33 34 GND RX_CLK RXD0 RXD1 RXD2 RXD3 RX_DV RX_ER C 20 0.1 uF R22 49.9 Ohm, 1% ADDR[0..19] RXI+ RXI- 21 5 GND 1 IOR# IOW# AEN IOWAIT IO16 CMD TXD+ EEDI EEDO EECK EECS ADDR[0..19] 93 94 95 96 97 98 TXO+ TXO- BGRES BGGND ADDR2 ADDR3 ADDR1 ADDR4 TXD+ C31 TXD- INT WAKEUP CLK20MO ADDR0 1 2 3 4 91 92 RST PW_RST# X2_25M X1_25M WE# MAC_CS# IOWAIT 100 79 NC NC NC IOWAIT MAC_IRQ1 AGND AGND WE# HRESET_BUF# DGND DGND DGND DGND DGND DGND DGND DGND MAC_IRQ1 4 L2 71 70 69 68 5 20 36 55 72 73 90 R24 49.9 Ohm, 1% U8 HRESET_BUF# T1A GND 0.1 uF C 14 80 VCC_PHY2 VCC_PHY2 LED_BUF4 C30 VCC_PHY2 GND L4 VCC_+3.3 VCC_+3.3 74LVC32 R35 R36 R37 R38 13 62 61 60 OE# LED_BUF6 11 LED_BUF7 R23 49.9 Ohm, 1% U10D L3 12 48 19 18 17 16 OE# MAC_CS# 27 28 35 MAC_CS# Keep res close to chip pins. 1 6 GND GND 3.3K Ohm, 8x Array The secondary Ethernet MAC and connector are optional. If it is not required then all parts on this page can be depopulated (or removed entirely from a new design based on this circuit). A A Title: 1 2 3 4 Cirrus Logic Confidential 5 Secondary Ethernet Cirrus Logic, Inc. 305 Interlocken Parkway Broomfield, CO 80021 (303) 466-5228 Filename: macphy2.sch Sheet: 6 of 7 Date: 14-Jul-2005 PN: 600-00181-01 (C) 2002, Cirrus Logic, Inc. 6 1 2 3 4 6 5 GND 9 D1 1N4148W U10C 8 D 16 3.3K Ohm DAO2_LRCLK VCC_+3.3 VCC_+3.3 JP1 4 6 2 8 4 6 2 8 4 6 2 8 DEBUG_CLK DEBUG_DATA CN12 0.1 uF, 4x Array CN3 0.1 uF, 4x Array CN5 0.1 uF, 4x Array 1 2 3 4 GND VCC_+3.3 GND GND GND R57 10K Ohm G A/B 1A 2A 3A 4A 1B 2B 3B 4B 1Y 2Y 3Y 4Y 8 VCC_+3.3 GND GND GND 15 1 2 5 11 14 3 6 10 13 VCC R13 R14 GND DAO1_LRCLK GND R56 VCC_+3.3 VCC_+3.3 5 3 7 CN4 0.1 uF, 4x Array 1 5 3 7 C52 0.1 uF 4 6 74LVC32 CN2 0.1 uF, 4x Array 1 5 3 7 1 CN1 0.1 uF, 4x Array 2 8 4 VCC_+1.8 6 2 8 4 VCC_+1.8 6 2 8 VCC_+1.8 3.3K Ohm 10 CON4 FS1 R53 4 FS1 D 7 9 12 U11 74LVC157 VCC_+3.3 5 3 7 1 5 3 7 1 5 3 7 1 Debug Port C53 0.1 uF 9 GND 4 3 VCC_+3.3 18 33 44 60 91 113 136 73 10 24 54 66 83 98 119 130 VCC_+1.8 C DATA[0..15] DATA[0..15] ADDR[0..19] ADDR[0..19] UART_TX_OE UART_TXD UART_RXD B CLK_25 24.9 Ohm, 1% R45 CLK_25 89 38 90 65 96 DATA15 DATA14 DATA13 DATA12 DATA11 DATA10 DATA9 DATA8 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 40 41 42 43 45 46 48 49 29 30 31 32 34 35 37 39 ADDR19 ADDR18 ADDR17 ADDR16 ADDR15 ADDR14 ADDR13 ADDR12 ADDR11 ADDR10 ADDR9 ADDR8 ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 88 87 85 84 82 75 77 55 56 74 58 59 61 62 64 67 68 70 71 72 UART_TX_OE UART_TXD UART_RXD 23 25 26 123 124 125 127 128 Y1 1 TEST DBCK DBDA VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO RESET# HR/W# HDS# HEN# HACK# HREQ# EXT_OE# EXT_WE# EXT_CS1# EXT_CS2# IOWAIT HADDR3 HADDR2 HADDR1 HADDR0 SD_D15/EXT_D7 SD_D14/EXT_D6 SD_D13/EXT_D5 SD_D12/EXT_D4 SD_D11/EXT_D3 SD_D10/EXT_D2 SD_D9/EXT_D1 SD_D8/EXT_D0 SD_D7/EXT_D15 SD_D6/EXT_D14 SD_D5/EXT_D13 SD_D4/EXT_D12 SD_D3/EXT_D11 SD_D2/EXT_D10 SD_D1/EXT_D9 SD_D0/EXT_D8 HDATA7 HDATA6 HDATA5 HDATA4 HDATA3 HDATA2 HDATA1 HDATA0 DAO_MCLK DAO1_LRCLK DAO1_SCLK DAO1_DATA3 DAO1_DATA2/HS2 DAO1_DATA1/HS1 DAO1_DATA0/HS0 EXT_A19 EXT_A18 EXT_A17 EXT_A16 EXT_A15 SD_A14/EXT_A13 SD_A13/EXT_A14 SD_A12/EXT_A11 SD_A11/EXT_A10 SD_A10/EXT_A12 SD_A9/EXT_A9 SD_A8/EXT_A8 SD_A7/EXT_A7 SD_A6/EXT_A6 SD_A5/EXT_A5 SD_A4/EXT_A4 SD_A3/EXT_A3 SD_A2/EXT_A2 SD_A1/EXT_A1 SD_A0/EXT_A0 FILT2 FILT1 2 105 106 109 110 HADDR3 HADDR2 HADDR1 HADDR0 111 112 114 115 117 118 120 121 HDATA7 HDATA6 HDATA5 HDATA4 HDATA3 HDATA2 HDATA1 HDATA0 8 MCLK_INTERNAL 22 20 15 16 17 19 DAO1_LRCLK SSI_CLK_J SSI_DOUT3 SSI_DOUT2 SSI_DOUT1 SSI_DOUT0 14 12 5 6 7 11 DAO2_LRCLK RSVD5 RSVD4 RSVD2 RSVD1 138 137 131 132 134 135 DAO1_LRCLK SSI_CLK_J SSI_DIN3 SSI_DIN2 SSI_DIN1 SSI_DIN0 141 142 RSVD3 HRW HDS# HEN# HACK# HREQ# HADDR[0..3] HADDR[0..3] HDATA[0..7] C HDATA[0..7] MCLK_INTERNAL SSI_CLK R54 SSI_CLK 24.9 Ohm, 1% SSI_DOUT[0..3] RSVD[1..5] SSI_DIN[0..3] NC NC SSI_DIN[0..3] RSVD[1..5] GPIO2 GPIO1 GPIO0 REFCLK_IN WATCHDOG_OUT MUTE# MCLK_SEL IRQ1 IRQ2 XTAL_OUT XTO XTI HRW HDS# HEN# HACK# HREQ# RSVD[1..5] DAI1_LRCLK DAI1_SCLK DAI1_DATA3 DAI1_DATA2 DAI1_DATA1 DAI1_DATA0 UART_TX_OE UART_TXD UART_RXD 107 103 104 102 140 SSI_DOUT[0..3] DAO2_LRCLK NC NC NC NC HS3 GND_A VDD_A IOWAIT OE# WE# FLASH_CS# MAC_CS# IOWAIT NC NC NC NC NC NC NC NC NC OE# WE# FLASH_CS# MAC_CS# GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND HRESET_BUF# 93 VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD U6 HRESET_BUF# VCXO_CTRL 108 100 99 97 95 92 2 143 144 GPIO1 GPIO0 REFCLK_IN WATCHDOG MUTE# MCLK_SEL MAC_IRQ1 MAC_IRQ0 1 VCXO_CTRL GPIO[0..1] REFCLK_IN WATCHDOG MUTE# MCLK_SEL MAC_IRQ1 MAC_IRQ0 B GPIO[0..1] VCXO_CTRL 126 129 13 21 27 36 47 57 63 69 76 86 94 101 116 122 133 139 28 50 51 52 53 78 79 80 81 CS181012-CQZ 25 MHz FB1 VCC_DSPA C40 22 pF R55 1 MegOhm VCC_+1.8 FBEAD, 68 Ohm @ 100 MHz C41 22 pF C4 C24 0.1 uF C5 C44 0.1 uF VCC_+3.3 10 uF, X5R, 6.3 Volts 10 uF, X5R, 6.3 Volts R42 R46 R48 R50 R41 5.90K Ohm C42 2.2 uF, X7R, 1206 3.3K Ohm C43 1000 pF, COG These pullups and pulldowns are used to set the boot mode of the DSP. The appropriate resistor is installed to select the boot mode. RSVD1 SSI_DOUT2 SSI_DOUT1 SSI_DOUT0 R43 R47 R49 R51 Default Boot Mode: HS3 - Down HS2 - Down HS1 - Up HS0 - Down 3.3K Ohm A Title: Cirrus Logic Confidential 1 2 3 4 5 A DSP Filename: dsp.sch Sheet: 4 of 7 Date: 14-Jul-2005 PN: 600-00181-01 Cirrus Logic, Inc. 305 Interlocken Parkway Broomfield, CO 80021 (303) 466-5228 (C) 2002, Cirrus Logic, Inc. 6