YZH TPA2012D2 RTJ www.ti.com SLOS438 – DECEMBER 2004 2.1 W/CH STEREO FILTER-FREE CLASS-D AUDIO POWER AMPLIFIER FEATURES APPLICATIONS • • • • • • • • • • • • • • • • • • • 2.1 W/Ch Into 4 Ω at 5 V • 1.4 W/Ch Into 8 Ω at 5 V • 720 mW/Ch Into 8 Ω at 3.6 V Only Two External Components Required Power Supply Range: 2.5 V to 5.5 V Independent Shutdown Control for Each Channel Selectable Gain of 6, 12, 18, and 24 dB Internal Pulldown Resistor On Shutdown Pins High PSRR: 77 dB at 217 Hz Fast Startup Time (3.5 ms) Low Supply Current Low Shutdown Current Short-Circuit and Thermal Protection Space Saving Packages • 2 mm X 2 mm NanoFree™ WCSP (YZH) (Future Product) • 4 mm X 4 mm Pb-Free Thin QFN (RTJ) with PowerPAD™ Wireless or Cellular Handsets and PDAs Portable DVD Player Notebook PC Portable Radio Portable Gaming Educational Toys USB Speakers DESCRIPTION The TPA2012D2 is a stereo, filter-free Class-D audio amplifier available in a WCSP or QFN package. The TPA2012D2 only requires two external components for operation. The TPA2012D2 features independent shutdown controls for each channel. The gain can be selected to 6, 12, 18, or 24 dB utilizing the G0 and G1 gain select pins. High PSRR and differential architecture provide increased immunity to noise and RF rectification. In addition to these features, a fast startup time and small package size make the TPA2012D2 an ideal choice for both cellular handsets and PDAs. The TPA2012D2 is capable of driving 1.4 W/Ch at 5 V or 720 mW/Ch at 3.6 V into 8 Ω. The TPA2012D2 is also capable of driving 4 Ω. The TPA2012D2 provides thermal and short circuit protection. APPLICATION CIRCUIT TLV320AIC26 or TLV320AIC28 HPL or SPK1 INL− PVDD INL+ AVDD To Battery CS PGND AGND HPR or SPK2 INR− TPA2012D2 OUTR+ INR+ OUTR− OUTL+ OUTL− SDR SDL G0 Shutdown Control G1 Gain Control TPA4411 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoFree, PowerPAD are trademarks of Texas Instruments. UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004, Texas Instruments Incorporated TPA2012D2 www.ti.com SLOS438 – DECEMBER 2004 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. AVAILABLE OPTIONS TA -40°C to 85°C PACKAGE PART NUMBER SYMBOL 2 mm x 2 mm WCSP (YZH) TPA2012D2YZH AKR 4 mm x 4 mm, 20 pin QFN (RTJ) TPA2012D2RTJ AKS ABSOLUTE MAXIMUM RATINGS over operating free-air temperature (unless otherwise noted) (1) UNITS VSS Supply voltage, AVDD, PVDD VI Input voltage In active mode -0.3 V to 6.0 V In shutdown mode -0.3 V to 7.0 V -0.3 V to VDD + 0.3 V Continuous total power dissipation See Dissipation Rating Table TA Operating free-air temperature range - 40°C to 85°C TJ Operating junction temperature range - 40°C to 150°C Tstg Storage temperature range (1) -65°C to 85°C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. DISSIPATION RATING TABLE (1) (2) PACKAGE TA = 25°C POWER RATING (1) Derating Factor TA = 75°C POWER RATING TA = 85°C POWER RATING RTJ 5.2 W 41.6 mW/°C 3.12 W 2.7 W YZH (2) TBD TBD TBD TBD This data was taken using 2 oz trace and copper pad that is soldered directly to a JEDEC standard 4–layer 3 in × 3 in PCB. Product preview RECOMMENDED OPERATING CONDITIONS MIN MAX 5.5 VSS Supply voltage AVDD, PVDD 2.5 VIH High-level input voltage SDL, SDR, G0, G1 1.3 VIL Low-level input voltage SDL, SDR, G0, G1 TA Operating free-air temperature 2 - 40 UNIT V V 0.35 V 85 °C TPA2012D2 www.ti.com SLOS438 – DECEMBER 2004 ELECTRICAL CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS |VOO| Output offset voltage (measured differentially) Inputs ac grounded, AV = 6 dB, VDD = 2.5 to 5.5 V PSRR Power supply rejection ratio VDD = 2.5 to 5.5 V Vicm Common-mode input voltage CMRR Common-mode rejection Inputs shorted together, ration VDD = 2.5 to 5.5 V |IIH| High-level input current VDD = 5.5 V, VI = VDD |IIL| Low-level input current VDD = 5.5 V, VI = 0 V IDD Supply current MIN TYP MAX 5 25 mV -75 -55 dB VDD-0.8 V -50 dB 50 µA 5 µA 0.5 -69 VDD = 5.5 V, No load 6 9 VDD = 3.6 V, No load 5 7.5 VDD = 2.5 V, No load 4 rDS(on) f(sw) Static drain-source on-state resistance 1.5 500 VDD = 3.6 V 570 VDD = 2.5 V 700 µA mΩ Output impedance in shutdown mode V(SDR, SDL)= 0.35 V Switching frequency VDD = 2.5 V to 5.5 V 250 300 350 G0, G1 = 0.35 V 5.5 6 6.5 G0 = VDD, G1 = 0.35 V 11.5 12 12.5 G0 = 0.35 V, G1 = VDD 17.5 18 18.5 G0, G1 = VDD 23.5 24 24.5 Closed-loop voltage gain mA 6 Shutdown mode VDD = 5.5 V UNIT 2 kΩ kHz dB OPERATING CHARACTERISTICS TA = 25°C, RL = 8 Ω, (unless otherwise noted) PARAMETER TEST CONDITIONS RL = 8 Ω MIN TYP VDD = 5.0 V, f = 1 kHz, THD = 10% 1.4 VDD = 3.6 V, f = 1 kHz, THD = 10% 0.72 PO Output power (per channel) THD+N Total harmonic distortion plus noise PO = 1 W, VDD = 5 V, AV = 6 dB f = 1 kHz 0.14% PO = 0.5 W, VDD = 5 V, AV = 6 dB f = 1 kHz 0.11% Channel crosstalk f = 1 kHz RL = 4 Ω kSVR Supply ripple rejection ratio CMRR Common mode rejection ratio Input impedance Start-up time from shutdown Vn Output voltage noise VDD = 5.0 V, f = 1 kHz, THD = 10% VDD = 5 V, AV = 6 dB f = 217 Hz -77 VDD = 3.6 V, AV = 6 dB f = 217 Hz -73 VDD = 3.6 V, VIC = 1 Vpp f = 217 Hz -69 Av = 6 dB 28.1 Av = 12 dB 17.3 Av = 18 dB 9.8 Av = 24 dB 5.2 VDD = 3.6 V, f = 20 to 20 kHz, Inputs are ac grounded, AV = 6 dB UNIT W 2.1 -85 VDD = 3.6 V MAX 3.5 No weighting 35 A weighting 27 dB dB dB kΩ ms µV 3 TPA2012D2 www.ti.com SLOS438 – DECEMBER 2004 BLOCK DIAGRAM V DD to Battery CS INR+ OUTR+ Gain Adjust Right Input PWM H− Bridge OUTR− INR− Internal Oscillator GND OUTL+ INL+ Gain Adjust Left Input PWM H− Bridge OUTL− INL− G0 G1 SDR 300 k SDL 300 k 4 Bias Circuitry Short−Circuit Protection Gain V/V dB G1 G0 0 0 2 6 0 1 4 12 1 0 8 18 1 1 16 24 TPA2012D2 www.ti.com SLOS438 – DECEMBER 2004 Terminal Functions TERMINAL NAME I/O DESCRIPTION QFN WCSP INR+ 16 D1 I Right channel positive input INR- 17 C1 I Right channel negative input INL+ 20 A1 I Left channel positive input INL- 19 B1 I Left channel negative input SDR 8 B3 I Right channel shutdown terminal (active low) SDL 7 B4 I Left channel shutdown terminal (active low) G0 15 C2 I Gain select (LSB) G1 1 B2 I Gain select (MSB) 3, 13 A2 I Power supply (Must be same voltage as AVDD) AVDD 9 D2 I Analog supply (Must be same voltage as PVDD) PGND 4, 12 C4 I Power ground AGND 18 C3 I Analog ground OUTR+ 14 D3 O Right channel positive differential output OUTR- 11 D4 O Right channel negative differential output OUTL+ 2 A3 O Left channel positive differential output OUTL- 5 A4 O Left channel negative differential output 6, 10 N/A PVDD NC No internal connection Thermal Pad Connect the thermal pad of QFN package to GND. WCSP PIN OUT TOP VIEW INL− INR− INR+ G1 G0 AVDD SDR AGND OUTR+ SDL INR+ G0 1 G1 2 OUTL+ OUTR+ 14 3 PVDD PVDD 13 4 PGND PGND 12 5 OUTL− OUTR− 11 PGND OUTR− 16 NC OUTL− 17 INR− OUTL+ 18 AVDD PVDD 19 AGND INL+ 20 INL− A4 INL+ A3 SDR D1 A2 SDL C1 A1 NC B1 RTJ PIN OUT TOP VIEW 6 7 8 9 10 15 5 TPA2012D2 www.ti.com SLOS438 – DECEMBER 2004 TYPICAL CHARACTERISTICS TOTAL HARMONIC DISTORTION vs OUTPUT POWER 2.5 V 3.6 V 0.1 5V 0.01 0.01 0.1 PO − Output Power − W 1 0.1 5V 0.1 PO − Output Power − W 1 1 3.6 V 0.1 5V 0.01 0.01 3 0.1 1 SUPPLY CURRENT vs SUPPLY VOLTAGE 6 6 RL = 4 , f = 1 kHz, AV 6 dB VDD = 5 V 5 3.6 V 0.1 5V 5.5 VDD = 3.6 V I DD − Supply Current − mA 1 4 VDD = 2.5 V 3 2 1 0 4 PO − Output Power − W SUPPLY CURRENT vs SHUTDOWN VOLTAGE I DD − Supply Current − mA THD+N − Total Harmonic Distortion + Noise − % 3.6 V TOTAL HARMONIC DISTORTION vs OUTPUT POWER RL = 4 , 33 H 5 RL = 4 4.5 RL = 8 4 No Load 3.5 RL = 8, 33 H 3 2.5 5 3.5 4 4.5 VDD − Supply Voltage − V 5 5.5 Figure 4. Figure 5. Figure 6. TOTAL HARMONIC DISTORTION vs FREQUENCY TOTAL HARMONIC DISTORTION vs FREQUENCY TOTAL HARMONIC DISTORTION vs FREQUENCY 4 1 3 PO − Output Power − W 1 0 2 2.5 2 3 4 VSD − Shutdown Voltage − V 0.1 1 VDD = 2.5 V, RL = 4 , CI = 1 F, AV = 6 dB 120 mW 350 mW 0.1 240 mW 100 1k f − Frequency − Hz Figure 7. 10 k 20 k THD+N − Total Harmonic Distortion + Noise − % 1 THD+N − Total Harmonic Distortion + Noise − % 1 2.5 V Figure 3. 0.01 0.01 6 2.5 V RL = 4 , f = 1 kHz, AV 24 dB 10 Figure 2. 2.5 V 0.01 20 10 20 Figure 1. 20 10 RL = 8 , f = 1 kHz, AV 6 dB 0.01 0.01 3 THD+N − Total Harmonic Distortion + Noise − % 20 RL = 8 , f = 1 kHz, AV 24 dB 1 TOTAL HARMONIC DISTORTION vs OUTPUT POWER 1 VDD = 2.5 V, RL = 8 , CI = 1 F, AV = 6 dB THD+N − Total Harmonic Distortion + Noise − % 10 THD+N − Total Harmonic Distortion + Noise − % THD+N − Total Harmonic Distortion + Noise − % 20 TOTAL HARMONIC DISTORTION vs OUTPUT POWER 90 mW 260 mW 0.1 180 mW 0.01 20 100 1k f − Frequency − Hz Figure 8. 10 k 20 k VDD = 3.6 V, RL = 4 , CI = 1 F, AV = 6 dB 275 mW 825 mW 0.1 550 mW 0.01 20 100 1k f − Frequency − Hz Figure 9. 10 k 20 k TPA2012D2 www.ti.com SLOS438 – DECEMBER 2004 TYPICAL CHARACTERISTICS (continued) TOTAL HARMONIC DISTORTION vs FREQUENCY TOTAL HARMONIC DISTORTION vs FREQUENCY 1 190 mW 560 mW 0.1 375 mW 0.01 20 100 1k f − Frequency − Hz 1 VDD = 5 V, RL = 4 , CI = 1 F, AV = 6 dB 0.1 1.65 W 1.1 W 0.01 20 10 k 20 k 550 mW 100 1k f − Frequency − Hz 100 1k f − Frequency − Hz CROSSTALK vs FREQUENCY CROSSTALK vs FREQUENCY POWER SUPPLY REJECTION RATIO vs FREQUENCY −20 2.5 V R to L −80 2.5 V L to R 5 V R to L Crosstalk − dB −60 −40 −60 2.5 V R to L −80 2.5 V L to R 3.6 V L to R −100 −100 −120 5 V L to R 3.6 V L to R 3.6 V R to L 5 V L to R −120 1k f − Frequency − Hz Figure 13. 10 k 20 k 20 100 PSRR − Power Supply Rejecyion Ratio − dB −30 RI = 4 −40 Crosstalk − dB 775 mW Figure 12. 0 100 1.16 W 0.1 0.01 20 10 k 20 k 380 mW Figure 11. RI = 8 3.6 V R to L VDD = 5 V, RL = 8 , CI = 1 F, AV = 6 dB Figure 10. 0 −140 20 THD+N − Total Harmonic Distortion + Noise − % VDD = 3.6 V, RL = 8 , CI = 1 F, AV = 6 dB THD+N − Total Harmonic Distortion + Noise − % THD+N − Total Harmonic Distortion + Noise − % 1 −20 TOTAL HARMONIC DISTORTION vs FREQUENCY −40 10 k 20 k 10 k 20 k Inputs AC, Grounded, CI = 1 F, RI = 4 AV = 6 dB −50 VDD = 2.7 V −60 −70 −80 VDD = 3.6 V −90 VDD = 5 V 5 V R to L 1k f − Frequency − Hz Figure 14. 10 k 20 k −100 20 100 1k f − Frequency − Hz Figure 15. 7 TPA2012D2 www.ti.com SLOS438 – DECEMBER 2004 TYPICAL CHARACTERISTICS (continued) COMMOM-MODE REJECTION RATIO vs COMMON-MODE INPUT VOLTAGE POWER SUPPLY REJECTION RATIO vs FREQUENCY −50 VDD = 2.7 V −60 −70 −80 VDD = 3.6 V −90 VDD = 5 V VDD = 2.5 V CMRR − Common-Mode Rejection Ratio − dB −40 −50 20 Inputs AC Grounded, CI = 1 F, RI = 8 , AV = 6 dB CMRR − Common-Mode Rejection Ratio − dB PSRR − Power Supply Rejecyion Ratio − dB −30 COMMON-MODE REJECTION RATIO vs FREQUENCY VDD = 3.6 V 0 −20 VDD = 5.5 V −40 −60 −80 −100 100 1k 10 k 20 k 0 f − Frequency − Hz −60 −65 VDD = 2.5 V VDD = 3.6 V −70 VDD = 5 V 20 1 2 3 4 5 VICR − Common-Mode Input Voltage Range − V 100 1k f − Frequency − Hz Figure 17. Figure 18. GSM POWER SUPPLY REJECTION vs TIME POWER SUPPLY REJECTION vs FREQUENCY POWER DISSIPATION vs OUTPUT POWER Supply Signal Ripple − V VOUT 20 mV/div CI = 1 F, Inputs AC Grounded, AV = 6 dB VDD = 3.6 V Input −20 −20 −40 −40 −60 −60 −80 −80 −100 −100 −120 −120 −140 −140 Output −160 0 500 1000 1500 2000 0.7 0 Powers are per Channel Class−AB 3.6 V, 4 0.6 PD − Power Dissipation − W C1 − High, 3.6 V C1 − Amp, 512 mV C1 − Duty, 12% f − Frequency − Hz 0.5 0.4 Class−AB 3.6 V, 8 0.3 VDD = 3.6 V, RL = 4 0.2 0.1 −160 2500 VDD = 3.6 V, RL = 8 33 H 0 0 0.2 0.4 0.6 0.8 PO − Output Power − W t − Time − 2 ms/div Figure 19. 8 10 k 20 k Figure 16. 0 VDD 200 mV/div −55 −75 −100 Power-Supply Rejection Output − V 20 VIC = 1 VPP, RL = 8 , AV = 6 dB Figure 20. Figure 21. 1 1.2 TPA2012D2 www.ti.com SLOS438 – DECEMBER 2004 TYPICAL CHARACTERISTICS (continued) POWER DISSIPATION vs OUTPUT POWER EFFICIENCY vs OUTPUT POWER EFFICIENCY vs OUTPUT POWER 100 100 1.4 Powers are per Channel 90 70 0.8 Class−AB,VDD = 5 V, 8 0.6 0.4 0.2 VDD = 5 V, RL = 8 , 33 H 70 60 50 40 0 0.5 1 1.5 2 20 10 0 0 0.5 1 1.5 PO − Output Power − W VDD = 3.6 V, RL = 8 , 33 H 30 10 2.5 VDD = 5 V, RL = 8 , 33 H 40 20 PO − Output Power − W 2 2.5 0 0.2 0.4 0.6 0.8 SUPPLY CURRENT vs OUTPUT POWER SUPPLY CURRENT vs OUTPUT POWER OUTPUT POWER vs SUPPLY VOLTAGE 1200 500 400 300 VDD = 5 V, RL = 8 , 33 H 200 800 600 VDD = 5 V, RL = 4 , 33 H 400 VDD = 3.6 V, RL = 8 , 33 H VDD = 3.6 V, RL = 4 , 33 H VDD = 2.5 V, RL = 4 , 33 H 0.8 1 1.2 1.4 1.6 0 PO − Output Power/Channel − W 1 0.8 0.6 Figure 25. 0 2.5 2.2 3 3.5 4 4.5 VDD − Supply Voltage − V 5 Figure 27. SUPLY VOLTAGE REJECTION RATIO vs DC COMMON-MODE VOLTAGE 0 2.5 RL = 4 THD+N = 10% 2 PO − Output Power − W 2 Figure 26. OUTPUT POWER vs SUPPLY VOLTAGE RL = 4 THD+N = 1% 1.5 RL = 8 THD+N = 10% 1 0.5 RL = 8 THD+N = 1% 0 2.5 RL = 8 THD+N = 1% 0.2 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 PO − Output Power/Channel − W k SVR − Supply Voltage Rejection Ratio − dB 0.6 RL = 8 THD+N = 10% 1.2 0 0.4 RL = 4 THD+N = 1% 1.4 0.4 200 VDD = 2.5 V, RL = 8 , 33 H 1.8 RL = 4 THD+N = 10% 1.6 PO − Output Power − W I DD − Supply Current − mA 1000 600 1.6 2 IDD is for Both Channels 700 0.2 1.4 Figure 24. 1.8 0 1.2 Figure 23. IDD is for Both Channels 100 1 PO − Output Power − W Figure 22. 800 I DD − Supply Current − mA Class−AB, 5 V, 8 50 0 0 0 60 Class−AB, VDD = 5 V, 4 30 VDD = 5 V, RL = 4 80 VDD = 5 V, RL = 4 33 H Efficiency − % Efficiency − % PD − Power Dissipation − W VDD = 3.6 V, RL = 4 33 H 80 Class−AB,VDD = 5 V, 4 1 VDD = 2.5 V, RL = 8 , 33 H 90 VDD = 2.5 V, RL = 4 33 H 1.2 3 3.5 4 4.5 VDD − Supply Voltage − V Figure 28. 5 5.5 −10 RL = 8 , VIN = 200 mVPP f = 217 Hz −20 VDD = 3.6 V −30 VDD = 5 V −40 VDD = 2.7 V −50 −60 −70 −80 −90 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 DC Common Mode Voltage − V Figure 29. 9 TPA2012D2 www.ti.com SLOS438 – DECEMBER 2004 APPLICATION INFORMATION To Battery 4.7 F 1 F 0.1 F PVDD* INL− 0.1 F AVDD OUTL+ 1 nF INL+ 0.1 F DAC OUTL− 1 nF 0.1 F INR− OUTR+ INR+ 1 nF 0.1 F OUTR− Shutdown Control SDL 1 nF G0 SDR G1 PGND AGND * For QFN, an additional capacitor is recomended for the second PVDD pin. Figure 30. Typical Application Circuit V DD to Battery V DD CS CI INR+ Right Differential Input CS OUTR+ Gain Adjust H− Bridge PWM INR+ OUTR− INR− Right Single−Ended Input OUTR+ Gain Adjust CI CI H− Bridge PWM OUTR− CI Internal Oscillator to Battery INR− GND Internal Oscillator GND CI INL+ Left Differential Input OUTL+ Gain Adjust PWM H− Bridge OUTL− INL− CI G0 OUTL+ Gain Adjust PWM H− Bridge OUTL− CI INL− G0 G1 G1 SDR SDR 300 k Bias Circuitry 300 k Short−Circuit Protection Bias Circuitry Short−Circuit Protection SDL SDL 300 k Figure 31. TPA2012D2 Application Schematic With Differential Input and Input Capacitors 10 INL+ Left CI Single−Ended Input 300 k Figure 32. TPA2012D2 Application Schematic With Single-Ended Input TPA2012D2 www.ti.com SLOS438 – DECEMBER 2004 Decoupling Capacitor (CS) The TPA2012D2 is a high-performance Class-D audio amplifier that requires adequate power supply decoupling to ensure the efficiency is high and total harmonic distortion (THD) is low. For higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR) ceramic capacitor, typically 1 µF, placed as close as possible to the device PVDD lead works best. Placing this decoupling capacitor close to the TPA2012D2 is important for the efficiency of the Class-D amplifier, because any resistance or inductance in the trace between the device and the capacitor can cause a loss in efficiency. For filtering lower-frequency noise signals, a 4.7 µF or greater capacitor placed near the audio power amplifier would also help, but it is not required in most applications because of the high PSRR of this device. Table 1. Gain Setting G1 G0 GAIN (V/V) GAIN (dB) INPUT IMPEDANCE (RI) (kΩ) 0 0 2 6 28.1 0 1 4 12 17.3 1 0 8 18 9.8 1 1 16 24 5.2 Input Capacitors (CI) The TPA2012D2 does not require input coupling capacitors if the design uses a differential source that is biased from 0.5 V to VDD - 0.8 V. If the input signal is not biased within the recommended common-mode input range, if high pass filtering is needed (see Figure 31), or if using a single-ended source (see Figure 32), input coupling capacitors are required. The input capacitors and input resistors form a high-pass filter with the corner frequency, fc, determined in Equation 1. 1 fc 2 RIC I (1) The value of the input capacitor is important to consider as it directly affects the bass (low frequency) performance of the circuit. Speakers in wireless phones cannot usually respond well to low frequencies, so the corner frequency can be set to block low frequencies in this application. Not using input capacitors can increase output offset. Equation 2 is used to solve for the input coupling capacitance. 1 CI 2 RI f c (2) If the corner frequency is within the audio band, the capacitors should have a tolerance of ±10% or better, because any mismatch in capacitance causes an impedance mismatch at the corner frequency and below. 11 TPA2012D2 www.ti.com SLOS438 – DECEMBER 2004 BOARD LAYOUT In making the pad size for the WCSP balls, it is recommended that the layout use nonsolder mask defined (NSMD) land. With this method, the solder mask opening is made larger than the desired land area, and the opening size is defined by the copper pad width. Figure 33 and Table 2 shows the appropriate diameters for a WCSP layout. The TPA2012D2 evaluation module (EVM) layout is shown in the next section as a layout example. Copper Trace Width Solder Pad Width Solder Mask Opening Copper Trace Thickness Solder Mask Thickness Figure 33. Land Pattern Dimensions Table 2. Land Pattern Dimensions (1) (2) (3) (4) SOLDER PAD DEFINITIONS COPPER PAD Nonsolder mask defined (NSMD) 275 µm (+0.0, -25 µm) (1) (2) (3) (4) (5) (6) (7) SOLDER MASK OPENING (5) 375 µm (+0.0, -25 µm) COPPER THICKNESS STENCIL (6) (7) OPENING STENCIL THICKNESS 1 oz max (32 µm) 275 µm x 275 µm Sq. (rounded corners) 125 µm thick Circuit traces from NSMD defined PWB lands should be 75 µm to 100 µm wide in the exposed area inside the solder mask opening. Wider trace widths reduce device stand off and impact reliability. Best reliability results are achieved when the PWB laminate glass transition temperature is above the operating the range of the intended application. Recommend solder paste is Type 3 or Type 4. For a PWB using a Ni/Au surface finish, the gold thickness should be less 0.5 mm to avoid a reduction in thermal fatigue performance. Solder mask thickness should be less than 20 µm on top of the copper circuit pattern Best solder stencil performance is achieved using laser cut stencils with electro polishing. Use of chemically etched stencils results in inferior solder paste volume control. Trace routing away from WCSP device should be balanced in X & Y directions to avoid unintentional component movement due to solder wetting forces. Component Location Place all the external components very close to the TPA2012D2. Placing the decoupling capacitor, CS, close to the TPA2012D2 is important for the efficiency of the Class-D amplifier. Any resistance or inductance in the trace between the device and the capacitor can cause a loss in efficiency. 12 TPA2012D2 www.ti.com SLOS438 – DECEMBER 2004 Trace Width Recommended trace width at the solder balls is 75 µm to 100 µm to prevent solder wicking onto wider PCB traces. For high current pins (PVDD, PGND, and audio output pins) of the TPA2012D2, use 100-µm trace widths at the solder balls and at least 500-µm PCB traces to ensure proper performance and output power for the device. For the remaining signals of the TPA2012D2, use 75-µm to 100-µm trace widths at the solder balls. The audio input pins (INR+/- and INL+/-) must run side-by-side to maximize common-mode noise cancellation. EFFICIENCY AND THERMAL INFORMATION The maximum ambient temperature depends on the heat-sinking ability of the PCB system. The derating factor for the packages are shown in the dissipation rating table. Converting this to θJA for the QFN package: 1 1 24°CW JA 0.041 Derating Factor (3) Given θJA of 24°C/W, the maximum allowable junction temperature of 150°C, and the maximum internal dissipation of 1.5W (0.75 W per channel) for 2.1 W per channel, 4-Ω load, 5-V supply, from Figure 3, the maximum ambient temperature can be calculated with the following equation. T Max T Max P 150 24 (1.5) 114°C A J JA Dmax (4) Equation 4 shows that the calculated maximum ambient temperature is 114°C at maximum power dissipation with a 5-V supply and 4-Ω a load. The TPA2012D2 is designed with thermal protection that turns the device off when the junction temperature surpasses 150°C to prevent damage to the IC. Also, using speakers more resistive than 4-Ω dramatically increases the thermal performance by reducing the output current and increasing the efficiency of the amplifier. FILTER FREE OPERATION AND FERRITE BEAD FILTERS A ferrite bead filter can often be used if the design is failing radiated emissions without an LC filter and the frequency sensitive circuit is greater than 1 MHz. This filter functions well for circuits that just have to pass FCC and CE because FCC and CE only test radiated emissions greater than 30 MHz. When choosing a ferrite bead, choose one with high impedance at high frequencies, and very low impedance at low frequencies. In addition, select a ferrite bead with adequate current rating to prevent distortion of the output signal. Use an LC output filter if there are low frequency (< 1 MHz) EMI sensitive circuits and/or there are long leads from amplifier to speaker. Figure 34 shows typical ferrite bead and LC output filters. Ferrite Chip Bead OUTP 1 nF Ferrite Chip Bead OUTN 1 nF Figure 34. Typical Ferrite Chip Bead Filter (Chip bead example: TDK: MPZ1608S221A) 13 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. 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