www.ti.com SLOS417A − OCTOBER 2003 − REVISED DECEMBER 2003 FEATURES D Maximum Battery Life and Minimum Heat APPLICATIONS D Ideal for Wireless or Cellular Handsets and − Efficiency With an 8-Ω Speaker: − 88% at 400 mW − 80% at 100 mW − 2.8-mA Quiescent Current − 0.5-µA Shutdown Current PDAs DESCRIPTION D Only Three External Components D − Optimized PWM Output Stage Eliminates LC Output Filter − Internally Generated 250-kHz Switching Frequency Eliminates Capacitor and Resistor − Improved PSRR (−75 dB) and Wide Supply Voltage (2.5 V to 5.5 V) Eliminates Need for a Voltage Regulator − Fully Differential Design Reduces RF Rectification and Eliminates Bypass Capacitor − Improved CMRR Eliminates Two Input Coupling Capacitors Wafer Chip Scale Packaging (WCSP) − NanoFreeE Lead-Free (YZF) − NanoStarE SnPb (YEF) The TPA2010D1 is a 2.5-W high efficiency filter-free class-D audio power amplifier in a 1.45 mm × 1.45 mm wafer chip scale package (WCSP) that requires only three external components. Features like 88% efficiency, −75-dB PSRR, improved RF-rectification immunity, and 8 mm2 total PCB area make the TPA2010D1 ideal for cellular handsets. A fast start-up time of 1 ms with minimal pop makes the TP2010D1 ideal for PDA applications. In cellular handsets, the earpiece, speaker phone, and melody ringer can each be driven by the TPA2010D1. The TPA2010D1 allows independent gain while summing signals from seperate sources, and has a low 36 µV noise floor, A-weighted. APPLICATION CIRCUIT 9-BALL WAFER CHIP SCALE YZF, YEF PACKAGES TPA2010D1 DIMENSIONS (TOP VIEW OF PCB) To Battery Internal Oscillator + RI − RI CS IN− _ Differential Input VDD PWM VO+ H− Bridge VO− + 1,55 mm 1,40 mm IN+ IN+ GND VO− A1 A2 A3 VDD PVDD GND B1 B2 B3 GND SHUTDOWN Bias Circuitry IN− TPA2010D1 C1 SHUTDOWN VO+ C2 C3 1,55 mm 1,40 mm Note: Pin A1 is marked with a “0” for Pb−free (YZF) and a “1” for SnPb (YEF). Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoFree and NanoStar are trademarks of Texas Instruments. !"# $"%&! '# '"! ! $#!! $# (# # #) "# '' *+ '"! $!#, '# #!#&+ !&"'# #, && $## Copyright 2003, Texas Instruments Incorporated www.ti.com SLOS417A − OCTOBER 2003 − REVISED DECEMBER 2003 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ORDERING INFORMATION TA −40°C to 85°C PACKAGE PART NUMBER SYMBOL Wafer chip scale package (YEF) TPA2010D1YEF (1) TPA2010D1YZF (1) AKO Wafer chip scale packaging − Lead free (YZF) AJZ (1) The YEF and YZF packages are only available taped and reeled. To order add the suffix “R” to the end of the part number for a reel of 3000, or add the suffix “T” to the end of the part number for a reel of 250 (e.g. TPA2010D1YEFR). ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) TPA2010D1 Supply voltage, VDD In active mode −0.3 V to 6 V In SHUTDOWN mode −0.3 V to 7 V Input voltage, VI Continuous total power dissipation −0.3 V to VDD + 0.3 V See Dissipation Rating Table Operating free-air temperature, TA −40°C to 85°C Operating junction temperature, TJ −40°C to 125°C Storage temperature, Tstg −65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds YZF 260°C YEF 235°C (1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS MIN Supply voltage, VDD MAX V VDD 0.35 V SHUTDOWN 1.3 Low-level input voltage, VIL SHUTDOWN 0 Input resistor, RI Gain ≤ 20 V/V (26 dB) 15 Common mode input voltage range, VIC VDD = 2.5 V, 5.5 V, CMRR ≤ −49 dB 0.5 −40 2 V kΩ VDD−0.8 85 PACKAGE DISSIPATION RATINGS PACKAGE DERATING FACTOR(1) TA ≤ 25°C POWER RATING TA = 70°C POWER RATING TA = 85°C POWER RATING YEF 7.8 mW/°C 780 mW 429 mW 312 mW YZF 7.8 mW/°C 780 mW 429 mW 312 mW (1) Derating factor measure with High K board. UNIT 5.5 High-level input voltage, VIH Operating free-air temperature, TA NOM 2.5 V °C www.ti.com SLOS417A − OCTOBER 2003 − REVISED DECEMBER 2003 ELECTRICAL CHARACTERISTICS TA = 25°C (unless otherwise noted) PARAMETER |VOS| Output offset voltage (measured differentially) PSRR Power supply rejection ratio CMRR Common mode rejection ratio IIH IIL High-level input current TEST CONDITIONS MIN TYP VI = 0 V, AV = 2 V/V, VDD = 2.5 V to 5.5 V VDD = 2.5 V to 5.5 V VDD = 2.5 V to 5.5 V, VIC = VDD/2 to 0.5 V VIC = VDD/2 to VDD − 0.8 V MAX UNIT 1 25 mV −75 −55 dB −68 −49 dB 100 µA 5 µA Low-level input current VDD = 5.5 V, VI = 5.8 V VDD = 5.5 V, VI = −0.3 V 3.4 Quiescent current VDD = 5.5 V, no load VDD = 3.6 V, no load 2.2 3.2 I(SD) Shutdown current VDD = 2.5 V, no load V(SHUTDOWN)= 0.35 V, VDD = 2.5 V to 5.5 V 0.5 2 Static drain-source on-state resistance VDD = 2.5 V VDD = 3.6 V VDD = 5.5 V 700 rDS(on) I(Q) Output impedance in SHUTDOWN f(sw) 4.9 2.8 mA 500 µA mΩ 400 Switching frequency V(SHUTDOWN) = 0.4 V VDD = 2.5 V to 5.5 V Gain VDD = 2.5 V to 5.5 V >1 200 kΩ 250 285 kW RI 300 kW RI Resistance from shutdown to GND 300 kHz 315 kW RI V V 300 kΩ OPERATING CHARACTERISTICS TA = 25°C, Gain = 2 V/V, RL = 8 Ω (unless otherwise noted) PARAMETER TEST CONDITIONS THD + N= 10%, f = 1 kHz, RL = 4 Ω THD + N= 1%, f = 1 kHz, RL = 4 Ω PO Output power THD + N= 10%, f = 1 kHz, RL = 8 Ω THD + N= 1%, f = 1 kHz, RL = 8 Ω THD+N Total harmonic distortion plus noise kSVR Supply ripple rejection ratio SNR Signal-to-noise ratio Vn Output voltage noise CMRR Common mode rejection ratio ZI Input impedance Start-up time from shutdown MIN TYP VDD = 5 V VDD = 3.6 V 2.5 VDD = 2.5 V VDD = 5 V 0.52 VDD = 3.6 V VDD = 2.5 V 1.06 VDD = 5 V VDD = 3.6 V 1.45 VDD = 2.5 V VDD = 5 V 0.33 VDD = 3.6 V VDD = 2.5 V 0.59 1.3 UNIT W 2.08 W 0.42 0.73 W 1.19 W 0.26 VDD = 5 V, PO = 1 W, RL = 8 Ω, f = 1 kHz VDD = 3.6 V, PO = 0.5 W, RL = 8 Ω, f = 1 kHz 0.18% VDD = 2.5 V, PO = 200 mW, RL = 8 Ω, f = 1 kHz VDD = 3.6 V, Inputs acf = 217 Hz, grounded with Ci = 2 µF V(RIPPLE) = 200 mVpp VDD = 5 V, PO = 1 W, RL = 8 Ω 0.20% 0.19% −67 dB 97 dB VDD = 3.6 V, f = 20 Hz to 20 kHz, Inputs ac-grounded with Ci = 2 µF No weighting 48 A weighting 36 VDD = 3.6 V, VIC = 1 Vpp f = 217 Hz µV VRMS −63 142 VDD = 3.6 V MAX 150 1 dB 158 kΩ ms 3 www.ti.com SLOS417A − OCTOBER 2003 − REVISED DECEMBER 2003 TERMINAL FUNCTIONS TERMINAL NAME I/O YEF, YZF DESCRIPTION IN− C1 I Negative differential input IN+ A1 I Positive differential input VDD VO+ B1 I Power supply C3 O Positive BTL output GND A2, B3 I High-current ground VO− SHUTDOWN A3 O Negative BTL output C2 I Shutdown terminal (active low logic) PVDD B2 I Power supply FUNCTIONAL BLOCK DIAGRAM *Gain = 150 kΩ RI *Gain = 2 V/V B1, B2 VDD 150 kΩ IN− C1 _ + VDD + _ Deglitch Logic Gate Drive + _ Deglitch Logic Gate Drive A3 VO− _ + _ + + _ IN+ A1 150 kΩ C2 SHUTDOWN TTL SD Input Buffer 300 kΩ Notes: * Total gain = 4 2x 150 kΩ RI Biases and References Ramp Generator Startup Protection Logic C3 VO+ OC Detect A2, B3 GND www.ti.com SLOS417A − OCTOBER 2003 − REVISED DECEMBER 2003 TYPICAL CHARACTERISTICS TABLE OF GRAPHS FIGURE PD Efficiency vs Output power 1, 2 Power dissipation vs Output power 3, 4 Supply current vs Output power 5, 6 I(Q) I(SD) Quiescent current vs Supply voltage 7 Shutdown current vs Shutdown voltage 8 PO Output power THD+N vs Supply voltage 9 vs Load resistance 10, 11 vs Output power 12, 13 vs Frequency Total harmonic distortion plus noise 14, 15, 16, 17 vs Common-mode input voltage KSVR Supply voltage rejection ratio vs Frequency GSM power supply rejection KSVR CMRR Supply voltage rejection ratio Common-mode rejection ratio 18 19, 20, 21 vs Time 22 vs Frequency 23 vs Common-mode input voltage 24 vs Frequency 25 vs Common-mode input voltage 26 TEST SET-UP FOR GRAPHS CI TPA2010D1 RI + Measurement Output − IN+ CI OUT+ Load RI + IN− OUT− VDD GND 30 kHz Low Pass Filter + Measurement Input − 1 µF VDD − Notes: (1) CI was Shorted for any Common-Mode input voltage measurement (2) A 33-µH inductor was placed in series with the load resistor to emulate a small speaker for efficiency measurements. (3) The 30-kHz low-pass filter is required even if the analyzer has an internal low-pass filter. An RC low pass filter (100 Ω, 47 nF) is used on each output for the data sheet graphs. 5 www.ti.com SLOS417A − OCTOBER 2003 − REVISED DECEMBER 2003 EFFICIENCY vs OUTPUT POWER 90 90 80 VDD = 5 V, RL = 8 Ω, 33 µH 70 60 50 40 Class AB. VDD = 5 V, RL = 8 Ω 30 20 1.4 70 Efficiency − % VDD = 2.5 V, RL = 8 Ω, 33 µH VDD = 3.6 V, RL = 4 Ω, 33 µH 60 40 Class AB. VDD = 5 V, RL = 4 Ω 20 10 0 0.4 0.6 1 0.8 0 1.2 0.2 0.4 0.6 0.8 1 Figure 1 0.6 500 Class-AB 3.6 V, 4 Ω I DD − Supply Current − mA P D − Power Dissipation − W 600 0.5 Class-AB 3.6 V, 8 Ω 0.3 VDD = 3.6 V, RL = 4 Ω 0.2 VDD = 3.6 V, RL = 8 Ω, 33 µH 0 0.2 0.4 0.6 0.8 1 400 200 VDD = 5 V, 150 100 VDD = 2.5 V 50 0.5 1 1.5 2 2.5 0 0.2 Figure 5 3 No Load VDD − Supply Voltage − V 5 5.5 1.4 OUTPUT POWER vs LOAD RESISTANCE 3 PO at 10% THD Gain = 2 V/V f = 1 kHz 2.5 1.5 VDD = 5 V 1 VDD = 3.6 V VDD = 2.5 V 0.5 VDD = 5 V 2 VDD = 3.6 V 1.5 VDD = 2.5 V 1 0.5 0 0 4.5 0.4 0.6 0.8 1.2 1 PO − Output Power − W Figure 6 SHUTDOWN CURRENT vs SHUTDOWN VOLTAGE RL = 8 Ω, 33 µH Figure 7 VDD = 3.6 V 200 PO − Output Power − W RL = 8 Ω, (resistive) 4 RL = 8 Ω, 33 µH 0 0 1.2 4.5 3.5 2.5 250 2 3 2 VDD = 5 V I (SD) − Shutdown Current − µ A I DD − Supply Current − mA 300 0 5 2 2.5 1.5 SUPPLY CURRENT vs OUTPUT POWER 300 100 1 Figure 3 VDD = 2.5 V SUPPLY CURRENT vs SUPPLY VOLTAGE 2.5 VDD = 5 V, RL = 8 Ω 0.5 PO − Output Power − W VDD = 3.6 V Figure 4 3.5 0.2 0 RL = 4 Ω, 33 µH PO − Output Power − W 4 VDD = 5 V, RL = 4 Ω, 0.4 SUPPLY CURRENT vs OUTPUT POWER 0.7 0 0.6 Figure 2 POWER DISSIPATION vs OUTPUT POWER 0.1 Class-AB 5 V, 8 Ω 0.8 PO − Output Power − W PO − Output Power − W 0.4 1 0 1.2 1.4 1.6 1.8 2 I DD − Supply Current − mA 0.2 PO − Output Power − W 0 0 Class-AB 5 V, 4 Ω 1.2 VDD = 5 V, RL = 4 Ω, 33 µH VDD = 2.5 V, RL = 4 Ω, 33 µH 50 30 10 6 POWER DISSIPATION vs OUTPUT POWER P D − Power Dissipation − W 100 80 Efficiency − % EFFICIENCY vs OUTPUT POWER 0 0.1 0.2 0.3 0.4 Shutdown Voltage − V Figure 8 0.5 4 8 12 16 20 24 RL − Load Resistance − Ω Figure 9 28 32 www.ti.com SLOS417A − OCTOBER 2003 − REVISED DECEMBER 2003 3 2.5 2.5 1.5 VDD = 3.6 V VDD = 2.5 V 0.5 2 RL = 4 Ω, 1% THD 1.5 1 0.5 4 8 12 16 20 24 RL − Load Resistance − Ω 28 32 TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER 20 10 2.5 V 5 3V 3.6 V 2 5V 1 0.5 0.2 0.1 5m 10m 20m 50m 100m 200m 500m 1 10 2 0.5 PO = 1W 0.2 0.1 0.05 0.02 0.01 0.2 0.1 0.05 0.02 0.01 50 100 200 500 1k 2k f − Frequency − Hz Figure 16 1 5V 0.5 0.2 0.1 20m 50m 100m 200m 500m 1 PO − Output Power − W 50 100 200 500 1k 2k 5k 10k 20k 5k 10k 20k 3 TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY 10 VDD = 3.6 V CI = 2 µF RL = 8 Ω Gain = 2 V/V 5 2 PO = 25 mW PO = 125 mW 1 0.5 PO = 500 mW 0.2 0.1 0.05 0.02 0.01 20 50 100 200 500 1k 2k f − Frequency − Hz 10 PO = 250 mW CI = 2 µF RL = 4 Ω Gain = 2 V/V 5 2 1 VDD = 3.6 V VDD = 3 V 0.5 0.2 VDD = 2.5 V 0.1 0.05 0.02 VDD = 4 V 20 50 100 200 VDD = 5 V 500 1k 2k f − Frequency − Hz Figure 17 5k 10k 20k Figure 15 TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY 0.01 2 0.005 20 THD+N − Total Harmonic Distortion + Noise − % PO = 15 mW PO = 200 mW 20 3.6 V Figure 14 PO = 75 mW 0.5 3V 2 f − Frequency − Hz 10 1 PO = 50 mW PO = 250 mW 1 2 TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY 2 5 2.5 V Figure 12 VDD = 5 V CI = 2 µF RL = 8 Ω Gain = 2 V/V 5 Figure 13 VDD = 2.5 V CI = 2 µF RL = 8 Ω Gain = 2 V/V 3 3.5 4 4.5 VCC − Supply Voltage − V 5 TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY PO − Output Power − W 5 RL = 8 Ω,1% THD RL = 4 Ω, f = 1 kHz, Gain = 2 V/V 10 Figure 11 THD+N − Total Harmonic Distortion + Noise − % THD+N − Total Harmonic Distortion + Noise − % Figure 10 RL = 8 Ω, f = 1 kHz, Gain = 2 V/V RL = 8 Ω,10% THD 0 2.5 0 THD+N − Total Harmonic Distortion + Noise − % RL = 4 Ω, 10% THD 20 THD+N − Total Harmonic Distortion + Noise − % 1 Gain = 2 V/V f = 1 kHz TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER 5k 10k 20k THD+N − Total Harmonic Distortion + Noise − % VDD = 5 V PO − Output Power − W PO − Output Power − W 2 PO at 1% THD Gain = 2 V/V f = 1 kHz THD+N − Total Harmonic Distortion + Noise − % OUTPUT POWER vs SUPPLY VOLTAGE OUTPUT POWER vs LOAD RESISTANCE TOTAL HARMONIC DISTORTION + NOISE vs COMMON MODE INPUT VOLTAGE 10 f = 1 kHz PO = 200 mW VDD = 2.5 V 1 VDD = 5 V VDD = 3.6 V 0.1 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VIC − Common Mode Input Voltage − V Figure 18 7 www.ti.com SLOS417A − OCTOBER 2003 − REVISED DECEMBER 2003 SUPPLY RIPPLE REJECTION RATIO vs FREQUENCY −30 Inputs ac-grounded CI = 2 µF RL = 8 Ω Gain = 2 V/V −50 VDD = 2. 5 V VDD = 3.6 V −60 −70 −80 VDD = 5 V −30 Inputs ac-grounded CI = 2 µF RL = 4 Ω Gain = 2 V/V −40 VDD = 2.5 V −50 −60 VDD = 3.6 V −70 −80 VDD = 5 V 20 100 1k 20 10 k 20 k 100 20 10 k 20 k Figure 20 Figure 21 GSM POWER SUPPLY REJECTION vs FREQUENCY 0 −50 C1 − High 3.6 V −100 VO − Output Voltage − dBV C1 − Amp 512 mV 0 VDD Shown in Figure 22 CI = 2 µF, Inputs ac-grounded Gain = 2V/V −50 −150 400 800 −40 VDD = 3.6 V VDD = 2. 5 V VDD = 5 V −60 −70 −80 1.5 2 2.5 3 3.5 4 DC Common Mode Voltage − V Figure 24 4.5 5 CMRR − Common Mode Rejection Ratio − dB −30 2000 COMMON-MODE REJECTION RATIO vs COMMON-MODE INPUT VOLTAGE COMMON-MODE REJECTION RATIO vs FREQUENCY CMRR − Common Mode Rejection Ratio − dB −20 1600 Figure 23 SUPPLY RIPPLE REJECTION RATIO vs DC COMMON MODE VOLTAGE −10 1200 f − Frequency − Hz Figure 22 0 −150 −100 0 Sopply Ripple Rejection Ratio − dB 1k Figure 19 t − Time − 2 ms/div 8 100 f − Frequency − Hz VOUT 20 mV/div 1 VDD = 3.6 V −80 −90 10 k 20 k 1k C1 − Duty 12% 0.5 −70 f − Frequency − Hz VDD 200 mV/div 0 VDD = 5 V −60 f − Frequency − Hz GSM POWER SUPPLY REJECTION vs TIME −50 −50 VDD = 2.5 V −90 −90 Inputs floating RL = 8 Ω −40 V DD − Supply Voltage − dBV −40 Sopply Ripple Rejection Ratio − dB Sopply Ripple Rejection Ratio − dB −30 SUPPLY RIPPLE REJECTION RATIO vs FREQUENCY Sopply Ripple Rejection Ratio − dB SUPPLY RIPPLE REJECTION RATIO vs FREQUENCY −50 VIC = 200 mVPP RL = 8 Ω Gain = 2 V/V −55 −60 VDD = 3.6 V −65 −70 −75 20 100 1k f − Frequency − Hz Figure 25 10 k 20 k 0 −10 −20 −30 −40 VDD = 3.6 V VDD = 2.5 V −50 −60 −70 −80 VDD = 5 V, Gain = 2 −90 −100 0 1 2 3 4 VIC − Common Mode Input Voltage − V Figure 26 5 www.ti.com SLOS417A − OCTOBER 2003 − REVISED DECEMBER 2003 APPLICATION INFORMATION FULLY DIFFERENTIAL AMPLIFIER The TPA2010D1 is a fully differential amplifier with differential inputs and outputs. The fully differential amplifier consists of a differential amplifier and a common-mode amplifier. The differential amplifier ensures that the amplifier outputs a differential voltage on the output that is equal to the differential input times the gain. The common-mode feedback ensures that the common-mode voltage at the output is biased around VDD/2 regardless of the common-mode voltage at the input. The fully differential TPA2010D1 can still be used with a single-ended input; however, the TPA2010D1 should be used with differential inputs when in a noisy environment, like a wireless handset, to ensure maximum noise rejection. Advantages of Fully DIfferential Amplifiers D Input-coupling capacitors not required: − The fully differential amplifier allows the inputs to be biased at voltage other than mid-supply. For example, if a codec has a midsupply lower than the midsupply of the TPA2010D1, the common-mode feedback circuit will adjust, and the TPA2010D1 outputs will still be biased at midsupply of the TPA2010D1. The inputs of the TPA2010D1 can be biased from 0.5V to VDD – 0.8 V. If the inputs are biased outside of that range, input-coupling capacitors are required. D Midsupply bypass capacitor, C(BYPASS), not required: − The fully differential amplifier does not require a bypass capacitor. This is because any shift in the midsupply affects both positive and negative channels equally and cancels at the differential output. D Better RF−immunity: − GSM handsets save power by turning on and shutting off the RF transmitter at a rate of 217 Hz. The transmitted signal is picked-up on input and output traces. The fully differential amplifier cancels the signal much better than the typical audio amplifier. COMPONENT SELECTION Figure 27 shows the TPA2010D1 typical schematic with differential inputs and Figure 28 shows the TPA2010D1 with differential inputs and input capacitors, and Figure 29 shows the TPA2010D1 with single-ended inputs. Differential inputs should be used whenever possible because the single-ended inputs are much more susceptible to noise. Table 1. Typical Component Values REF DES VALUE EIA SIZE MANUFACTURER PART NUMBER RI CS 150 kΩ (±0.5%) 0402 Panasonic ERJ2RHD154V 1 µF (+22%, −80%) 0402 Murata GRP155F50J105Z CI(1) 3.3 nF (±10%) 0201 Murata GRP033B10J332K (1) CI is only needed for single-ended input or if VICM is not between 0.5 V and VDD – 0.8 V. CI = 3.3 nF (with RI = 150 kΩ) gives a high-pass corner frequency of 321 Hz. 9 www.ti.com SLOS417A − OCTOBER 2003 − REVISED DECEMBER 2003 Input Resistors (RI) The input resistors (RI) set the gain of the amplifier according to equation (1). Gain + 2 x 150 kW R I ǒVVǓ (1) Resistor matching is very important in fully differential amplifiers. The balance of the output on the reference voltage depends on matched ratios of the resistors. CMRR, PSRR, and cancellation of the second harmonic distortion diminish if resistor mismatch occurs. Therefore, it is recommended to use 1% tolerance resistors or better to keep the performance optimized. Matching is more important than overall tolerance. Resistor arrays with 1% matching can be used with a tolerance greater than 1%. Place the input resistors very close to the TPA2010D1 to limit noise injection on the high-impedance nodes. For optimal performance the gain should be set to 2 V/V or lower. Lower gain allows the TPA2010D1 to operate at its best, and keeps a high voltage at the input making the inputs less susceptible to noise. Decoupling Capacitor (CS) The TPA2010D1 is a high-performance class-D audio amplifier that requires adequate power supply decoupling to ensure the efficiency is high and total harmonic distortion (THD) is low. For higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR) ceramic capacitor, typically 1 µF, placed as close as possible to the device VDD lead works best. Placing this decoupling capacitor close to the TPA2010D1 is very important for the efficiency of the class-D amplifier, because any resistance or inductance in the trace between the device and the capacitor can cause a loss in efficiency. For filtering lower-frequency noise signals, a 10 µF or greater capacitor placed near the audio power amplifier would also help, but it is not required in most applications because of the high PSRR of this device. Input Capacitors (CI) The TPA2010D1 does not require input coupling capacitors if the design uses a differential source that is biased from 0.5 V to VDD – 0.8 V (shown in Figure 27). If the input signal is not biased within the recommended common−mode input range, if needing to use the input as a high pass filter (shown in Figure 28), or if using a single-ended source (shown in Figure 29), input coupling capacitors are required. The input capacitors and input resistors form a high-pass filter with the corner frequency, fc, determined in equation (2). fc + 1 ǒ2p RICIǓ (2) The value of the input capacitor is important to consider as it directly affects the bass (low frequency) performance of the circuit. Speakers in wireless phones cannot usually respond well to low frequencies, so the corner frequency can be set to block low frequencies in this application. Equation (3) is reconfigured to solve for the input coupling capacitance. C + I 1 ǒ2p RI f cǓ (3) If the corner frequency is within the audio band, the capacitors should have a tolerance of ±10% or better, because any mismatch in capacitance causes an impedance mismatch at the corner frequency and below. For a flat low-frequency response, use large input coupling capacitors (1 µF). However, in a GSM phone the ground signal is fluctuating at 217 Hz, but the signal from the codec does not have the same 217 Hz fluctuation. The difference between the two signals is amplified, sent to the speaker, and heard as a 217 Hz hum. 10 www.ti.com SLOS417A − OCTOBER 2003 − REVISED DECEMBER 2003 To Battery Internal Oscillator RI + IN− PWM _ Differential Input RI − VDD H− Bridge CS VO+ VO− + IN+ GND Bias Circuitry SHUTDOWN TPA2010D1 Filter-Free Class D Figure 27. Typical TPA2010D1 Application Schematic With Differential Input for a Wireless Phone To Battery CI Internal Oscillator RI IN− PWM _ Differential Input CI RI VDD H− Bridge CS VO+ VO− + IN+ GND Bias Circuitry SHUTDOWN TPA2010D1 Filter-Free Class D Figure 28. TPA2010D1 Application Schematic With Differential Input and Input Capacitors To Battery CI Single-ended Input Internal Oscillator RI IN− _ RI + PWM H− Bridge CS VO+ VO− IN+ CI SHUTDOWN VDD GND Bias Circuitry TPA2010D1 Filter-Free Class D Figure 29. TPA2010D1 Application Schematic With Single-Ended Input 11 www.ti.com SLOS417A − OCTOBER 2003 − REVISED DECEMBER 2003 SUMMING INPUT SIGNALS WITH THE TPA2010D1 Most wireless phones or PDAs need to sum signals at the audio power amplifier or just have two signal sources that need separate gain. The TPA2010D1 makes it easy to sum signals or use separate signal sources with different gains. Many phones now use the same speaker for the earpiece and ringer, where the wireless phone would require a much lower gain for the phone earpiece than for the ringer. PDAs and phones that have stereo headphones require summing of the right and left channels to output the stereo signal to the mono speaker. Summing Two Differential Input Signals Two extra resistors are needed for summing differential signals (a total of 5 components). The gain for each input source can be set independently (see equations (4) and (5), and Figure 30). Gain 1 + Gain 2 + V V V V O + 2 x 150 kW R I1 I1 O + 2 x 150 kW R I2 I2 ǒVVǓ (4) ǒVVǓ (5) If summing left and right inputs with a gain of 1 V/V, use RI1 = RI2 = 300 kΩ. If summing a ring tone and a phone signal, set the ring-tone gain to Gain 2 = 2 V/V, and the phone gain to gain 1 = 0.1 V/V. The resistor values would be. . . RI1 = 3 MΩ, and = RI2 = 150 kΩ. Differential Input 1 + RI1 − RI1 R + I2 To Battery Internal Oscillator IN− _ Differential Input 2 − RI2 VDD + PWM H− Bridge CS VO+ VO− IN+ GND SHUTDOWN Bias Circuitry Filter-Free Class D Figure 30. Application Schematic With TPA2010D1 Summing Two Differential Inputs 12 www.ti.com SLOS417A − OCTOBER 2003 − REVISED DECEMBER 2003 Summing a Differential Input Signal and a Single-Ended Input Signal Figure 31 shows how to sum a differential input signal and a single-ended input signal. Ground noise can couple in through IN+ with this method. It is better to use differential inputs. The corner frequency of the single-ended input is set by CI2, shown in equation (8). To assure that each input is balanced, the single-ended input must be driven by a low-impedance source even if the input is not in use Gain 1 + Gain 2 + C I2 + V V V V O + 2 x 150 kW R I1 I1 O + 2 x 150 kW R I2 I2 ǒVVǓ (6) ǒVVǓ (7) 1 ǒ2p RI2 f c2Ǔ (8) If summing a ring tone and a phone signal, the phone signal should use a differential input signal while the ring tone might be limited to a single-ended signal. Phone gain is set at gain 1 = 0.1 V/V, and the ring-tone gain is set to gain 2 = 2 V/V, the resistor values would be… RI1 = 3 MΩ, and = RI2 = 150 kΩ. The high pass corner frequency of the single-ended input is set by CI2. If the desired corner frequency is less than 20 Hz... C C 1 ǒ2p 150kW 20HzǓ I2 u I2 u 53 pF RI1 Differential Input 1 Single-Ended Input 2 RI1 CI2 R I2 To Battery Internal Oscillator IN− _ RI2 VDD + PWM H− Bridge CS VO+ VO− IN+ CI2 SHUTDOWN Bias Circuitry GND Filter-Free Class D Figure 31. Application Schematic With TPA2010D1 Summing Differential Input and Single-Ended Input Signals 13 www.ti.com SLOS417A − OCTOBER 2003 − REVISED DECEMBER 2003 Summing Two Single-Ended Input Signals Four resistors and three capacitors are needed for summing single-ended input signals. The gain and corner frequencies (fc1 and fc2) for each input source can be set independently (see equations (9) through (12), and Figure 32). Resistor, RP, and capacitor, CP, are needed on the IN+ terminal to match the impedance on the IN− terminal. The single-ended inputs must be driven by low impedance sources even if one of the inputs is not outputting an ac signal. Gain 1 + V V Gain 2 + C C I1 + + O + 2 x 150 kW R I1 I1 V V O + 2 x 150 kW R I2 I2 ǒVVǓ (9) ǒVVǓ (10) 1 ǒ2p RI1 f c1Ǔ (11) 1 ǒ2p RI2 f c2Ǔ (12) C +C ) C P I1 I2 (13) I2 R + P R I1 ǒRI1 R ) R I2 Ǔ I2 Single-Ended Input 1 Single-Ended Input 2 (14) CI1 R I1 To Battery CI2 R I2 Internal Oscillator IN− _ RP VDD + PWM H− Bridge CS VO+ VO− IN+ CP GND SHUTDOWN Bias Circuitry Filter-Free Class D Figure 32. Application Schematic With TPA2010D1 Summing Two Single-Ended Inputs 14 www.ti.com SLOS417A − OCTOBER 2003 − REVISED DECEMBER 2003 BOARD LAYOUT In making the pad size for the WCSP balls, it is recommended that the layout use nonsolder mask defined (NSMD) land. With this method, the solder mask opening is made larger than the desired land area, and the opening size is defined by the copper pad width. Figure 33 and Table 2 show the appropriate diameters for a WCSP layout. The TPA2010D1 evaluation module (EVM) layout is shown in the next section as a layout example. Copper Trace Width Solder Pad Width Solder Mask Opening Copper Trace Thickness Solder Mask Thickness Figure 33. Land Pattern Dimensions Table 2. Land Pattern Dimensions SOLDER PAD DEFINITIONS COPPER PAD SOLDER MASK OPENING COPPER THICKNESS Nonsolder mask defined (NSMD) 275 µm (+0.0, −25 µm) 375 µm (+0.0, −25 µm) 1 oz max (32 µm) STENCIL OPENING 275 µm x 275 µm Sq. (rounded corners) STENCIL THICKNESS 125 µm thick NOTES:A. Circuit traces from NSMD defined PWB lands should be 75 µm to 100 µm wide in the exposed area inside the solder mask opening. Wider trace widths reduce device stand off and impact reliability. NOTES:B. Recommend solder paste is Type 3 or Type 4. NOTES:C. Best reilability results are achieved when the PWB laminate glass transition temperature is above the operating the range of the intended application. NOTES:D. For a PWB using a Ni/Au surface finish, the gold thickness should be less 0.5 µm to avoid a reduction in thermal fatigue performance. NOTES:E. Solder mask thickness should be less than 20 µm on top of the copper circuit pattern. NOTES:F. Best solder stencil preformance is achieved using laser cut stencils with electro polishing. Use of chemically etched stencils results in inferior solder paste volume control. NOTES:G. Trace routing away from WCSP device should be balanced in X & Y directions to avoid unintentional component movement due to solder wetting forces. 15 www.ti.com SLOS417A − OCTOBER 2003 − REVISED DECEMBER 2003 Component Location Place all the external components very close to the TPA2010D1. The input resistors need to be very close to the TPA2010D1 input pins so noise does not couple on the high impedance nodes between the input resistors and the input amplifier of the TPA2010D1. Placing the decoupling capacitor, CS, close to the TPA2010D1 is important for the efficiency of the class-D amplifier. Any resistance or inductance in the trace between the device and the capacitor can cause a loss in efficiency. Trace Width Recommended trace width at the solder balls is 75 µm to 100 µm to prevent solder wicking onto wider PCB traces. Figure 34 shows the layout of the TPA2010D1 evaluation module (EVM). For high current pins (VDD, GND VO+, and VO−) of the TPA2010D1, use 100-µm trace widths at the solder balls and at least 500-µm PCB traces to ensure proper performance and output power for the device. For input pins (IN−, IN+, and SHUTDOWN) of the TPA2010D1, use 75-µm to 100-µm trace widths at the solder balls. IN− and IN+ pins need to run side-by-side to maximize common-mode noise cancellation. Placing input resistors, RIN, as close to the TPA2010D1 as possible is recommended. 75 mm 100 mm 100 mm 100 mm 375 mm (+0, −25 mm) 275 mm (+0, −25 mm) 100 mm Circular Solder Mask Opening Paste Mask (Stencil) = Copper Pad Size 75 mm 75 mm 100 mm Figure 34. Close Up of TPA2010D1 Land Pattern From TPA2010D1 EVM 16 www.ti.com SLOS417A − OCTOBER 2003 − REVISED DECEMBER 2003 EFFICIENCY AND THERMAL INFORMATION The maximum ambient temperature depends on the heat-sinking ability of the PCB system. The derating factor for the YEF and YEZ packages are shown in the dissipation rating table. Converting this to θJA: q JA + 1 1 + + 128.2°CńW 0.0078 Derating Factor (15) Given θJA of 128.2°C/W, the maximum allowable junction temperature of 125°C, and the maximum internal dissipation of 0.4 W (2.25 W, 4-Ω load, 5-V supply, from Figure 3), the maximum ambient temperature can be calculated with the following equation. T Max + T Max * q P + 125 * 128.2 (0.4) + 73.7°C A J JA Dmax (16) Equation (16) shows that the calculated maximum ambient temperature is 73.7°C at maximum power dissipation with a 5-V supply and 4-Ω a load, see Figure 3. The TPA2010D1 is designed with thermal protection that turns the device off when the junction temperature surpasses 150°C to prevent damage to the IC. Also, using speakers more resistive than 4-Ω dramatically increases the thermal performance by reducing the output current and increasing the efficiency of the amplifier. ELIMINATING THE OUTPUT FILTER WITH THE TPA2010D1 This section focuses on why the user can eliminate the output filter with the TPA2010D1. Effect on Audio The class-D amplifier outputs a pulse-width modulated (PWM) square wave, which is the sum of the switching waveform and the amplified input audio signal. The human ear acts as a band-pass filter such that only the frequencies between approximately 20 Hz and 20 kHz are passed. The switching frequency components are much greater than 20 kHz, so the only signal heard is the amplified input audio signal. Traditional Class-D Modulation Scheme The traditional class-D modulation scheme, which is used in the TPA005Dxx family, has a differential output where each output is 180 degrees out of phase and changes from ground to the supply voltage, VDD. Therefore, the differential pre-filtered output varies between positive and negative VDD, where filtered 50% duty cycle yields 0 volts across the load. The traditional class-D modulation scheme with voltage and current waveforms is shown in Figure 35. Note that even at an average of 0 volts across the load (50% duty cycle), the current to the load is high causing a high loss and thus causing a high supply current. OUT+ OUT− +5 V Differential Voltage Across Load 0V −5 V Current Figure 35. Traditional Class-D Modulation Scheme’s Output Voltage and Current Waveforms Into an Inductive Load With no Input 17 www.ti.com SLOS417A − OCTOBER 2003 − REVISED DECEMBER 2003 TPA2010D1 Modulation Scheme The TPA2010D1 uses a modulation scheme that still has each output switching from 0 to the supply voltage. However, OUT+ and OUT− are now in phase with each other with no input. The duty cycle of OUT+ is greater than 50% and OUT− is less than 50% for positive voltages. The duty cycle of OUT+ is less than 50% and OUT− is greater than 50% for negative voltages. The voltage across the load sits at 0 volts throughout most of the switching period greatly reducing the switching current, which reduces any I2R losses in the load. OUT+ OUT− Differential Voltage Across Load Output = 0 V +5 V 0V −5 V Current OUT+ OUT− Differential +5 V Voltage Across 0V Load Output > 0 V −5 V Current Figure 36. The TPA2010D1 Output Voltage and Current Waveforms Into an Inductive Load Efficiency: Why You Must Use a Filter With the Traditional Class-D Modulation Scheme The main reason that the traditional class-D amplifier needs an output filter is that the switching waveform results in maximum current flow. This causes more loss in the load, which causes lower efficiency. The ripple current is large for the traditional modulation scheme because the ripple current is proportional to voltage multiplied by the time at that voltage. The differential voltage swing is 2 × VDD and the time at each voltage is half the period for the traditional modulation scheme. An ideal LC filter is needed to store the ripple current from each half cycle for the next half cycle, while any resistance causes power dissipation. The speaker is both resistive and reactive, whereas an LC filter is almost purely reactive. The TPA2010D1 modulation scheme has very little loss in the load without a filter because the pulses are very short and the change in voltage is VDD instead of 2 × VDD. As the output power increases, the pulses widen making the ripple current larger. Ripple current could be filtered with an LC filter for increased efficiency, but for most applications the filter is not needed. An LC filter with a cutoff frequency less than the class-D switching frequency allows the switching current to flow through the filter instead of the load. The filter has less resistance than the speaker that results in less power dissipated, which increases efficiency. 18 www.ti.com SLOS417A − OCTOBER 2003 − REVISED DECEMBER 2003 Effects of Applying a Square Wave Into a Speaker If the amplitude of a square wave is high enough and the frequency of the square wave is within the bandwidth of the speaker, a square wave could cause the voice coil to jump out of the air gap and/or scar the voice coil. A 250-kHz switching frequency, however, is not significant because the speaker cone movement is proportional to 1/f2 for frequencies beyond the audio band. Therefore, the amount of cone movement at the switching frequency is very small. However, damage could occur to the speaker if the voice coil is not designed to handle the additional power. To size the speaker for added power, the ripple current dissipated in the load needs to be calculated by subtracting the theoretical supplied power, PSUP THEORETICAL, from the actual supply power, PSUP, at maximum output power, POUT. The switching power dissipated in the speaker is the inverse of the measured efficiency, ηMEASURED, minus the theoretical efficiency, ηTHEORETICAL. P P P SPKR +P SPKR + SPKR +P SUP –P SUP THEORETICAL (at max output power) P SUP – SUP THEORETICAL (at max output power) P P OUT OUT (17) P ǒ Ǔ 1 1 * (at max output power) OUT h MEASURED h THEORETICAL hTHEORETICAL + (18) (19) R R L (at max output power) ) 2r L DS(on) (20) The maximum efficiency of the TPA2010D1 with a 3.6 V supply and an 8-Ω load is 86% from equation (20). Using equation (19) with the efficiency at maximum power (84%), we see that there is an additional 17 mW dissipated in the speaker. The added power dissipated in the speaker is not an issue as long as it is taken into account when choosing the speaker. 19 www.ti.com SLOS417A − OCTOBER 2003 − REVISED DECEMBER 2003 When to Use an Output Filter Design the TPA2010D1 without an output filter if the traces from amplifier to speaker are short. The TPA2010D1 passed FCC and CE radiated emissions with no shielding with speaker trace wires 100 mm long or less. Wireless handsets and PDAs are great applications for class-D without a filter. A ferrite bead filter can often be used if the design is failing radiated emissions without an LC filter, and the frequency sensitive circuit is greater than 1 MHz. This is good for circuits that just have to pass FCC and CE because FCC and CE only test radiated emissions greater than 30 MHz. If choosing a ferrite bead, choose one with high impedance at high frequencies, but very low impedance at low frequencies. Use an LC output filter if there are low frequency (< 1 MHz) EMI sensitive circuits and/or there are long leads from amplifier to speaker. Figure 37 and Figure 38 show typical ferrite bead and LC output filters. Ferrite Chip Bead OUTP 1 nF Ferrite Chip Bead OUTN 1 nF Figure 37. Typical Ferrite Chip Bead Filter (Chip bead example: NEC/Tokin: N2012ZPS121) 33 µH OUTP 1 µF 33 µH OUTN 1 µF Figure 38. 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