FAIRCHILD NM27LV210

NM27LV210
1,048,576-Bit (64K x 16) Low Voltage EPROM
General Description
Features
The NM27LV210 is a high performance Low Voltage Electrical
Programmable read only memory. It is manufactured using
Fairchild’s latest EPROM technology. This technology allows the
part to operate at high speeds.
■ 3.0V to 3.6V operation
■ 200 ns, 250 ns maximum access time
■ Low current operation
— 20mA ICC active current @ 5 MHz
— 50µA ICC standby current @ 5 MHz
This Low Voltage and Low Power EPROM is designed with power
sensitive hand held and portable battery products in mind. This
allows for code storage of firmware for applications like notebook
computers, palm top computers, cellular phones, and HDD.
■ Ultra low power operation
— 60 µA standby power @ 3.3V
— 50 mW active power @ 3.3V
The NM27LV210 is one member of Fairchild’s growing Low
Voltage product family.
■ Surface mount package option
— 44-Pin PLCC
Block Diagram
Vcc
Data Outputs O0 - O15
GND
Vpp
OE
PGM
CE
Output Enable
Chip Enable, and
Program Logic
Output
Buffers
Y
Decoder
A0 - A15
Address
Inputs
1,048,576-Bit
Cell Matrix
X
Decoder
DS011376-1
© 1998 Fairchild Semiconductor Corporation
1
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NM27LV210 1,048,576-Bit (64K x 16) Low Voltage EPROM
July 1998
7
8
9
10
11
12
13
14
15
16
1
O12
O11
O10
O9
O8
GND
NC
O7
O6
O5
O4
29
CE
XX/VPP
NC
VCC
XX/PGM
NC
A15
A14
O13
O14
O15
38
37
36
35
34
33
32
31
30
18 19 20 21 22 23 24 25 26 27 28
1
A13
A12
A11
A10
A9
GND
NC
A8
A7
A6
A5
44 43 42 41 40 39 38 37 36 35 34
33
A13
A12
A11
A10
A9
GND
NC
A8
A7
A6
A5
32
31
30
29
28
27
26
25
24
2
3
4
5
6
7
8
9
10
12 13 14 15 16 17 18 19 20 21 22
11
O3
O2
O1
O0
OE
NC
A0
A1
A2
A3
A4
17
39
44 43 42 41 40
6 5 4 3 2
23
O3
O2
O1
O0
OE
NC
A0
A1
A2
A3
A4
O12
O11
O10
O9
O8
GND
NC
O7
O6
O5
O4
CE
XX/VPP
NC
VCC
XX/PGM
NC
A15
A14
O13
O14
O15
PLCC Pin Configuration
DS011376-3
Top View
DS011376-7
Commercial Temperature Range
Extended Temperature Range
(0°C to +70°C) VCC = 3.3V ± 0.3
(-40°C to +85°C) VCC = 3.3V ±0.3
Parameter/Order Number
Access Time (ns)
NM27LV210 V 200
200
NM27LV210 V 250
250
Parameter/Order Number
NM27LV210 VE 250
250
• All packages conform to JEDEC standard.
• All versions are guaranteed to function in slower applications.
Pin Names
A0–A15
Access Time (ns)
• Consult the FSC representative for newly released products/
packages.
Addresses
CE
Chip Enable
OE
Output Enable
O0–O15
Outputs
PGM
Program
XX
Don’t Care (During Read)
NC
No Connect
VPP
Programming Voltage
2
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NM27LV210 1,048,576-Bit (64K x 16) Low Voltage EPROM
Connection Diagrams
Storage Temperature
All Output Voltages with
Respect to Ground (Note 11)
-65°C to +150°C
All Input Voltages except A9 with
Respect to Ground (Note 12)
VPP and A9 with Respect to Ground
VCC Supply Voltage with
Respect to Ground
Operating Range
-0.6V to +7V
Range
-0.6V to +14V
Commercial
Extended
-0.6V to +7V
ESD Protection
VCC + 1.0V to GND - 0.6V
Temperature
VCC
Tolerance
0°C to +70°C
3.3
±0.3
-40°C to +85°C
3.3
±0.3
Min
Max
Units
>2000V
DC Read Characteristics Over Operating Range with VPP = VCC
Symbol
Parameter
Test Conditions
VIL
Input Low Level
-0.3
0.7
V
VIH
Input High Level
2.0
VCC + 0.3
V
0.4
V
VOL1
Output Low Voltage (TTL)
VOH1
Output High Voltage (TTL)
VOL2
Output Low Voltage (CMOS)
VOH2
Output High Voltage (CMOS)
ISB1
VCC Standby Current (TTL)
CE = VIH
ISB2
VCC Standby Current (CMOS)
CE = VCC ±0.3V
ICC
VCC Active Current
CE = OE = VIL,
I/O = 0 µA
IPP
VPP Supply Current
VPP = VCC
ILI
Input Load Current
VIN = 3.3 or GND
ILO
Output Leakage Current
VOUT = 3.3V or GND
2.4
V
0.2
VCC - 0.3
V
V
150
µA
50
µA
20
mA
10
µA
-1
1
µA
-1
10
µA
f = 5 MHz
AC Read Characteristics Over Operating Range with VPP = VCC
Symbol
Parameter
200
Min
250
Max
Min
Units
Max
tACC
Address to Output Delay
200
250
tCE
CE to Output Delay
200
250
tOE
OE to Output Delay
70
tDF
(Note 3)
Output Disable to Output Float
0
tOH
(Note 3)
Output Hold from Addresses,
CE or OE , Whichever
Occurred First
0
75
50
0
60
ns
0
Capacitance (Note 3) TA = +25˚C, f = 1 MHz
Symbol
CIN
COUT
Parameter
Conditions
Typ
Max
Units
Input Capacitance
VIN = 0V
12
20
pF
Output Capacitance
VOUT = 0V
13
20
pF
3
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NM27LV210 1,048,576-Bit (64K x 16) Low Voltage EPROM
Absolute Maximum Ratings (Note 2)
Output Load
1 TTL Gate and CL = 100 pF (Note 9)
≤5 ns
Input Rise and Fall Times
Input Pulse Levels
0.45V to 2.4V
Timing Measurement Reference Level
Inputs
Outputs
0.8V and 2V
0.8V and 2V
AC Waveforms (Note 7) (Note 8) (Note 10)
ADDRESS
2.0V
0.8V
CE
2.0V
0.8V
Address Valid
,,
,
t CF
(Note 4, 5)
t CE
OE
2.0V
0.8V
t DF
t OE
(Note 4, 5)
(Note 3)
OUTPUT
Hi-Z
2.0V
0.8V
Hi-Z
Valid Output
t ACC
t DH
(Note 3)
DS011376-4
Note 2: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Note 3: This parameter is only sampled and is not 100% tested.
Note 4: OE may be delayed up to tACC - tOE after the falling edge of CE without impacting tACC.
Note 5: The tDF and tCF compare level is determined as follows:
High to TRI-STATE™, the measured VOH1 (DC) - 0.10V;
Low to TRI-STATE, the measured VOL1 (DC) + 0.10V.
Note 6: TRI-STATE may be attained using OE or CE.
Note 7: The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1 µF ceramic capacitor be used on every device
between VCC and GND.
Note 8: The outputs must be restricted to VCC + 1.0V to avoid latch-up and device damage.
Note 9: 1 TTL Gate: IOL = 1.6 mA, IOH = -400 µA.
CL: 100 pF includes fixture capacitance.
Note 10: VPP may be connected to VCC except during programming.
Note 11: Inputs and outputs can undershoot to -2.0V for 20 ns Max.
Programming Characteristics (Note 12) (Note 13) (Note 14) (Note 15)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
tAS
Address Setup Time
1
µs
tOES
OE Setup Time
1
µs
tCES
CE Setup Time
1
µs
tDS
Data Setup Time
1
µs
tVPS
VPP Setup Time
1
µs
tVCS
VCC Setup Time
1
µs
tAH
Address Hold Time
0
µs
tDH
Data Hold Time
1
µs
tDF
Output Enable to Output Float Delay
OE = VIH
CE = VIL
4
0
60
ns
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NM27LV210 1,048,576-Bit (64K x 16) Low Voltage EPROM
AC Test Conditions
Symbol
Parameter
Conditions
Min
Typ
Max
45
50
Units
tPW
Program Pulse Width
105
µs
tOE
Data Valid from OE
CE = VIL
100
ns
IPP
VPP Supply Current during
Programming Pulse
CE = VIL
PGM = VIL
40
mA
ICC
VCC Supply Current
50
mA
TA
Temperature Ambient
20
25
30
°C
VCC
Power Supply Voltage
6.25
6.5
6.75
V
VPP
Programming Supply Voltage
12.5
12.75
13.0
V
tFR
Input Rise, Fall Time
VIL
Input Low Voltage
VIH
Input High Voltage
2.4
tIN
Input Timing Reference Voltage
0.8
2.0
V
Output Timing Reference Voltage
0.8
2.0
V
tOUT
5
ns
0.0
0.45
4.0
V
V
Programming Waveforms (Note 14)
Program
Addresses
2.0V
0.8V
Program Verify
Address N
t AS
2.0V
Data
t DS
6.25V
VCC
VPP
CE
12.75V
Hi-Z
Data In Stable
ADD N
0.8V
Data Out Valid
ADD N
t DF
t DH
t VCS
t VPS
0.8V
t CES
PGM
2.0V
0.8V
t OES
t PW
OE
t OE
2.0V
0.8V
DS011376-5
Note 12: Fairchild’s standard product warranty applies only to devices programmed to specifications described herein.
Note 13: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. The EPROM must not be inserted into or removed from a board with
voltage applied to VPP or VCC.
Note 14: The maximum absolute allowable voltage which may be applied to the VPP pin during programming is 14V. Care must be taken when switching the VPP supply to
prevent any overshoot from exceeding this 14V maximum specification. At least a 0.1 µF capacitor is required across VPP, VCC to GND to suppress spurious voltage transients
which may damage the device.
Note 15: During power up the PGM pin must be brought high (≥VIH) either coincident with or before power is applied to VPP.
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NM27LV210 1,048,576-Bit (64K x 16) Low Voltage EPROM
Programming Characteristics (Note 12) (Note 13) (Note 14) (Note 15) (Continued)
NM27LV210 1,048,576-Bit (64K x 16) Low Voltage EPROM
Turbo LV Programming Algorithm Flow Chart
VCC = 6.5V VPP = 12.75V
n=0
ADDRESS = FIRST LOCATION
PROGRAM ONE 50µs PULSE
INCREMENT n
NO
DEVICE
FAILED
YES
n = 10?
FAIL
VERIFY
BYTE
PASS
LAST
ADDRESS
?
NO
INCREMENT
ADDRESS
n=0
YES
ADDRESS = FIRST LOCATION
VERIFY
BYTE
FAIL
PASS
INCREMENT
ADDRESS
NO
PROGRAM ONE
50 µs
PULSE
LAST
ADDRESS
?
YES
CHECK ALL BYTES
1ST: VCC = VPP = 5.0V
2ND: VCC = VPP = 3.0V
DS011376-6
Note:
The standard National Semiconductor algorithm may also be used but it will have longer programming time.
FIGURE 1.
6
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Programming
DEVICE OPERATION
CAUTION: Exceeding 14V on the VPP or A9 pin will damage the
EPROM.
The six modes of operation of the EPROM are listed in . It should
be noted that all inputs for the six modes are at TTL levels. The
power supplies required are VCC and VPP. The VPP power supply
must be at 12.75V during the three programming modes, and must
be at 3.3V in the other three modes. The VCC power supply must
be at 6.5V during the three programming modes, and at 3.3V in the
other three modes.
Initially, and after each erasure, all bits of the EPROM are in the
“1’s” state. Data is introduced by selectively programming “0’s”
into the desired bit locations. Although only “0’s” will be programmed, both “1’s” and “0’s” can be presented in the data word.
The only way to change a “0” to a “1” is by ultraviolet light erasure.
The EPROM is in the programming mode when the VPP power
supply is at 12.75V and OE is at VIH. It is required that at least a
0.1 µF capacitor be placed across VPP, VCC to ground to suppress
spurious voltage transients which may damage the device. The
data to be programmed is applied 16 bits in parallel to the data
output pins. The levels required for the address and data inputs
are TTL.
Read Mode
The EPROM has two control functions, both of which must be
logically active in order to obtain data at the outputs. Chip Enable
(CE) is the power control and should be used for device selection.
Output Enable (OE) is the output control and should be used to
gate data to the output pins, independent of device selection.
Assuming that the addresses are stable, address access time
(tACC) is equal to the delay from CE to output (tCE). Data is available
at the outputs tOE after the falling edge of OE, assuming that CE
has been low and addresses have been stable for at least tACC –
tOE.
When the address and data are stable, an active low, TTL program
pulse is applied to the PGM input. A program pulse must be
applied at each address location to be programmed. The EPROM
is programmed with the Turbo Programming Algorithm shown in
Figure 1. Each Address is programmed with a series of 50 µs
pulses until it verifies good, up to a maximum of 10 pulses. Most
memory cells will program with a single 50 µs pulse. (The standard
National Semiconductor Algorithm may also be used but it will
have longer programming time.)
Standby Mode
The EPROM has a standby mode which reduces the active power
dissipation by over 99%, from 66 mW to 66 µW. The EPROM is
placed in the standby mode by applying a CMOS high signal to the
CE input. When in standby mode, the outputs are in a high
impedance state, independent of the OE input.
The EPROM must not be programmed with a DC signal applied to
the PGM input.
Programming multiple EPROM in parallel with the same data can
be easily accomplished due to the simplicity of the programming
requirements. Like inputs of the parallel EPROM may be connected together when they are programmed with the same data.
A low level TTL pulse applied to the PGM input programs the
paralleled EPROM.
Output Disable
The EPROM is placed in output disable by applying a TTL high
signal to the OE input. When in output disable all circuitry is
enabled, except the outputs are in a high impedance state (TRISTATE).
Output OR-Tying
Because the EPROM is usually used in larger memory arrays,
Fairchild has provided a 2-line control function that accommodates this use of multiple memory connections. The 2-line control
function allows for:
1. the lowest possible memory power dissipation, and
2. complete assurance that output bus contention will not
occur.
To most efficiently use these two control lines, it is recommended
that CE be decoded and used as the primary device selecting
function, while OE be made a common connection to all devices
in the array and connected to the READ line from the system
control bus. This assures that all deselected memory devices are
in their low power standby modes and that the output pins are
active only when data is desired from a particular memory device.
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NM27LV210 1,048,576-Bit (64K x 16) Low Voltage EPROM
Functional Description
MODE SELECTION
The modes of operation of the NM27LV210 are listed in Table 1. A single power supply is required in the read mode. All inputs are TTL
levels except for VPP and A9 for device signature.
TABLE 1. Modes Selection
Pins
CE
OE
PGM
VPP
VCC
Outputs
VIL
VIL
X
(Note 16)
X
3.3V
DOUT
X
VIH
X
X
3.3V
High Z
Standby
VIH
X
X
X
3.3V
High Z
Programming
VIL
VIH
VIL
12.75V
6.25V
DIN
Program Verify
VIL
VIL
VIH
12.75V
6.25V
DOUT
Program Inhibit
VIH
X
X
12.75V
6.25V
High Z
Mode
Read
Output Disable
Note 16: X can be VIL or VIH.
The code is accessed by applying 12V ±0.5V to address pin A9 .
Addresses A1 –A8 ,A10 –A15 , and all control pins are held at VIL.
Address pin A0 is held at VIL for the manufacturer’s code, and held
at VIH for the device code. The code is read on the lower eight data
pins, O0 –07 . Proper code access is only guaranteed at 25°C ±
5°C.
Program Inhibit
Programming multiple EPROM’s in parallel with different data is
also easily accomplished. Except for CE all like inputs (including
OE and PGM) of the parallel EPROM may be common. A TTL low
level program pulse applied to an EPROM’s PGM input with CE at
VIL and VPP at 12.75V will program that EPROM. A TTL high level
CE input inhibits the other EPROM’s from being programmed.
SYSTEM CONSIDERATION
The power switching characteristics of EPROMs require careful
decoupling of the devices. The supply current, ICC, has three
segments that are of interest to the system designer: the standby
current level, the active current level, and the transient current
peaks that are produced by voltage transitions on input pins. The
magnitude of these transient current peaks is dependent on the
output capacitance loading of the device. The associated VCC
transient voltage peaks can be suppressed by properly selected
decoupling capacitors. It is recommended that at least a 0.1 µF
ceramic capacitor be used on every device between VCC and
GND. This should be a high frequency capacitor of low inherent
inductance. In addition, at least a 4.7 µF bulk electrolytic capacitor
should be used between VCC and GND for each eight devices. The
bulk capacitor should be located near where the power supply is
connected to the array. The purpose of the bulk capacitor is to
overcome the voltage drop caused by the inductive effects of the
PC board traces.
Program Verify
A verify should be performed on the programmed bits to determine
whether they were correctly programmed. The verify may be
performed with VPP at 6.25V. VPP must be at VCC, except during
programming and program verify.
MANUFACTURER’S IDENTIFICATION CODE
The EPROM has a manufacturer’s identification code to aid in
programming. When the device is inserted in an EPROM programmer socket, the programmer reads the code and then
automatically calls up the specific programming algorithm for the
part. This automatic programming control is only possible with
programmers which have the capability of reading the code.
The Manufacturer’s Identification code, shown in Table 2, specifically identifies the manufacturer and device type. The code for the
NM27LV210 is “8FD6”, where “8F” designates that it is made by
Fairchild Semiconductor, and “D6” designates a 1 Megabit (64K
x 16) part.
TABLE 2. Manufacturer’s Identification Code
Pins
A0
(21)
A9
(31)
O7
(12)
O6
(13)
O5
(14)
O4
(15)
O3
(16)
O2
(17)
O1
(18)
O0
(19)
Manufacturer Code
VIL
12V
1
0
0
0
1
1
1
1
8F
Device Code
VIH
12V
1
1
0
1
0
1
1
0
D6
8
Hex
Data
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NM27LV210 1,048,576-Bit (64K x 16) Low Voltage EPROM
Functional Description (Continued)
+0.006
0.650 –0.000
+0.15
16.51 0
45°X 0.045
[1.14]
PIN 1 IDENT
6
1 44
17
0.017 ±0.021
TYP
[0.43 ±0.10]
0.045
45°X [1.14]
40
39
0.026–0.032
[0.66–0.81]
TYP
0.610 ±0.020
[15.49 ±0.51]
TYP
Seating
plane
17
29
18
0.500
TYP
[12.70]
28
0.050
TYP
[1.27]
0.020 MIN TYP
[0.51]
0.690 ± 0.005 TYP
[17.53 –0.13]
0.105 ±0.015 TYP
[2.67 ±0.38]
0.165–0.180 TYP
[4.19–4.57]
0.004 [0.10]
44-Lead Plastic Chip Carrier (V)
Order Number NM27LV210XXX
Package Number V44A
Life Support Policy
Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written
approval of the President of Fairchild Semiconductor Corporation. As used herein:
1. Life support devices or systems are devices or systems which,
(a) are intended for surgical implant into the body, or (b) support
or sustain life, and whose failure to perform, when properly
used in accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a significant
injury to the user.
Fairchild Semiconductor
Americas
Customer Response Center
Tel. 1-888-522-5372
2. A critical component is any component of a life support device
or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system,
or to affect its safety or effectiveness.
Fairchild Semiconductor
Europe
Fax:
+44 (0) 1793-856858
Deutsch
Tel:
+49 (0) 8141-6102-0
English
Tel:
+44 (0) 1793-856856
Français
Tel:
+33 (0) 1-6930-3696
Italiano
Tel:
+39 (0) 2-249111-1
Fairchild Semiconductor
Hong Kong
8/F, Room 808, Empire Centre
68 Mody Road, Tsimshatsui East
Kowloon. Hong Kong
Tel; +852-2722-8338
Fax: +852-2722-8383
Fairchild Semiconductor
Japan Ltd.
4F, Natsume Bldg.
2-18-6, Yushima, Bunkyo-ku
Tokyo, 113-0034 Japan
Tel: 81-3-3818-8840
Fax: 81-3-3818-8841
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
9
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NM27LV210 1,048,576-Bit (64K x 16) Low Voltage EPROM
Physical Dimensions inches (millimeters) unless otherwise noted