FINAL Advanced Micro Devices Am27C4096 4 Megabit (262,144 x 16-Bit) CMOS EPROM DISTINCTIVE CHARACTERISTICS ■ Fast access time ■ Single + 5 V power supply — 90 ns ■ Low power consumption ■ ± 10% power supply tolerance standard on most speeds — 100 µA maximum CMOS standby current ■ JEDEC-approved pinout ■ 100% Flashrite programming — Plug in upgrade of 1 Mbit and 2 Mbit EPROMs — 40-pin DIP/PDIP — 44-pin PLCC — Typical programming time of 32 seconds ■ Latch-up protected to 100 mA from –1 V to VCC + 1 V ■ High noise immunity GENERAL DESCRIPTION The Am27C4096 is a 4 Mbit ultraviolet erasable programmable read-only memory. It is organized as 256K words by 16 bits per word, operates from a single +5 V supply, has a static standby mode, and features fast single address location programming. The Am27C4096 is ideal for use in 16-bit microprocessor systems. Products are available in windowed ceramic DIP packages as well as plastic one time programmable (OTP) PDIP and PLCC packages. Typically, any byte can be accessed in less than 90 ns, allowing operation with high-performance microprocessors without any WAIT states. The Am27C4096 offers separate Output Enable (OE) and Chip Enable (CE) controls, thus eliminating bus contention in a multiple bus microprocessor system. AMDs CMOS process technology provides high speed, low power, and high noise immunity. Typical power consumption is only 125 mW in active mode, and 125 µW in standby mode. All signals are TTL levels, including programming signals. Bit locations may be programmed singly, in blocks, or at random. The Am27C4096 supports AMD’s Flashrite programming algorithm (100 µs pulses) resulting in typical programming times of 32 seconds. BLOCK DIAGRAM Data Outputs DQ0–DQ15 VCC VSS VPP OE CE/PGM A0–A17 Address Inputs Output Enable Chip Enable and Prog Logic Output Buffers Y Decoder Y Gating X Decoder 4.194,304-Bit Cell Matrix 11408E-1 2-126 Publication# 11408 Rev. E Issue Date: May 1995 Amendment /0 AMD PRODUCT SELECTOR GUIDE Family Part No. Ordering Part No: Am27C4096 VCC + 5% -95 VCC +10% -105 -255 -100 -120 -150 -200 90 100 120 150 200 250 CE (E) Access Time (ns) 90 100 120 150 200 250 OE (G) Access Time (ns) 50 50 50 65 75 75 Max Access Time (ns) CONNECTION DIAGRAMS Top View DIP PLCC 5 36 A14 DQ12 6 35 A13 DQ11 7 34 DQ10 8 33 A12 A11 DQ12 7 39 A13 DQ9 9 32 A10 DQ11 8 38 A12 DQ8 10 31 A9 DQ10 9 37 A11 VSS 11 30 10 36 A10 DQ8 11 35 A9 DQ7 DQ6 DQ5 DQ4 DQ9 DQ13 DQ14 6 5 4 A14 DQ13 A15 A15 A16 4 A17 A16 37 VCC 38 DQ14 DU 39 3 VPP 2 DQ15 CE (E)/PGM (P) VCC A17 1 DQ15 40 VPP CE (E)/PGM (P) 1 44 43 42 41 40 3 2 12 29 VSS A8 13 28 A7 VSS 12 34 VSS 13 33 NC 14 27 A6 NC 15 26 A5 DQ7 14 32 A8 A7 16 25 A4 DQ6 15 31 DQ2 17 24 A3 DQ5 16 30 A6 DQ1 18 23 A2 DQ4 17 29 A5 DQ0 19 22 A1 20 21 A0 A4 A3 A2 A1 A0 DU DQ0 OE (G) DQ1 11408E-2 DQ2 OE (G) 18 19 20 21 22 23 24 25 26 27 28 DQ3 DQ3 11408E-3 Note: 1. JEDEC nomenclature is in parentheses. PIN DESIGNATIONS A0– A17 LOGIC SYMBOL = Address Inputs 18 CE (E)/PGM (P) = Chip Enable Input DQ0–DQ15 = Data Input/Outputs DU = No External Connection NC = No Internal Connection OE (G) = Output Enable Input VCC = VCC Supply Voltage VPP = Program Voltage Input VSS = Ground A0–A17 16 DQ0–DQ15 CE (E)/PGM OE (G) 11408E-4 Am27C4096 2-127 AMD ORDERING INFORMATION UV EPROM Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of: AM27C4096 -95 D C B OPTIONAL PROCESSING Blank = Standard processing B = Burn-in TEMPERATURE RANGE C = Commercial (0°C to +70°C) I = Industrial (–40°C to +85°C) E = Extended Commercial (–55°C to +125°C) PACKAGE TYPE D = 40-Pin Ceramic DIP (CDV040) SPEED OPTION See Product Selector Guide and Valid Combinations DEVICE NUMBER/DESCRIPTION Am27C4096 4 Megabit (262,144 x 16 Bit) CMOS UV EPROM Valid Combinations AM27C4096-95 AM27C4096-100 AM27C4096-105 AM27C4096-120 AM27C4096-150 AM27C4096-200 AM27C4096-255 2-128 DC, DCB DC, DCB, DI, DIB Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. DC, DCB, DE, DEB, DI, DIB DC, DCB, DI, DIB Am27C4096 AMD ORDERING INFORMATION OTP Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of: AM27C4096 -105 P C OPTIONAL PROCESSING Blank = Standard processing TEMPERATURE RANGE C = Commercial (0°C to +70°C) I = Industrial (–40°C to +85°C) PACKAGE TYPE P = 40-Pin Plastic DIP (PD 040) J = 44-Pin Rectangular Plastic Leaded Chip Carrier (PL 044) SPEED OPTION See Product Selector Guide and Valid Combinations DEVICE NUMBER/DESCRIPTION Am27C4096 4 Megabit (262,144 x 16 Bit ) CMOS OTP EPROM Valid Combinations AM27C4096-105 AM27C4096-120 AM27C4096-150 AM27C4096-200 AM27C4096-255 PC, JC PC, JC, PI, JI Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. Am27C4096 2-129 AMD FUNCTIONAL DESCRIPTION Erasing The Am27C4096 In order to clear all locations of their programmed contents, it is necessary to expose the Am27C4096 to an ultraviolet light source. A dosage of 15 W seconds/cm2 is required to completely erase an Am27C4096. This dosage can be obtained by exposure to an ultraviolet lamp — wavelength of 2537 A° — with intensity of 12,000 µW/ cm2 for 15 to 20 minutes. The Am27C4096 should be directly under and about one inch from the source and all filters should be removed from the UV light source prior to erasure. It is important to note that the Am27C4096 and similar devices will erase with light sources having wavelengths shorter than 4000 A° . Although erasure times will be much longer than with UV sources at 2537 A° , exposure to fluorescent light and sunlight will eventually erase the Am27C4096 and exposure to them should be prevented to realize maximum system reliability. If used in such an environment, the package window should be covered by an opaque label or substance. Programming the Am27C4096 Upon delivery or after each erasure the Am27C4096 has all 4,194,304 bits in the “ONE” or HIGH state. “ZEROs” are loaded into the Am27C4096 through the procedure of programming. The programming mode is entered when 12.75 V ± 0.25 V is applied to the VPP pin, CE/PGM is at VIL and OE is at VIH. For programming, the data to be programmed is applied 16 bits in parallel to the data output pins. The Flashrite algorithm reduces programming time by using 100 µs programming pulses and by giving each address only as many pulses as are necessary in order to reliably program the data. After each pulse is applied to a given address, the data in that address is verified. If the data does not verify, additional pulses are given until it verifies or the maximum is reached. This process is repeated while sequencing through each address of the Am27C4096. This part of the algorithm is done at VCC = 6.25 V to assure that each EPROM bit is programmed to a sufficiently high threshold voltage after the final address is completed, the entire EPROM memory is verified at VCC = VPP = 5.25 V. Please refer to Section 6 for programming flow chart and characteristics. Program Inhibit Programming of multiple Am27C4096 in parallel with different data is also easily accomplished. Except for CE/PGM, all like inputs of the parallel Am27C4096 may be common. A TTL low-level program pulse applied to 2-130 an Am27C4096 CE/PGM input with VPP = 12.75 V ± 0.25 V and OE HIGH will program that Am27C4096. A high-level CE/PGM input inhibits the other Am27C4096 devices from being programmed. Program Verify A verify should be performed on the programmed bits to determine that they were correctly programmed. The verify should be performed with OE at VIL, CE/PGM at VIH, and VPP between 12.5 V and 13.0 V. Auto Select Mode The auto select mode allows the reading out of a binary code from an EPROM that will identify its manufacturer and type. This mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional in the 25°C ± 5°C ambient temperature range that is required when programming the Am27C4096. To activate this mode, the programming equipment must force 12.0 V ± 0.5 V on address line A9 of the Am27C4096. Two identifier bytes may then be sequenced from the device outputs by toggling address line A0 from VIL to VIH. All other address lines must be held at VIL during auto select mode. Byte 0 (A0 = VIL) represents the manufacturer code, and byte 1(A0 = VIH), the device identifier code. For the Am27C4096, these two identifier bytes are given in the Mode Select Table. All identifiers for manufacturer and device codes will possess odd parity, with the MSB (DQ7) defined as the parity bit. Read Mode The Am27C4096 has two control functions, both of which must be logically satisfied in order to obtain data at the outputs. Chip Enable (CE/PGM) is the power control and should be used for device selection. Output Enable (OE) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that addresses are stable, address access time (tACC) is equal to the delay from CE/PGM to output (tCE). Data is available at the outputs tOE after the falling edge of OE, assuming that CE/PGM has been LOW and addresses have been stable for at least tACC – tOE. Standby Mode The Am27C4096 has a CMOS standby mode which reduces the maximum VCC current to 100 µA. It is placed in CMOS-standby when CE/PGM is at VCC ± 0.3 V. The Am27C4096 also has a TTL-standby mode which reduces the maximum VCC current to 1.0 mA. It is placed in TTL-standby when CE/PGM is at VIH. When in standby mode, the outputs are in a high-impedance state, independent of the OE input. Am27C4096 AMD Output OR-Tieing System Applications To accommodate multiple memory connections, a twoline control function is provided to allow for: During the switch between active and standby conditions, transient current peaks are produced on the rising and falling edges of Chip Enable. The magnitude of these transient current peaks is dependent on the output capacitance loading of the device. At a minimum, a 0.1-µF ceramic capacitor (high frequency, low inherent inductance) should be used on each device between VCC and VSS to minimize transient effects. In addition, to overcome the voltage drop caused by the inductive effects of the printed circuit board traces on EPROM arrays, a 4.7-µF bulk electrolytic capacitor should be used between VCC and VSS for each eight devices. The location of the capacitor should be close to where the power supply is connected to the array. Low memory power dissipation Assurance that output bus contention will not occur It is recommended that CE/PGM be decoded and used as the primary device-selecting function, while OE be made a common connection to all devices in the array and connected to the READ line from the system control bus. This assures that all deselected memory devices are in low-power standby mode and that the output pins are only active when data is desired from a particular memory device. MODE SELECT TABLE Pins CE/PGM OE A0 A9 VPP Outputs VIL VIL X X X DOUT Output Disable VIL VIH X X X High Z Standby (TTL) VIH X X X X High Z Mode Read VCC ± 0.3 V X X X X High Z Program VIL VIH X X VPP DIN Program Verify VIH VIL X X VPP DOUT Program Inhibit VIH X X X VPP High Z Standby (CMOS) Auto Select Manufacturer Code VIL VIL VIL VH X O1H (Note 3) Device Code VIL VIL VIH VH X 19H Notes: 1. VH = 12.0 V ± 0.5 V. 2. X = Either VIH or VIL. 3. A1–A8 = A10–A17 = VIL. 4. See DC Programming Characteristics for VPP voltage during programming. Am27C4096 2-131 AMD ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature: OTP Products . . . . . . . . . . . . . . . . . –65°C to +125°C All Other Products . . . . . . . . . . . . . . –65°C to +150°C Commercial (C) Devices Ambient Temperature with Power Applied . . . . . . . . . . . . . –55°C to +125°C Ambient Temperature (TA) . . . . . . . . . . 0°C to +70°C Industrial (I) Devices Ambient Temperature (TA) . . . . . . . . –40°C to +85°C Voltage with Respect to VSS: Extended Commercial (E) Devices All pins except A9, VPP, and VCC (Note 1) . . . . . . . . . . –0.6 V to VCC + 0.6 V Ambient Temperature (TA) . . . . . . . –55°C to +125°C A9 and VPP (Note 2) . . . . . . . . . . . . . –0.6 V to 13.5 V VCC for Am27C4096-XX5 . . . . . . . +4.75 V to +5.25 V VCC for Am27C4096-XX0 . . . . . . . +4.50 V to +5.50 V VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.6 V to 7.0 V Notes: 1. During transitions, the inputs may overshoot VSS to –2.0 V for periods of up to 20 ns. Maximum DC voltage on input and I/O may overshoot to VCC + 2.0 V for periods of up to 20 ns. Supply Read Voltages: Operating ranges define those limits between which the functionality of the device is guaranteed. 2. During transitions, A9 and VPP may overshoot VSS to –2.0 V for periods of up to 20 ns. A9 and VPP must not exceed 13.5 V for any period of time. Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. 2-132 Am27C4096 AMD DC CHARACTERISTICS over operating range unless otherwise specified (Notes 1, 2 and 4) Parameter Symbol Parameter Description Test Conditions Min VOH Output HIGH Voltage IOH = –400 µA 2.4 VOL Output LOW Voltage IOL = 2.1 mA VIH Input HIGH Voltage VIL Input LOW Voltage ILI Input Load Current ILO ICC1 Max Unit V 0.45 V 2.0 VCC +0.5 V –0.5 +0.8 V VIN = 0 V to VCC 1.0 µA Output Leakage Current VOUT = 0 V to VCC 5.0 µA VCC Active Current (Note 3) CE = VIL, f = 5 MHz IOUT = 0 mA C/I Devices 50 E Devices 60 mA ICC2 VCC TTL Standby CE = VIH 1.0 mA ICC3 VCC CMOS Standby CE = Vcc ± 0.3 V 100 µA IPP1 VPP Current During Read CE = OE = VIL, VPP = VCC 100 µA Notes: 1. VCC must be simultaneously or before VPP, and removed simultaneously or after VPP. 2. Caution: The Am27C4096 must not be removed from (or inserted into) a socket when VCC or VPP is applied. 3. ICC1 is tested with OE = VIH to simulate open outputs. 35 30 30 28 Supply Current in mA Supply Current in mA 4. Minimum DC Input Voltage is –0.5 V during transitions, the inputs may overshoot –2.0 V for periods less than 20 ns. Maximum DC Voltage on output pins is VCC +0.5 V, which may overshoot to VCC +2.0 V for periods less than 20 ns. 25 20 15 1 2 3 4 5 6 7 8 9 10 26 24 22 –75 –50 –25 0 25 50 75 100 125 150 Temperature in °C Frequency in MHz Figure 1. Typical Supply Current vs. Frequency VCC = 5.5 V, T = 25°C Figure 2. Typical Supply Current vs. Temperature VCC = 5.5 V, f = 5 MHz 11408E-5 11408E-6 Am27C4096 2-133 AMD CAPACITANCE Parameter Symbol CIN COUT CDV040 Parameter Description Test Conditions Input Capacitance Output Capacitance PD040 PL044 Typ Max Typ Max Typ Max Unit VIN = 0 V 10 13 6 8 10 13 pF VOUT = 0 V 10 13 8 10 12 14 pF Notes: 1. This parameter is only sampled and not 100% tested. 2. TA = +25°C, f = 1 MHz. SWITCHING CHARACTERISTICS over operating range unless otherwise specified (Notes 1, 3 and 4) Am27C4096 Parameter Symbols JEDEC Standard -95 -105 -120 -150 -200 -255 Unit AVQV tACC Address to Output Delay CE = OE = VIL Min Max — 90 — 100 — 120 — 150 — 200 — 250 ns tELQV tCE Chip Enable to Output Delay OE = VIL Min Max — 90 — 100 — 120 — 150 — 200 — 250 ns tGLQV tOE Output Enable to Output Delay CE = VIL Min Max — 50 — 50 — 50 — 65 — 75 — 75 ns tEHQZ , tGHQZ tDF (Note 2) Min — — — — — — Max 30 30 40 40 40 60 Min 0 0 0 0 0 0 Max — — — — — — tAXQX tOH Parameter Description Test Conditions Chip Enable HIGH or Output Enable HIGH, whichever comes first, to Output Float ns Output Hold from Addresses, CE, or OE, whichever occurred first ns Notes: 1. VCC must be applied simultaneously or before VPP, and removed simultaneously or after VPP. 2. This parameter is only sampled and not 100% tested. 3. Caution: The Am27C4096 must not be removed from (or inserted into) a socket or board when VPP or VCC is applied. 4. Output Load: 2-134 1 TTL gate and CL = 100 pF Input Rise and Fall Times: 20 ns Input Pulse Levels: 0.45 V to 2.4 V Timing Measurement Reference Level: 0.8 V and 2 V inputs and outputs. Am27C4096 AMD SWITCHING TEST CIRCUIT Device Under Test 2.7 kΩ 5.0 V CL Diodes = IN3064 or Equivalent 6.2 kΩ 11408E-7 CL = 100 pF including jig capacitance SWITCHING TEST WAVEFORM 2.4 V 2.0 V 2.0 V Test Points 0.8 V 0.8 V 0.45 V Input Output 11408E-8 AC Testing: Inputs are driven at 2.4 V for a Logic “1” and 0.45 V for a Logic “0”. Input pulse rise and fall times are ≤ 20 ns. Am27C4096 2-135 AMD KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS OUTPUTS Must be Steady Will be Steady May Change from H to L Will be Changing from H to L May Change from L to H Will be Changing from L to H Don’t Care, Any Change Permitted Changing, State Unknown Does Not Apply Center Line is HighImpedance “Off” State KS000010 SWITCHING WAVEFORM 2.4 Addresses 0.45 2.0 0.8 2.0 0.8 Addresses Valid CE/PGM tCE OE Output High Z tOE tACC (Note 1) tOH Valid Output tDF (Note 2) High Z 11408E-9 Notes: 1. OE may be delayed up to tACC – tOE after the falling edge of the addresses without impact on tACC. 2. tDF is specified from OE or CE, whichever occurs first. 2-136 Am27C4096