K9F5608R0D
K9F5608U0D K9F5608D0D
FLASH MEMORY
K9F5608X0D
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
1
K9F5608R0D
K9F5608U0D K9F5608D0D
FLASH MEMORY
Document Title
32M x 8 Bit NAND Flash Memory
Revision History
Revision No. History
Draft Date
Remark
0.0
Initial issue
May 16th. 2005
Advance
0.1
1. Leaded package devices are eliminated
Aug. 11th. 2005
Advance
0.2
Oct. 17th. 2005
Preliminary
1.0
Oct. 30th. 2005
Final
1.1
1. LOCKPRE pin mode is eliminated
Dec. 30th 2005
Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site.
http://www.samsung.com/Products/Semiconductor/Flash/TechnicalInfo/datasheets.htm
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near you.
2
K9F5608R0D
K9F5608U0D K9F5608D0D
FLASH MEMORY
32M x 8 Bit NAND Flash Memory
PRODUCT LIST
Part Number
Vcc Range
K9F5608R0D-J
1.65 ~ 1.95V
K9F5608D0D-P
K9F5608D0D-J
Organization
FBGA
TSOP1
2.4 ~ 2.9V
X8
K9F5608U0D-P
K9F5608U0D-J
PKG Type
2.7 ~ 3.6V
FBGA
TSOP1
FBGA
K9F5608U0D-F
WSOP1
FEATURES
• Voltage Supply
- 1.8V device(K9F5608R0D) : 1.65~1.95V
- 2.65V device(K9F5608D0D) : 2.4~2.9V
- 3.3V device(K9F5608U0D) : 2.7 ~ 3.6 V
• Organization
- Memory Cell Array
-(32M + 1024K)bit x 8 bit
- Data Register
- (512 + 16)bit x 8bit
• Automatic Program and Erase
- Page Program
-(512 + 16)Byte
- Block Erase :
- (16K + 512)Byte
• Page Read Operation
- Page Size
- (512 + 16)Byte
- Random Access
: 15µs(Max.)
- Serial Page Access : 50ns(Min.)
• Fast Write Cycle Time
- Program time : 200µs(Typ.)
- Block Erase Time : 2ms(Typ.)
• Command/Address/Data Multiplexed I/O Port
• Hardware Data Protection
- Program/Erase Lockout During Power Transitions
• Reliable CMOS Floating-Gate Technology
- Endurance
: 100K Program/Erase Cycles
- Data Retention : 10 Years
• Command Register Operation
• Intelligent Copy-Back
• Unique ID for Copyright Protection
• Package
- K9F5608D(U)0D-PCB0/PIB0
48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)- Pb-free Package
- K9F5608X0D-JCB0/JIB0
63- Ball FBGA ( 9 x 11 /0.8mm pitch , Width 1.0 mm)
- Pb-free Package
- K9F5608U0D-FCB0/FIB0
48 - Pin WSOP I (12X17X0.7mm)- Pb-free Package
* K9F5608U0D-F(WSOPI ) is the same device as
K9F5608U0D-P(TSOP1) except package type.
GENERAL DESCRIPTION
Offered in 32Mx8bit , the K9F5608X0D is 256M bit with spare 8M bit capacity. The device is offered in 1.8V, 2.65V, 3.3V Vcc. Its
NAND cell provides the most cost-effective solutIon for the solid state mass storage market. A program operation can be performed
in typical 200µs on a 528-byte page and an erase operation can be performed in typical 2ms on a 16K-byte block. Data in the page
can be read out at 50ns cycle time per byte. The I/O pins serve as the ports for address and data input/output as well as command
input. The on-chip write control automates all program and erase functions including pulse repetition, where required, and internal
verification and margining of data. Even the write-intensive systems can take advantage of the K9F5608X0D′s extended reliability of
100K program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm.
The K9F5608X0D is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable
applications requiring non-volatility.
3
K9F5608R0D
K9F5608U0D K9F5608D0D
FLASH MEMORY
PIN CONFIGURATION (TSOP1)
K9F5608D(U)0D-PCB0/PIB0
N.C
N.C
N.C
N.C
N.C
N.C
R/B
RE
CE
N.C
N.C
Vcc
Vss
N.C
N.C
CLE
ALE
WE
WP
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
I/O7
I/O6
I/O5
I/O4
N.C
N.C
N.C
Vcc
Vss
N.C
N.C
N.C
I/O3
I/O2
I/O1
I/O0
N.C
N.C
N.C
N.C
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
PACKAGE DIMENSIONS
48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)
48 - TSOP1 - 1220F
0.10
MAX
0.004
Unit :mm/Inch
#48
#24
#25
12.40
0.488 MAX
12.00
0.472
+0.003
( 0.25 )
0.010
#1
0.008-0.001
0.50
0.0197
0.16 -0.03
+0.075
18.40±0.10
0.724±0.004
0~8°
0.45~0.75
0.018~0.030
+0.003
0.005-0.001
0.25
0.010 TYP
1.00±0.05
0.039±0.002
0.125 0.035
+0.07
0.20 -0.03
+0.07
20.00±0.20
0.787±0.008
( 0.50 )
0.020
4
1.20
0.047MAX
0.05
0.002 MIN
K9F5608R0D
K9F5608U0D K9F5608D0D
FLASH MEMORY
PIN CONFIGURATION (FBGA)
K9F5608X0D-JCB0/JIB0
Top View
1
2
3
4
5
6
N.C N.C
A
N.C N.C
N.C
N.C N.C
B
C
D
E
F
G
H
/WP
ALE
Vss
/CE
/WE
R/B
NC
/RE
CLE
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
I/O0
NC
NC
NC
Vcc
VccQ I/O5
I/O7
NC
I/O1
NC
Vss
I/O2
I/O3 I/O4
I/O6
Vss
N.C N.C
N.C N.C
N.C N.C
N.C N.C
PACKAGE DIMENSIONS
63-Ball FBGA (measured in millimeters)
Top View
Bottom View
9.00±0.10
0.80 x 9= 7.20
0.80 x 5= 4.00
6
(Datum A)
5
0.80
4
3
2
B
1
0.80
9.00±0.10
A
#A1
A
D
2.80
E
F
11.00±0.10
C
0.80 x7= 5.60
11.00±0.10
(Datum B)
0.80 x11= 8.80
B
G
H
∅ 0.20 M A B
2.00
0.25(Min.)
Side View
9.00±0.10
0.10MAX
5
0.45±0.05
1.00(Max.)
63-∅0.45±0.05
K9F5608R0D
K9F5608U0D K9F5608D0D
FLASH MEMORY
PIN CONFIGURATION (WSOP1)
K9F5608U0D-FCB0/FIB0
N.C
N.C
DNU
N.C
N.C
N.C
R/B
RE
CE
DNU
N.C
Vcc
Vss
N.C
DNU
CLE
ALE
WE
WP
N.C
N.C
DNU
N.C
N.C
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
N.C
N.C
DNU
N.C
I/O7
I/O6
I/O5
I/O4
N.C
DNU
N.C
Vcc
Vss
N.C
DNU
N.C
I/O3
I/O2
I/O1
I/O0
N.C
DNU
N.C
N.C
PACKAGE DIMENSIONS
48-PIN LEAD PLASTIC VERY VERY THIN SMALL OUT-LINE PACKAGE TYPE (I)
48 - WSOP1 - 1217F
Unit :mm
0.70 MAX
0.58±0.04
15.40±0.10
#48
#24
#25
0.20
0.50TYP
(0.50±0.06)
12.40MAX
12.00±0.10
+0.07
-0.03
0.16
+0.07
-0.03
#1
8°
0° ~
0.10 +0.075
-0.035
(0.01Min)
0.45~0.75
17.00±0.20
6
K9F5608R0D
K9F5608U0D K9F5608D0D
FLASH MEMORY
PIN DESCRIPTION
Pin NAME
Pin Function
I/O0 ~ I/O7
DATA INPUTS/OUTPUTS
The I/O pins are used to input command, address and data, and to output data during read operations. The I/
O pins float to high-z when the chip is deselected or when the outputs are disabled.
CLE
COMMAND LATCH ENABLE
The CLE input controls the activating path for commands sent to the command register. When active high,
commands are latched into the command register through the I/O ports on the rising edge of the WE signal.
ALE
ADDRESS LATCH ENABLE
The ALE input controls the activating path for address to the internal address registers. Addresses are
latched on the rising edge of WE with ALE high.
CE
CHIP ENABLE
The CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and
the device does not return to standby mode in program or erase operation. Regarding CE control during
read operation, refer to ’Page read’ section of Device operation.
RE
READ ENABLE
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid
tREA after the falling edge of RE which also increments the internal column address counter by one.
WE
WRITE ENABLE
The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of
the WE pulse.
WP
WRITE PROTECT
The WP pin provides inadvertent write/erase protection during power tra nsitions. The internal high voltage
generator is reset when the WP pin is active low.
R/B
READY/BUSY OUTPUT
The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or
random read operation is in process and returns to high state upon completion. It is an open drain output and
does not float to high-z condition when the chip is deselected or when outputs are disabled.
VccQ
OUTPUT BUFFER POWER
VccQ is the power supply for Output Buffer.
VccQ is internally connected to Vcc, thus should be biased to Vcc.
Vcc
POWER
VCC is the power supply for device.
Vss
GROUND
N.C
NO CONNECTION
Lead is not internally connected.
DNU
DO NOT USE
Leave it disconnected
NOTE : Connect all VCC and VSS pins of each device to common power supply outputs.
Do not leave VCC or VSS disconnected.
7
K9F5608R0D
K9F5608U0D K9F5608D0D
FLASH MEMORY
Figure 1-1. K9F5608X0D FUNCTIONAL BLOCK DIAGRAM
VCC
VSS
A9 - A24
X-Buffers
Latches
& Decoders
A0 - A7
Y-Buffers
Latches
& Decoders
256M + 8M Bit
NAND Flash
ARRAY
(512 + 16)Byte x 65536
Page Register & S/A
A8
Y-Gating
Command
Command
Register
CE
RE
WE
VCC/VCCQ
VSS
I/O Buffers & Latches
Control Logic
& High Voltage
Generator
Output
Driver
Global Buffers
I/0 0
I/0 7
CLE ALE WP
Figure 2-1. K9F5608X0D ARRAY ORGANIZATION
1 Block =32 Pages
= (16K + 512) Byte
64K Pages
(=2,048 Blocks)
1st half Page Register
2nd half Page Register
(=256 Bytes)
(=256 Bytes)
1 Page = 528 Byte
1 Block = 528 Byte x 32 Pages
= (16K + 512) Byte
1 Device = 528Bytes x 32Pages x 2048 Blocks
= 264 Mbits
8 bit
512Byte
16 Byte
I/O 0 ~ I/O 7
Page Register
512 Byte
16 Byte
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
1st Cycle
A0
A1
A2
A3
A4
A5
A6
A7
2nd Cycle
A9
A10
A11
A12
A13
A14
A15
A16
3rd Cycle
A17
A18
A19
A20
A21
A22
A23
A24
NOTE : Column Address : Starting Address of the Register.
00h Command(Read) : Defines the starting address of the 1st half of the register.
01h Command(Read) : Defines the starting address of the 2nd half of the register.
* A8 is set to "Low" or "High" by the 00h or 01h Command.
* The device ignores any additional input of address cycles than required.
8
Column Address
Row Address
(Page Address)
K9F5608R0D
K9F5608U0D K9F5608D0D
FLASH MEMORY
PRODUCT INTRODUCTION
The K9F5608X0D is a 264Mbit(276,824,064 bit) memory organized as 65,536 rows(pages) by 528 columns. Spare eight columns are
located from column address of 512~527. A 528-byte data register is connected to memory cell arrays accommodating data transfer
between the I/O buffers and memory during page read and page program operations.The memory array is made up of 16 cells that
are serially connected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of two NAND structured strings. A NAND structure consists of 16 cells. Total 135168 NAND cells reside in a block. The array organization is shown in
Figure 2-1. The program and read operations are executed on a page basis, while the erase operation is executed on a block basis.
The memory array consists of 2048 separately erasable 16K-Byte blocks. It indicates that the bit by bit erase operation is prohibited
on the K9F5608X0D.
The K9F5608X0D has addresses multiplexed into 8 I/Os. This scheme dramatically reduces pin counts while providing high performance and allows systems upgrades to future densities by maintaining consistency in system board design. Command, address and
data are all written through I/O′s by bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch
Enable(CLE) and Address Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one bus cycle. For example, Reset command, Read command, Status Read command, etc require just one cycle bus.
Some other commands like Page Program and Copy-back Program and Block Erase, require two cycles: one cycle for setup and the
other cycle for execution. The 32M-byte physical space requires 24 addresses, thereby requiring three cycles for word-level addressing: column address, low row address and high row address, in that order. Page Read and Page Program need the same three
address cycles following the required command input. In Block Erase operation, however, only the two row address cycles are used.
Device operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of
the K9F5608X0D.
The device includes one block sized OTP(One Time Programmable), which can be used to increase system security or to provide
identification capabilities. Detailed information can be obtained by contact with Samsung.
Table 1. COMMAND SETS
Function
Read 1
1st. Cycle
2nd. Cycle
00h/01h
-
Read 2
50h
-
Read ID
90h
-
Reset
FFh
-
Page Program
80h
10h
Copy-Back Program
00h
8Ah
Block Erase
60h
D0h
Read Status
70h
-
Caution : Any undefined command inputs are prohibited except for above command set of Table 1.
9
Acceptable Command during Busy
O
O
K9F5608R0D
K9F5608U0D K9F5608D0D
FLASH MEMORY
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to VSS
Temperature Under Bias
Storage Temperature
K9F5608X0D-XCB0
K9F5608X0D-XIB0
K9F5608X0D-XCB0
K9F5608X0D-XIB0
Short Circuit Current
Symbol
Rating
Unit
VIN/OUT
-0.6 to + 4.6
VCC
-0.6 to + 4.6
VCCQ
-0.6 to + 4.6
V
-10 to +125
TBIAS
°C
-40 to +125
TSTG
-65 to +150
°C
Ios
5
mA
NOTE :
1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns.
Maximum DC voltage on input/output pins is VCC,+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.
2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions
as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltage reference to GND, K9F5608X0D-XCB0 :TA=0 to 70°C, K9F5608X0D-XIB0:TA=-40 to 85°C)
Parameter
Symbol
K9F5608R0D(1.8V)
K9F5608D0D(2.65V)
K9F5608U0D(3.3V)
Min
Typ.
Max
Min
Typ.
Max
Min
Typ.
Max
Unit
Supply Voltage
VCC
1.65
1.8
1.95
2.4
2.65
2.9
2.7
3.3
3.6
V
Supply Voltage
VCCQ
1.65
1.8
1.95
2.4
2.65
2.9
2.7
3.3
3.6
V
Supply Voltage
VSS
0
0
0
0
0
0
0
0
0
V
10
K9F5608R0D
K9F5608U0D K9F5608D0D
FLASH MEMORY
DC AND OPERATING CHARACTERISTICS(Recommended operating conditions otherwise noted.)
K9F5608X0D
Parameter
Symbol
Test Conditions
1.8V
2.65V
Min Typ Max Min Typ
Sequential
OperatRead
ing
Current Program
Erase
ICC1
tRC=50ns, CE=VIL
IOUT=0mA
3.3V
Max
Unit
Min Typ Max
-
8
20
-
10
20
-
10
20
ICC2
-
-
8
20
-
10
20
-
10
25
ICC3
-
-
8
20
-
10
20
-
10
25
Stand-by Current(TTL)
ISB1
CE=VIH, WP=0V/VCC
-
-
1
-
-
1
-
-
1
Stand-by Current(CMOS)
ISB2
CE=VCC-0.2, WP=0V/VCC
-
10
50
-
10
50
-
10
50
-
-
±10
-
-
±10
-
-
±10
-
-
±10
-
-
±10
-
-
Input Leakage Current
ILI
VIN=0 to Vcc(max)
Output Leakage Current
ILO
VOUT=0 to Vcc(max)
VccQ
I/O pins
Input High Voltage
-0.4
VIH*
VCC
Except I/O pins
Input Low Voltage, All
inputs
Output High Voltage
Level
Output Low Voltage
Level
VIL*
-0.4
-
-0.3
-
+0.3 -0.4
VCC
VCC
+0.3 -0.4
0.4
-0.3
-
VCCQ
+0.3
VCC
+0.3
0.5
2.0
-
2.0
-
-0.3
-
µA
±10
VCCQ
+0.3
VCC
+0.3
0.8
V
K9F5608R0D :IOH=-100µA
VOH
-
VCCQ VCCQ
mA
VCCQ
K9F5608D0D :IOH=-100µA
-
-
-
-
0.1
3
4
-
-0.1
K9F5608U0D :IOH=-400µA
VCCQ
-
-
2.4
-
-
-
-
0.4
-
-
0.4
3
4
-
8
10
-
-0.4
K9F5608R0D :IOL=100uA
VOL
K9F5608D0D :IOL=100µA
K9F5608U0D :IOL=2.1mA
K9F5608R0D :VOL=0.1V
Output Low Current(R/B) IOL(R/B) K9F5608D0D :VOL=0.1V
K9F5608U0D :VOL=0.4V
NOTE : VIL can undershoot to -0.4V and VIH can overshoot to VCC +0.4V for durations of 20 ns or less.
11
mA
K9F5608R0D
K9F5608U0D K9F5608D0D
FLASH MEMORY
VALID BLOCK
Parameter
Valid Block Number
Symbol
Min
Typ.
Max
Unit
NVB
2013
-
2048
Blocks
NOTE :
1. The device may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or program
factory-marked bad blocks. Refer to the attached technical notes for a appropriate management of invalid blocks.
2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block, does not require Error Correction up to 1K Program/Erase
cycles.
3. Minimum 1004 valid blocks are guaranteed for each contiguous 128Mb memory space.
AC TEST CONDITION
(K9F5608X0D-XCB0 :TA=0 to 70°C, K9F5608X0D-XIB0:TA=-40 to 85°C
K9F5608R0D : Vcc=1.65V~1.95V , K9F5608D0D : Vcc=2.4V~2.9V , K9F5608U0D : Vcc=2.7V~3.6V unless otherwise noted)
Parameter
K9F5608R0D
K9F5608D0D
K9F5608U0D
0V to VccQ
0V to VccQ
0.4V to 2.4V
5ns
5ns
5ns
VccQ/2
VccQ/2
1.5V
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Levels
K9F5608R0D:Output Load (VccQ:1.8V +/-10%)
K9F5608D0D:Output Load (VccQ:2.65V +/-10%) 1 TTL GATE and CL=30pF 1 TTL GATE and CL=30pF 1 TTL GATE and CL=50pF
K9F5608U0D:Output Load (VccQ:3.0V +/-10%)
K9F5608U0D:Output Load (VccQ:3.3V +/-10%)
-
-
1 TTL GATE and CL=100pF
CAPACITANCE(TA=25°C, VCC=1.8V/2.65V/3.3V, f=1.0MHz)
Item
Symbol
Test Condition
Min
Max
Unit
Input/Output Capacitance
CI/O
VIL=0V
-
10
pF
Input Capacitance
CIN
VIN=0V
-
10
pF
NOTE : Capacitance is periodically sampled and not 100% tested.
MODE SELECTION
CLE
ALE
CE
RE
WP
H
L
L
WE
H
X
Mode
L
H
L
H
X
H
L
L
H
H
L
H
L
H
H
L
L
L
H
H
Data Input
L
L
L
H
X
Data Output
L
L
L
H
H
X
During Read(Busy) On K9F5608U0D_Y,P,V,F or K9F5608D0D_Y,P
X
X
X
X
H
X
X
X
X
X
X
H
During Program(Busy)
X
X
X
X
X
H
During Erase(Busy)
X
X(1)
X
X
X
L
Write Protect
X
X
H
X
X
Read Mode
Write Mode
Command Input
Address Input(3clock)
Command Input
Address Input(3clock)
During Read(Busy) on the devices except On K9F5608U0D_Y,P,V,F or
K9F5608D0D_Y,P
0V/VCC(2) Stand-by
NOTE : 1. X can be VIL or VIH.
2. WP should be biased to CMOS high or CMOS low for standby.
12
K9F5608R0D
K9F5608U0D K9F5608D0D
FLASH MEMORY
PROGRAM/ERASE CHARACTERISTICS
Parameter
Symbol
Program Time
Number of Partial Program Cycles
in the Same Page
tPROG
Main Array
Spare Array
Block Erase Time
Nop
tBERS
Min
Typ
Max
Unit
-
200
500
µs
-
-
2
cycles
-
-
3
cycles
-
2
3
ms
AC TIMING CHARACTERISTICS FOR COMMAND / ADDRESS / DATA INPUT
Symbol
Min
Max
Unit
CLE setup Time
Parameter
tCLS
0
-
ns
CLE Hold Time
tCLH
10
-
ns
CE setup Time
tCS
0
-
ns
CE Hold Time
tCH
10
-
ns
WE Pulse Width
tWP
25(1)
-
ns
ALE setup Time
tALS
0
-
ns
ALE Hold Time
tALH
10
-
ns
Data setup Time
tDS
20
-
ns
Data Hold Time
tDH
10
-
ns
Write Cycle Time
tWC
50
-
ns
WE High Hold Time
tWH
15
-
ns
Address to Data Loading Time
tADL
100
-
ns
NOTE: 1. If tCS is set less than 10ns, tWP must be minimum 35ns, otherwise, tWP may be minimum 25ns.
13
K9F5608R0D
K9F5608U0D K9F5608D0D
FLASH MEMORY
AC CHARACTERISTICS FOR OPERATION
Parameter
Symbol
Min
Max
Unit
tR
-
15
µs
ALE to RE Delay
tAR
10
-
ns
CLE to RE Delay
tCLR
10
-
ns
Ready to RE Low
tRR
20
-
ns
RE Pulse Width
tRP
25
-
ns
WE High to Busy
tWB
-
100
ns
Read Cycle Time
tRC
50
-
ns
RE Access Time
tREA
-
30/35(1)
ns
Data Transfer from Cell to Register
CE Access Time
tCEA
-
45
ns
RE High to Output Hi-Z
tRHZ
-
30
ns
CE High to Output Hi-Z
tCHZ
-
20
ns
RE or CE High to Output hold
tOH
15
-
ns
RE High Hold Time
tREH
15
-
ns
tIR
0
-
ns
WE High to RE Low
tWHR
60
-
Device Resetting Time(Read/Program/Erase)
tRST
-
Output Hi-Z to RE Low
K9F5608U0DP,F or
K9F5608D0D-P only
ns
5/10/500
Symbol
Min
(2)
µs
Max
Uni
Last RE High to Busy(at sequential read)
tRB
-
100
ns
CE High to Ready(in case of interception by CE at
tCRY
-
50 +tr(R/B)(3)
ns
CE High Hold Time(at the last serial read)
tCEH
100
-
ns
(4)
NOTE: 1. K9F5608R0D tREA = 35ns.
2. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5us.
3. The time to Ready depends on the value of the pull-up resistor tied R/B pin.
4. To break the sequential read cycle, CE must be held high for longer time than tCEH.
14
K9F5608R0D
K9F5608U0D K9F5608D0D
FLASH MEMORY
NAND Flash Technical Notes
Initial Invalid Block(s)
Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by Samsung.
The information regarding the initial invalid block(s) is so called as the initial invalid block information. Devices with initial invalid
block(s) have the same quality level as devices with all valid blocks and have the same AC and DC characteristics. An initial invalid
block(s) does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a
select transistor. The system design must be able to mask out the invalid block(s) via address mapping. The 1st block, which is
placed on 00h block address, is guaranteed to be a valid block, does not require Error Correction up to 1K Program/Erase cycles.
Identifying Initial Invalid Block(s)
All device locations are erased(FFh) except locations where the initial invalid block(s) information is written prior to shipping. The
initial invalid block(s) status is defined by the 6th byte in the spare area. Samsung makes sure that either the 1st or 2nd page of every
initial invalid block has non-FFh data at the column address of 517. Since the initial invalid block information is also erasable in most
cases, it is impossible to recover the information once it has been erased. Therefore, the system must be able to recognize the initial
invalid block(s) based on the initial invalid block information and create the initial invalid block table via the following suggested flow
chart(Figure 3). Any intentional erasure of the initial invalid block information is prohibited.
Start
Set Block Address = 0
Increment Block Address
*
Create (or update)
Initial
Invalid Block(s) Table
No
Check "FFh" at the column address
517of the 1st and 2nd page in the block
Check "FFh" ?
Yes
No
Last Block ?
Yes
End
Figure 3. Flow chart to create initial invalid block table.
15
K9F5608R0D
K9F5608U0D K9F5608D0D
FLASH MEMORY
NAND Flash Technical Notes (Continued)
Error in write or read operation
Within its life time, the additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual
data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read failure after erase or program, block replacement should be done. Because program status fail during a page program does not affect
the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased
empty block and reprogramming the current target data and copying the rest of the replaced block. In case of Read, ECC must be
employed. To improve the efficiency of memory space, it is recommended that the read or verification failure due to single bit error be
reclaimed by ECC without any block replacement. The said additional block failure rate does not include those reclaimed blocks.
Failure Mode
Write
Read
ECC
Detection and Countermeasure sequence
Erase Failure
Status Read after Erase --> Block Replacement
Program Failure
Status Read after Program --> Block Replacement
Single Bit Failure
Verify ECC -> ECC Correction
: Error Correcting Code --> Hamming Code etc.
Example) 1bit correction & 2bit detection
Program Flow Chart
Start
Write 80h
Write Address
Write Data
Write 10h
Read Status Register
I/O 6 = 1 ?
or R/B = 1 ?
*
Program Error
No
Yes
No
I/O 0 = 0 ?
Yes
Program Completed
*
16
: If program operation results in an error, map out
the block including the page in error and copy the
target data to another block.
K9F5608R0D
K9F5608U0D K9F5608D0D
FLASH MEMORY
NAND Flash Technical Notes (Continued)
Erase Flow Chart
Read Flow Chart
Start
Start
Write 60h
Write 00h
Write Block Address
Write Address
Write D0h
Read Data
Read Status Register
ECC Generation
No
I/O 6 = 1 ?
or R/B = 1 ?
Reclaim the Error
No
Verify ECC
Yes
Yes
*
Erase Error
No
Page Read Completed
I/O 0 = 0 ?
Yes
Erase Completed
*
: If erase operation results in an error, map out
the failing block and replace it with another block.
Block Replacement
1st
∼
(n-1)th
nth
{
Block A
2
an error occurs.
(page)
1st
∼
(n-1)th
nth
Buffer memory of the controller.
{
Block B
1
(page)
* Step1
When an error happens in the nth page of the Block ’A’ during erase or program operation.
* Step2
Copy the nth page data of the Block ’A’ in the buffer memory to the nth page of another free block. (Block ’B’)
* Step3
Then, copy the data in the 1st ~ (n-1)th page to the same location of the Block ’B’.
* Step4
Do not further erase Block ’A’ by creating an ’invalid Block’ table or other appropriate scheme.
17
K9F5608R0D
K9F5608U0D K9F5608D0D
FLASH MEMORY
Pointer Operation of K9F5608X0D(X8)
Samsung NAND Flash has three address pointer commands as a substitute for the two most significant column addresses. ’00h’
command sets the pointer to ’A’ area(0~255byte), ’01h’ command sets the pointer to ’B’ area(256~511byte), and ’50h’ command sets
the pointer to ’C’ area(512~527byte). With these commands, the starting column address can be set to any of a whole
page(0~527byte). ’00h’ or ’50h’ is sustained until another address pointer command is inputted. ’01h’ command, however, is effective
only for one operation. After any operation of Read, Program, Erase, Reset, Power_Up is executed once with ’01h’ command, the
address pointer returns to ’A’ area by itself. To program data starting from ’A’ or ’C’ area, ’00h’ or ’50h’ command must be inputted
before ’80h’ command is written. A complete read operation prior to ’80h’ command is not necessary. To program data starting from
’B’ area, ’01h’ command must be inputted right before ’80h’ command is written.
Table 2. Destination of the pointer
Command
Pointer position
Area
00h
01h
50h
0 ~ 255 byte
256 ~ 511 byte
512 ~ 527 byte
1st half array(A)
2nd half array(B)
spare array(C)
"A" area
(00h plane)
"B" area
(01h plane)
256 Byte
256 Byte
"A"
"B"
"C" area
(50h plane)
16 Byte
"C"
Internal
Page Register
Pointer select
commnad
(00h, 01h, 50h)
Pointer
Figure 4. Block Diagram of Pointer Operation
(1) Command input sequence for programming ’A’ area
The address pointer is set to ’A’ area(0~255), and sustained
Address / Data input
00h
80h
Address / Data input
10h
00h
’A’,’B’,’C’ area can be programmed.
It depends on how many data are inputted.
80h
10h
’00h’ command can be omitted.
(2) Command input sequence for programming ’B’ area
The address pointer is set to ’B’ area(256~512), and will be reset to
’A’ area after every program operation is executed.
Address / Data input
01h
80h
Address / Data input
10h
01h
’B’, ’C’ area can be programmed.
It depends on how many data are inputted.
80h
10h
’01h’ command must be rewritten before
every program operation
(3) Command input sequence for programming ’C’ area
The address pointer is set to ’C’ area(512~527), and sustained
Address / Data input
50h
80h
Address / Data input
10h
50h
Only ’C’ area can be programmed.
80h
’50h’ command can be omitted.
18
10h
K9F5608R0D
K9F5608U0D K9F5608D0D
FLASH MEMORY
System Interface Using CE don’t-care.
For an easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown below. The internal
528byte page registers are utilized as seperate buffers for this operation and the system design gets more flexible. In addition, for
voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and reading would provide significant savings in power consumption.
Figure 6. Program Operation with CE don’t-care.
CLE
CE don’t-care
WE
≈
≈
CE
ALE
I/Ox
80h
Start Add.(3Cycle)
tCS
Data Input
tCH
Data Input
10h
tCEA
CE
CE
RE
tWP
tREA
tOH
WE
I/O0~7
out
Figure 7. Read Operation with CE don’t-care.
CLE
On K9F5608U0D_Y,P,V,F or K9F5608D0D_Y,P
CE must be held
low during tR
CE don’t-care
≈
CE
RE
ALE
tR
R/B
WE
I/Ox
00h
Data Output(sequential)
Start Add.(3Cycle)
19
K9F5608R0D
K9F5608U0D K9F5608D0D
FLASH MEMORY
I/O
DATA
I/Ox
Data In/Out
I/O 0 ~ I/O 7
~528byte
Device
K9F5608X0D(X8 device)
NOTE: 1. I/O8~15 must be set to "0" during command or address input.
I/O8~15 are used only for data bus.
Command Latch Cycle
CLE
tCLS
tCLH
tCS
tCH
CE
tWP
WE
tALH
tALS
ALE
tDH
tDS
Command
I/Ox
Address Latch Cycle
tCLS
CLE
tWC
tCS
tWC
CE
tCH
tWP
tWP
WE
tWH
tALH tALS
tWH
tALH tALS
tALS
tWP
tALH
ALE
tDS
I/Ox
tDH
tDS
tDH
A9~A16
AO~A7
20
tDS
tDH
A17~A24
K9F5608R0D
K9F5608U0D K9F5608D0D
FLASH MEMORY
Input Data Latch Cycle
tCLH
CLE
tCH
CE
tWC
tALS
ALE
tWP
tWH
tDH
tDS
tDH
tDS
tDH
≈
tDS
tWP
≈
tWP
WE
I/Ox
DIN n
DIN 1
≈
DIN 0
Sequential Out Cycle after Read(CLE=L, WE=H, ALE=L)
tRC
≈
CE
tREA
≈
tREH
tREA
tRP
RE
tCHZ*
tOH
tREA
I/Ox
Dout
Dout
≈
tRHZ*
tRHZ*
tOH
Dout
≈
tRR
R/B
NOTES : Transition is measured ±200mV from steady state voltage with load.
This parameter is sampled and not 100% tested.
21
K9F5608R0D
K9F5608U0D K9F5608D0D
FLASH MEMORY
Status Read Cycle
tCLR
CLE
tCLS
tCLH
tCS
CE
tCH
tWP
WE
tCEA
tCHZ
tOH
tWHR1
RE
tDH
tDS
I/Ox
tIR
tRHZ
tOH
tREA
Status Output
70h
Read1 Operation (Read One Page)
CLE
1)
tCEH
On K9F5608U0D_Y,P,V,F or K9F5608D0D_Y,P
CE must be held
low during tR
CE
tCHZ
tOH
tWC
WE
tWB
tCRY
tAR
ALE
tR
RE
tRHZ
tOH
tRC
≈
N Address
I/Ox
Read
CMD
A0~A7
Column
Address
R/B
A9~A16
Dout N
A17~A24
Page(Row)
Address
Dout N+1
Dout N+2
Dout N+3
≈ ≈
tRR
Dout m
tRB
Busy
1)
m = 528 , Read CMD = 00h or 01h
NOTES : 1) is only valid On K9F5608U0D_Y,P,V,F or K9F5608D0D_Y,P
22
K9F5608R0D
K9F5608U0D K9F5608D0D
FLASH MEMORY
Read1 Operation (Intercepted by CE)
CLE
On K9F5608U0D_Y,P,V,F or K9F5608D0D_Y,P
CE must be held
low during tR
CE
WE
tWB
tCHZ
tOH
tAR
ALE
tRC
tR
RE
N Address
tRR
I/Ox
Read
CMD
Col. Add
Row Add1
Column
Address
Dout N
Row Add2
Dout N+1
Dout N+2
Dout N+3
Page(Row)
Address
Busy
R/B
Read2 Operation (Read One Page)
CLE
On K9F5608U0D_Y,P,V,F or K9F5608D0D_Y,P
CE must be held
low during tR
CE
WE
tR
tWB
tAR
ALE
RE
I/Ox
50h
Col. Add
Row Add1
Dout
n+M
Row Add2
R/B
Dout
n+M+1
≈
≈
tRR
Dout n+m
Selected
Row
M Address
A0~A3 are Valid Address & A4~A7 are Don′t care
n = 512, m = 16
n
m
Start
address M
23
K9F5608R0D
K9F5608U0D K9F5608D0D
FLASH MEMORY
Sequential Row Read Operation (only for On K9F5608U0D_Y,P,V,F or K9F5608D0D_Y,P)
CLE
CE
WE
Row Add1
Dout
N
Row Add2
Dout
N+1
Dout
N+2
Busy
R/B
Dout
0
≈
Ready
Dout
527
Dout
1
Dout
2
Dout
527
≈
Col. Add
≈
≈
00h
≈
RE
I/Ox
≈
ALE
Busy
M
M+1
N
Output
Output
Page Program Operation
CLE
CE
tWC
tWC
tWC
WE
tADL
tWB
tPROG
ALE
RE
80h
Col. Add
Sequential Data Column
Input Command Address
Row Add1
Row Add2
Page(Row)
Address
≈ ≈
I/Ox
N Address
Din
Din
N
N+1
1 up to m Data
Serial Input
Din
m
10h
70h
Program
Command
Read Status
Command
≈
R/B
m = 528 byte
24
I/O0
I/O0=0 Successful Program
I/O0=1 Error in Program
K9F5608R0D
K9F5608U0D K9F5608D0D
FLASH MEMORY
Copy-Back Program Operation
CLE
CE
tWC
WE
tWB
tWB
tPROG
ALE
tR
RE
I/Ox
00h
Col. Add
Row Add1
8Ah
Row Add2
70h
A0~A7 A9~A16 A17~A24
Program Column Page(Row)
Column Page(Row)
Address Address
≈
R/B
Address
≈
CommandAddress
Busy
Busy
I/O0
Read Status
Command
I/O0=0 Successful Program
I/O0=1 Error in Program
Block Erase Operation (Erase One Block)
CLE
CE
tWC
WE
tBERS
tWB
ALE
RE
I/Ox
60h
A9~A16
A17~A24
D0h
70h
I/O 0
Busy
R/B
Auto Block Erase
Setup Command
Erase Command
≈
Page(Row)
Address
Read Status
Command
25
I/O0=0 Successful Erase
I/O0=1 Error in Erase
K9F5608R0D
K9F5608U0D K9F5608D0D
FLASH MEMORY
Manufacture & Device ID Read Operation
CLE
CE
WE
ALE
tAR
RE
tREA
I/Ox
90h
Read ID Command
00h
ECh
Address. 1cycle
Maker Code
Device
Code*
Device Code
Device
Device Code*
K9F5608R0D
35h
K9F5608D0D
75h
K9F5608U0D
75h
26
K9F5608R0D
K9F5608U0D K9F5608D0D
FLASH MEMORY
DEVICE OPERATION
PAGE READ
Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00h to the command register along with three address cycles. Once the command is latched, it does not need to be written for the following page read operation. Two types of operations are available : random read, serial page read.
The random read mode is enabled when the page address is changed. The 528 byte of data within the selected page are transferred
to the data registers in less than 15µs(tR). The system controller can detect the completion of this data transfer(tR) by analyzing the
output of R/B pin. Once the data in a page is loaded into the registers, they may be read out in 50ns cycle time by sequentially pulsing
RE. High to low transitions of the RE clock output the data starting from the selected column address up to the last column address.
The way the Read1 and Read2 commands work is like a pointer set to either the main area or the spare area. Addresses A0~A3 set
the starting address of the spare area while addresses A4~A7 are ignored . The Read1 command is needed to move the pointer back
to the main area. Figures 8,9 show typical sequence and timings for each read operation.
Sequential Row Read is available only on K9F5608U0D_Y,P,V,F or K9F5608D0D_Y,P :
After the data of last column address is clocked out, the next page is automatically selected for sequential row read. Waiting 15µs
again allows reading the selected page. The sequential row read operation is terminated by bringing CE high. Unless the operation
is aborted, the page address is automatically incremented for sequential row read as in Read1 operation and spare sixteen bytes of
each page may be sequentially read. The Sequential Read 1 and 2 operations are allowed only within a block and after the last page
of a block being readout, the sequential read operation must be terminated by bringing CE high. When the page address moves onto
the next block, read command and address must be given. Figures 8-1, 9-1 show typical sequence and timings for sequential row
read operation.
Figure8. Read1 Operation
CLE
On K9F5608U0D_Y,P,V,F or K9F5608D0D_Y,P
CE must be held
low during tR
CE
WE
ALE
tR
R/B
RE
I/Ox
00h
Start Add.(3Cycle)
Data Output(Sequential)
A0 ~ A7 & A9 ~ A24
(00h Command)
1)
(01h Command)
1st half array
Main array
Data Field
Spare Field
2st half array
Data Field
NOTE: 1) After data access on 2nd half array by 01h command, the start pointer is automatically moved to 1st half
array (00h) at next cycle.
27
Spare Field
K9F5608R0D
K9F5608U0D K9F5608D0D
FLASH MEMORY
Figure 9. Read2 Operation
CLE
On K9F5608U0D_Y,P,V,F or K9F5608D0D_Y,P
CE must be held
low during tR
CE
WE
ALE
tR
R/B
RE
I/Ox
50h
Start Add.(3Cycle)
Data Output(Sequential)
Spare Field
A4 ~ A7 Don’t care
Main array
Data Field
Spare Field
Figure 8-1. Sequential Row Read1 Operation (only for K9F5608U0D_Y,P,V,F or K9F5608D0D_Y,P)
I/Ox
00h
01h
Data Output
Start Add.(3Cycle)
1st half array
2nd half array
1st
2nd
Nth
Data Field
Nth
(528 Byte)
(01h Command)
2nd half array
Block
Data Output
2nd
(528 Byte)
(00h Command)
1st half array
Data Output
1st
A0 ~ A7 & A9 ~ A24
tR
≈
tR
tR
R/B
1st
2nd
Nth
Data Field
Spare Field
28
Spare Field
K9F5608R0D
K9F5608U0D K9F5608D0D
FLASH MEMORY
Figure 9-1. Sequential Row Read2 Operation (only for K9F5608U0D_Y,P,V,F or K9F5608D0D_Y,P)
I/Ox
50h
Start Add.(3Cycle)
A0 ~ A3 & A9 ~ A24
≈
tR
tR
R/B
Data Output
1st
Data Output
Data Output
2nd
(16Byte)
Nth
(16Byte)
(A4 ~ A7 :
Don′t Care)
1st
Block
Nth
Data Field
Spare Field
29
tR
K9F5608R0D
K9F5608U0D K9F5608D0D
FLASH MEMORY
PAGE PROGRAM
The device is programmed basically on a page basis, but it does allow multiple partial page programing of a byte/word or consecutive
bytes/words up to 528, in a single page program cycle. The number of consecutive partial page programming operation within the
same page without an intervening erase operation should not exceed 2 for main array and 3 for spare array. The addressing may be
done in any random order in a block. A page program cycle consists of a serial data loading period in which up to 528 bytes of data
may be loaded into the page register, followed by a non-volatile programming period where the loaded data is programmed into the
appropriate cell. About the pointer operation, please refer to the attached technical notes.
The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the three cycle address input and
then serial data loading. The words other than those to be programmed do not need to be loaded.The Page Program confirm command(10h) initiates the programming process. Writing 10h alone without previously entering the serial data will not initiate the programming process. The internal write controller automatically executes the algorithms and timings necessary for program and verify,
thereby freeing the system controller for other tasks. Once the program process starts, the Read Status Register command may be
entered, with RE and CE low, to read the status register. The system controller can detect the completion of a program cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset command are valid
while programming is in progress. When the Page Program is complete, the Write Status Bit(I/O 0) may be checked(Figure 10). The
internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains in Read
Status command mode until another valid command is written to the command register.
Figure 10. Program Operation
tPROG
R/B
I/Ox
80h
Address & Data Input
10h
I/O0
70h
Pass
Fail
COPY-BACK PROGRAM
The copy-back program is configured to quickly and efficiently rewrite data stored in one page within the array to another page within
the same array without utilizing an external memory. Since the time-consuming sequently-reading and its re-loading cycles are
removed, the system performance is improved. The benefit is especially obvious when a portion of a block is updated and the rest of
the block also need to be copied to the newly assigned free block. The operation for performing a copy-back is a sequential execution
of page-read without burst-reading cycle and copying-program with the address of destination page. A normal read operation with
"00h" command with the address of the source page moves the whole 528bytes data into the internal buffer. As soon as the Flash
returns to Ready state, copy-back programming command "8Ah" may be given with three address cycles of target page followed. The
data stored in the internal buffer is then programmed directly into the memory cells of the destination page. Once the Copy-Back Program is finished, any additional partial page programming into the copied pages is prohibited before erase. Since the memory array is
internally partitioned into two different planes, copy-back program is allowed only within the same memory plane. Thus, A14, the
plane address, of source and destination page address must be the same."When there is a program-failure at Copy-Back operation, error is reported by pass/fail status. But if the soure page has a bit error for charge loss, accumulated copy-back
operations could also accumulate bit errors. For this reason, two bit ECC is recommended for copy-back operation."
Figure 11. Copy-Back Program Operation
tR
R/B
I/Ox
00h
Add.(3Cycles)
Source Address
tPROG
8Ah
Add.(3Cycles)
70h
I/O0
Destination Address
Fail
30
Pass
K9F5608R0D
K9F5608U0D K9F5608D0D
FLASH MEMORY
BLOCK ERASE
The Erase operation is done on a block basis. Block address loading is accomplished in two cycles initiated by an Erase Setup command(60h). Only address A14 to A24 is valid while A9 to A13 is ignored. The Erase Confirm command(D0h) following the block address
loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that memory
contents are not accidentally erased due to external noise conditions.
At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-verify. When the
erase operation is completed, the Write Status Bit(I/O 0) may be checked. Figure 12 details the sequence.
Figure 12. Block Erase Operation
tBERS
R/B
I/Ox
60h
Address Input(2Cycle)
I/O0
70h
D0h
Pass
Block Add. : A9 ~ A24
Fail
READ STATUS
The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether
the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs
the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows
the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE
does not need to be toggled for updated status. Refer to table 4 for specific Status Register definitions. The command register
remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read
cycle, a read command(00h or 50h) should be given before sequential page read cycle.
Table4. Read Status Register Definition
I/O #
Status
I/O 0
Program / Erase
Definition
"0" : Successful Program / Erase
"1" : Error in Program / Erase
I/O 1
I/O 2
I/O 3
"0"
"0"
Reserved for Future
Use
"0"
I/O 4
"0"
I/O 5
"0"
I/O 6
Device Operation
I/O 7
Write Protect
31
"0" : Busy
"1" : Ready
"0" : Protected
"1" : Not Protected
K9F5608R0D
K9F5608U0D K9F5608D0D
FLASH MEMORY
READ ID
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of
00h. Two read cycles sequentially output the manufacture code(ECh), and the device code respectively. The command register
remains in Read ID mode until further commands are issued to it. Figure 13 shows the operation sequence.
Figure 13. Read ID Operation
CLE
tCEA
CE
WE
tAR
ALE
RE
I/Ox
tWHR1
00h
90h
tREA
Address. 1cycle
ECh
Device
Code*
Maker code
Device code
Device
Device Code*
K9F5608R0D
35h
K9F5608D0D
75h
K9F5608U0D
75h
RESET
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random
read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no
longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and
the Status Register is cleared to value C0h when WP is high. Refer to table 5 for device status after reset operation. If the device is
already in reset state a new reset command will not be accepted by the command register. The R/B pin transitions to low for tRST
after the Reset command is written. Refer to Figure 14 below.
Figure 14. RESET Operation
tRST
R/B
I/Ox
FFh
Table5. Device Status
Operation Mode
After Power-up
After Reset
Read 1
Waiting for next command
32
K9F5608R0D
K9F5608U0D K9F5608D0D
FLASH MEMORY
READY/BUSY
The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random
read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command register or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin
is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. Because pull-up resistor value is related to tr(R/B)
and current drain during busy(ibusy) , an appropriate value can be obtained with the following reference chart(Fig 15). Its value can
be determined by the following guidance.
Rp
VCC
ibusy
1.8V device - VOL : 0.1V, VOH : VccQ-0.1V
2.65V device - VOL : 0.4V, VOH : VccQ-0.4V
3.3V device - VOL : 0.4V, VOH : 2.4V
Ready Vcc
R/B
open drain output
VOH
CL
VOL
Busy
tf
GND
Device
Figure 15. Rp vs tr ,tf & Rp vs ibusy
33
tr
K9F5608R0D
K9F5608U0D K9F5608D0D
FLASH MEMORY
Ibusy
300n
200n
3m
1.7
2m
0.85
tr
100n
30
90
60
1.7
0.57
1.7
1.7
2K
3K
Rp(ohm)
tf
1K
120
0.43
Ibusy [A]
tr,tf [s]
@ Vcc = 1.8V, Ta = 25°C , CL = 30pF
1m
1.7
4K
300n
2.3
3m
Ibusy
200n
100n
2m
1.1
tr
30
2.3
1K
2K
1m
0.75
2.3
2.3
tf
120
90
60
Ibusy [A]
tr,tf [s]
@ Vcc = 2.65V, Ta = 25°C , CL = 30pF
2.3
0.55
4K
3K
Rp(ohm)
@ Vcc = 3.3V, Ta = 25°C , CL = 100pF
tr,tf [s]
Ibusy
300n
200n
1.2
300
3m
200
0.8
2m
tr
100n
100
3.6
1K
0.6
3.6
3.6
3.6
2K
3K
Rp(ohm)
4K
tf
Rp value guidance
Rp(min, 1.8V part) =
Rp(min, 2.65V part) =
Rp(min, 3.3V part) =
1.85V
VCC(Max.) - VOL(Max.)
IOL + ΣIL
=
2.5V
VCC(Max.) - VOL(Max.)
IOL + ΣIL
=
3mA + ΣIL
3.2V
VCC(Max.) - VOL(Max.)
IOL + ΣIL
3mA + ΣIL
=
8mA + ΣIL
where IL is the sum of the input currents of all devices tied to the R/B pin.
Rp(max) is determined by maximum permissible limit of tr
34
1m
Ibusy [A]
400
2.4
K9F5608R0D
K9F5608U0D K9F5608D0D
FLASH MEMORY
Data Protection & Power up sequence
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector
disables all functions whenever Vcc is below about 1.1V(1.8V device), 1.8V(2.65V device), 2V(3.3V device). WP pin provides hardware protection and is recommended to be kept at VIL during power-up and power-down and recovery time of minimum 10µs is
required before internal circuit gets ready for any command sequences as shown in Figure 16. The two step command sequence for
program/erase provides additional software protection.
Figure 16. AC Waveforms for Power Transition
≈
1.8V device : ~ 1.5V
2.65V device : ~ 2.0V
3.3V device : ~ 2.5V
VCC
≈
High
≈
WP
10µs
≈
WE
35
1.8V device : ~ 1.5V
2.65V device : ~ 2.0V
3.3V device : ~ 2.5V