K9S5608V0C/B
K9S2808V0C/B
K9S6408V0C/B
SmartMediaTM
Document Title
SmartMediaTM Card
Revision History
Revision No
Draft Date
Remark
0.0
Initial issue
July 17th 2000
0.1
1. Explain how pointer operation works in detail.
2. Updated operation for tRST timing
- If reset command(FFh) is written at Ready state, the device goes
into Busy for maximum 5us.
Nov. 20th 2000
Advanced
Information
Preliminary
0.2
1. Renamed the 17th pin from Vcc to LVD(Low Voltage Detect)
-The LVD is used to electrically detect the proper supply voltage.
By connecting this pin to Vss through a pull-down resister, it is possible to distinguish 3.3V product from 5V product. When 3.3V is
applied as Vcc to pins 12 and 22, a ’High’level can be detected
on the system side if the device is a 3.3V product, and ’Low’level
for 5V product.
Mar. 2th 2001
Final
0.3
1.Powerup sequence is added
Recovery time of minimum 1µs is required before internal circuit gets
ready for any command sequences
Sep. 7th 2001
≈
History
~ 2.5V
~ 2.5V
High
≈
VCC
WP
1µs
WE
2. AC parameter tCLR(CLE to RE Delay, min 50ns) is added.
3. AC parameter tAR1 value : 100ns --> 20ns
Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site.
http://www.samsung.com/Products/Semiconductor/Flash/TechnicalInfo/datasheets.htm
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the
right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you
have any questions, please contact the SAMSUNG branch office near your office.
1
K9S5608V0C/B
K9S2808V0C/B
K9S6408V0C/B
SmartMediaTM
Revision History
Revision No
0.4
History
Draft Date
Remark
1. Unified access timing parameter definition for multiple operating modes
- Changed AC characteristics (Before)
Sep. 7th 2001
Final
Symbol
Min
Max
ALE to RE Delay (ID read)
tAR1
100
-
ALE to RE Delay (Read cycle)
tAR2
100
-
RE Low to Status Output
tRSTO
-
35
CE Low to Status Output
tCSTO
-
45
RE access time(Read ID)
tREADID
-
35
Parameter
Unit
ns
- AC characteristics (After)
. Deleted tRSTO, tCSTO and tREADID / Added tCLR, tCEA
Symbol
Min
Max
tAR1
50
-
ALE to RE Delay (Read cycle)
tAR2
50
-
CLE to RE Delay
tCLR
10
CE Access Time
tCEA
-
Parameter
ALE to RE Delay (ID read)
Unit
ns
45
CLE
tCR
CE
WE
tAR
ALE
RE
tREA
I/O0~7
90h
00h
ECh
Maker code
Address. 1cycle
CLE
tCEA
CE
WE
tAR
ALE
RE
tWHR
tREA
I/O0~7
90h
00h
ECh
Maker code
Address. 1cycle
Note : For more detailed features and specifications including FAQ, please refer to Samsung Flash web site.
http://www.samsung.com/Products/Semiconductor/Flash/TechnicalInfo/datasheets.htm
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the
right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you
have any questions, please contact the SAMSUNG branch office near your office.
2
K9S5608V0C/B
K9S2808V0C/B
K9S6408V0C/B
SmartMediaTM
Revision History
Revision No History
Draft Date
Remark
Feb. 9th 2002
Final
tCLS
CLE
tCLS
tCLH
tCS
CE
tWP
tCH
WE
tCSTO
tCHZ
tWHR
RE
tDS
I/O0~7
tDH
tRSTO
tIR
tRHZ
Status Output
70h
tCLS
CLE
tCLS
tCLH
tCS
CE
tWP
tCH
WE
tCEA
tCHZ
tWHR
RE
tDH
tDS
I/O0~7
0.5
tREA
tIR
tRHZ
Status Output
70h
1. Eliminated the duplicated AC parameter.
- AC characteristics (Before)
. Replaced tAR1,tAR2 with tAR
Parameter
ALE to RE Delay (ID read)
Symbol
Min
Max
tAR1
50
-
ALE to RE Delay (Read cycle)
tAR2
50
CLE to RE Delay
tCLR
10
CE Access Time
tCEA
-
45
Symbol
Min
Max
-
Unit
ns
- AC characteristics (After)
Parameter
ALE to RE Delay
tAR
10
CLE to RE Delay
tCLR
10
CE Access Time
tCEA
-
Unit
ns
45
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the
right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you
have any questions, please contact the SAMSUNG branch office near your office.
3
K9S5608V0C/B
K9S2808V0C/B
K9S6408V0C/B
SmartMediaTM
SmartMediaTM Card
FEATURES
GENERAL DESCRIPTION
•Single 2.7V~3.6V Supply
•Organization
- Memory Cell Array :
8MB(K9S6408V0X) : ( 8M + 256K)bit x 8bit
16MB(K9S2808V0X) : (16M + 512K)bit x 8bit
32MB(K9S5608V0X) : (32M + 1,024K)bit x 8bit
- Data Register : (512 + 16)bit x8bit
•Automatic Program and Erase
- Page Program : (512 + 16)Byte
- Block Erase
32MB, 16MB(K9S56/2808V0X) : (16K + 512)Byte
8MB (K9S6408V0X) : (8K + 256)Byte
•528-Byte Page Read Operation
- Random Access : 10µs(Max.)
* K9S6408V0B/A : 7µs(Max.)
* K9S6408V0C : 10µs(Max.)
- Serial Page Access : 50ns(Min.)
•Fast Write Cycle Time
- Program Time : 200µs(Typ.)
- Block Erase Time : 2ms(Typ.)
•Command/Address/Data Multiplexed I/O Port
•Hardware Data Protection
- Program/Erase Lockout During Power Transitions
•Reliable CMOS Floating-Gate Technology
- Endurance : 100K Program/Erase Cycles
* K9S6408V0X : 1Million Program/Erase Cycles
- Data Retention : 10 years
•Command Register Operation
Using Nand flash memory, SmartMedia provides the most costeffective solution for the solid state mass storage market. A program operation is implemented by the single page of 528 bytes
in typical 200µs and an erase operation is done by the single
block of 16K bytes (K9S6408V0X: 8K bytes) in typical 2ms.
Data in a page can be read out at 50ns cycle time per byte. The
I/O pins serve as ports for address and data inputs/outputs as
well as command inputs. The on-chip writing controller automates all program and erase functions including pulse repetition, where required, and internal verification and margining of
data. Even the write-intensive systems can take advantage of
the SmartMeida′s extended reliability of 100K program/erase
cycles by providing ECC(Error Correcting Code) with real time
mapping-out algorithm. (*Endurance varies according to its
density. please refer to Features). SmartMedia is an optimum
solution for data storage applications such as solid state file
storage, digital voice recorder, digital still camera and other portable applications requiring non-volatility.
PIN DESCRIPTION
•22pad SmartMediaTM(SSFDC)
•Unique ID for Copyright Protection
Device
Unique ID Support
K9S2808V0X
K9S5608V0X
K9S6408V0C
O
K9S6408V0A/M
X
PIN DESCRIPTION
SmartMediaTM CARD(SSFDC)
Pin Name
I/O0 ~ I/O7
Pin Function
Data Input/Outputs
CLE
Command Latch Enable
1
VSS
ALE
Address Latch Enable
21 CE
2
CLE
CE
Chip Enable
20 RE
3
ALE
19 R/B
4
WE
RE
Read Enable
5
WP
WE
Write Enable
6
I/O0
WP
Write Protect
7
I/O1
8
I/O2
22 VCC
12
22
18 GND
17 LVD
16 I/O7
15 I/O6
11
1
ID 32MB
Low Voltage Detect
Ground
14 I/O5
9
13 I/O4
10 VSS
R/B
Ready/Busy output
12 VCC
11 VSS
VCC
Power
VSS
Ground
N.C
No Connection
22 PAD
I/O3
LVD
GND
SmartMediaTM
NOTE : Connect all VCC and VSS pins of each device to common power supply outputs and do not leave VCC or VSS disconnected.
The pin 17(LVD) is used to detect 5V or 3.3V product electrically. Please, refer to the SmartMedia Application note for detail.
4
K9S5608V0C/B
K9S2808V0C/B
K9S6408V0C/B
SmartMediaTM
Figure 1. FUNCTIONAL BLOCK DIAGRAM
VCC
VSS
A22: K9S6408V0X
A23: K9S2808V0X
A24: K9S5608V0X
A9 - A24
A0 - A 7
K9S6408V0X : 64M + 2M Bit
K9S2808V0X : 128M + 4M Bit
K9S5608V0X : 256M + 8M Bit
X-Buffers
Latches
& Decoders
NAND Flash
ARRAY
Y-Buffers
Latches
& Decoders
K9S6408V0X : (512 + 16)Byte x 16,384
K9S2808V0X : (512 + 16)Byte x 32,768
K9S5608V0X : (512 + 16)Byte x 65,536
Page Register & S/A
A8
Y-Gating
Command
Command
Register
CE
RE
WE
VCC
VSS
I/O Buffers & Latches
Control Logic
& High Voltage
Generator
Global Buffers
CLE ALE WP
5
Output
Driver
I/0 0
I/0 7
K9S5608V0C/B
K9S2808V0C/B
K9S6408V0C/B
SmartMediaTM
Figure 2. ARRAY ORGANIZATION
Pages
(8MB) : 1block=16pages
(16MB/32MB) : 1block=32pages
1st half Page Register
2nd half Page Register
(=256 Bytes)
(=256 Bytes)
8 bit
512B Byte
16 Byte
I/O 0 ~ I/O 7
Page Register
512 Byte
16 Byte
ARRAY ORGANIZATION
1 Page
1 Block
1 Device
528 Byte
528 Bytes x 16 Pages
528 Byte x 16Pages x 1024 Blocks
K9S2808V0X
528Byte
528Bytes x 32 Pages
528Byte x 32Pages x 1024 Blocks
K9S5608V0X
528 Byte
528 Byte x 32 Pages
528Bytes x 32Pages x 2048 Blocks
K9S6408V0X
NOTE : Column Address : Starting Address of the Register.
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
1st Cycle
A0
A1
A2
A3
A4
A5
A6
A7
2nd Cycle
A9
A10
A11
A12
A13
A14
A15
A16
3rd Cycle
A17
A18
A19
A20
A21
A22
A23
A24
00h Command(Read) : Defines the starting address of the 1st half of the register.
01h Command(Read) : Defines the starting address of the 2nd half of the register.
A22: K9S6408V0X should be designated up to A22, addresse A23 to A24 must be set to "Low".
A23: K9S2808V0X should be designated up to A23, address A24 must be set to "Low".
A24: K9S5608V0X should be designated up to A24.
* A8 is set to "Low" or "High" by the 00h or 01h Command.
* The device ignores any additional input of address cycles than reguired.
6
Column Address
Row Address
(Page Address)
K9S5608V0C/B
K9S2808V0C/B
K9S6408V0C/B
SmartMediaTM
PRODUCT INTRODUCTION
The SmartMeida has the memory organization as following Table1. Spare sixteen columns are located from column address of 512
to 527. A 528-byte data register is connected to memory cell arrays and is accommodating data-transfer between the I/O buffers and
memory cell arrays during page read and page program operations. The memory array is made up of 16 cells that are serially connected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of the 32 pages formed by two 16
cell memory array. The array organization is shown in Figure 2. The program and the read operations are executed on a page basis,
while the erase operation is executed on a block basis.
The SmartMedia has addresses multiplexed into 8 I/O's. This scheme dramatically reduces pin counts and allows system upgrade to
future densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by
bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch
Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. All commands require one bus cycle except
for Block Erase and Page Program commands which require two cycles: one cycle for a setup and another for an execution. The
physical space of the SmartMedia varies according to its density and from 8MB to 32MB SmartMedia require three cycles for bytelevel addressing; column address, row address, in that order. Page Read and Page Program need the same three address cycles following the required command input. In Block Erase operation, however, only the two row address cycles are used. Device operations
are selected by writing specific commands into the command register. Table 2. defines the specific commands of the SmartMedia.
Table 1.MEMORY ORGANIZATION
Memory Organization
Number of rows(Pages)
Number of columns
K9S6408V0X
66Mbit (69,206,016 bit)
16,384 rows
528 columns
K9S2808V0X
132Mbit (138,412,032 bit)
32,768 rows
528 columns
K9S5608V0X
264Mbit (276,824,064 bit)
65,536 rows
528 columns
Table 2. COMMAND SETS
1st. Cycle
2nd. Cycle
Read 1
Function
00h/01h(1)
-
Read 2
50h
-
Read ID
90h
-
Reset
FFh
-
Page Program
80h
10h
Block Erase
60h
D0h
Read Status
70h
-
Acceptable Command during Busy
O
O
NOTE: 1. The 00h command defines starting address of the 1st half of registers.The 01h command defines starting address of the 2nd half of registers.
After data access on the 2nd half of register by the 01h command, address pointer is automatically moved to the 1st half register(00h) on the
next cycle.
Caution : Any undefined command inputs are prohibited except for above command sets of Table2.
7
K9S5608V0C/B
K9S2808V0C/B
K9S6408V0C/B
SmartMediaTM
PIN DESCRIPTION
Command Latch Enable(CLE)
The CLE input controls the path activation for commands sent to the command register. When active high, commands are latched
into the command register through the I/O ports on the rising edge of the WE signal.
Address Latch Enable(ALE)
The ALE input controls the activating path for address to the internal address registers. Addresses are latched on the rising edge of
WE with ALE high.
Chip Enable(CE)
The CE input is the device selection control. When CE goes high during a read operation the device is returned to standby mode.
However, when the device is in the busy state during program or erase, CE high is ignored and does not return the device to standby
mode.
Write Enable(WE)
The WE input controls writing to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse.
Read Enable(RE)
The RE input is the serial data-out control, and when active drives the data onto the I/O bus.
I/O Port : I/O 0 ~ I/O 7
The I/O pins are used to input command, address and data, and to output data during read operations. The I/O pins float to high-z
when the chip is deselected or when the outputs are disabled.
Write Protect(WP)
The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage generator is reset when
the WP pin is active low.
Ready/Busy(R/B)
The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is
in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip
is deselected or when outputs are disabled.
Low Voltage Detect(LVD)
The LVD is used to detect the proper supply voltage electrically. By connecting this pin to Vss through a pull-down resister, it is possible to distinguish 3.3V product from 5V product. When 3.3V is applied as Vcc to pins 12 and 22, a ’High’ level can be detected on
the system side if the device is a 3.3V product, and ’Low’level for 5V product.
8
K9S5608V0C/B
K9S2808V0C/B
K9S6408V0C/B
SmartMediaTM
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
VIN
-0.6 to + 4.6
VCC
-0.6 to + 4.6
Temperature Under Bias
TBIAS
-10 to +65
°C
Storage Temperature
TSTG
-20 to +65
°C
Voltage on any pin relative to VSS
Unit
V
NOTE :
1. Minimum DC voltage is -0.3V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns.
Maximum DC voltage on input/output pins is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.
2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions
as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltage reference to GND, TA=0 to 55°C)
Parameter
Symbol
Min
Typ.
Max
Unit
Supply Voltage
VCC
2.7
3.3
3.6
V
Supply Voltage
VSS
0
0
0
V
DC AND OPERATING CHARACTERISTICS(Recommended operating conditions otherwise noted.)
Parameter
Operating
Current
Symbol
Test Conditions
tRC=50ns, CE=VIL, IOUT=0mA
Min
Typ
Max
-
10
20
Sequential Read
ICC1
Program
ICC2
-
-
10
20
Erase
ICC3
-
-
10
20
Unit
mA
Stand-by Current(TTL)
ISB1
CE=VIH, WP=0V/VCC
-
-
1
Stand-by Current(CMOS)
ISB2
CE=VCC-0.2, WP=0V/VCC
-
10
50
Input Leakage Current
ILI
VIN=0 to 3.6V
-
-
±10
Output Leakage Current
ILO
VOUT=0 to 3.6V
-
-
±10
Input High Voltage, All inputs
VIH
-
2.0
-
VCC+0.3
Input Low Voltage, All inputs
VIL
-
-0.3
-
0.8
Output High Voltage Level
VOH
IOH=-400µA
2.4
-
-
Output Low Voltage Level
VOL
IOL=2.1mA
-
-
0.4
Output Low Current(R/B)
IOL(R/B)
VOL=0.4V
8
10
-
9
µA
V
mA
K9S5608V0C/B
K9S2808V0C/B
K9S6408V0C/B
SmartMediaTM
VALID BLOCK
Parameter
Symbol
K9S6408V0X
Valid Block Number
NVB
K9S2808V0X
K9S5608V0X
Min
Typ.
Max
1,014
1,020
1,024
1,004
-
1,024
2013
-
2048
Unit
Blocks
NOTE :
1. The K9SXX08V0X may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid
blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not
erase or program factory-marked bad blocks. Refer to the attached technical notes for an appropriate management of invalid blocks.
2. Per the specification of the physical format version 1.2 by SSFDC forum, minimum 1,000 vaild blocks are guaranteed for each 16MB memory space.
(Refer to the attached technical notes)
AC TEST CONDITION
(TA=0 to 55°C, VCC=2.7V~3.6V unless otherwise noted)
Parameter
Value
Input Pulse Levels
0.4V to 2.4V
Input Rise and Fall Times
5ns
Input and Output Timing Levels
1.5V
Output Load (3.0V +/-10%)
1 TTL GATE and CL=50pF
Output Load (3.3V +/-10%)
1 TTL GATE and CL=100pF
CAPACITANCE(TA=25°C, VCC=3.3V, f=1.0MHz)
Symbol
Test Condition
Min
Max
Unit
Input/Output Capacitance
Item
CI/O
VIL=0V
-
10
pF
Input Capacitance
CIN
VIN=0V
-
10
pF
NOTE : Capacitance is periodically sampled and not 100% tested.
MODE SELECTION
CLE
ALE
CE
RE
WP
H
L
L
WE
H
X
Mode
L
H
L
H
X
Address Input(3clock)
H
L
L
H
H
Command Input
L
H
L
H
H
L
L
L
H
H
Data Input
L
L
L
H
X
sequential Read & Data Output
X
X
L
X
X
X
During Read(Busy)
X
X
X
X
X
H
During Program(Busy)
X
X
X
X
X
H
During Erase(Busy)
X
X(1)
X
X
X
L
X
X
H
X
X
0V/VCC(2)
Read Mode
Write Mode
Command Input
Address Input(3clock)
Write Protect
Stand-by
NOTE : 1. X can be VIL or VIH.
2. WP should be biased to CMOS high or CMOS low for standby.
Program/Erase Characteristics
Parameter
Program Time
Number of Partial Program Cycles
in the Same Page
Block Erase Time
Main Array
Spare Array
Symbol
Min
Typ
Max
tPROG
-
200
500
µs
2
cycles
3
cycles
3
ms
Nop
-
-
tBERS
-
2
10
Unit
K9S5608V0C/B
K9S2808V0C/B
K9S6408V0C/B
SmartMediaTM
AC Timing Characteristics for Command / Address / Data Input
Parameter
Symbol
Min
Max
Unit
CLE setup Time
tCLS
0
-
ns
CLE Hold Time
tCLH
10
-
ns
CE setup Time
tCS
0
-
ns
CE Hold Time
tCH
10
-
ns
WE Pulse Width
tWP
25
-
ns
ALE setup Time
tALS
0
-
ns
ALE Hold Time
tALH
10
-
ns
Data setup Time
tDS
20
-
ns
(1)
Data Hold Time
tDH
10
-
ns
Write Cycle Time
tWC
50
-
ns
WE High Hold Time
tWH
15
-
ns
NOTE : 1. If tCS is set less than 10ns, tWP must be minimum 35ns, otherwise, tWP may be minimum 25ns.
AC Characteristics for Operation
Parameter
Symbol
Min
Max
Unit
tR
-
10
µs
Data Transfer from Cell to Register
CLE to RE Delay
tCLR
10
-
ns
ALE to RE Delay
tAR
10
-
ns
Ready to RE Low
tRR
20
-
ns
RE Pulse Width
tRP
30
-
ns
WE High to Busy
tWB
-
100
ns
Read Cycle Time
tRC
50
-
ns
RE Access Time
tREA
-
35
ns
RE High to Output Hi-Z
tRHZ
15
30
ns
CE High to Output Hi-Z
tCHZ
-
20
ns
RE High Hold Time
tREH
15
-
ns
Output Hi-Z to RE Low
tIR
0
-
ns
Last RE High to Busy (at sequential read)
tRB
-
100
ns
CE High to Ready (in case of interception by CE at read)
tCRY
-
50 +tr(R/B)(1)
ns
CE High Hold Time(at the last serial read)
tCEH
100
-
ns
WE High to RE Low
tWHR
60
-
(2)
Device Resetting Time(Read/Program/Erase)
tRST
-
NOTE : 1. The time to Ready depends on the value of the pull-up resistor tied R/B pin.
2. To break the sequential read cycle, CE must be held high for longer time than tCEH.
3. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5us.
11
5/10/500
ns
(3)
µs
K9S5608V0C/B
K9S2808V0C/B
K9S6408V0C/B
SmartMediaTM
SmartMedia Technical Notes
Invalid Block(s)
Invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by Samsung. The information regarding the invalid block(s) is so called as the invalid block information. An invalid block(s) does not affect the performance
of valid block(s) because it is isolated from the bit line and the common source line by a select transistor. The system design must be
able to mask out the invalid block(s) via address mapping.
Identifying Invalid Block(s)
SSFDC Forum specifies the logical format and physical format to ensure compatibility of SmartMedia. Samsung pre-formats SmartMedia in the Forum-compliant format prior to shipping. The physical format standard by SSFDC Forum specifies that invalid block
information is written at the 6th byte of spare area in invalid blocks with two or more "0" bits, while valid blocks are erased(FFh). Since
the invalid block information is also erasable in most cases, it is impossible to recover the information once it has been erased. Therefore, the system must be able to recognize the invalid block(s) based on the original invalid block information and create the invalid
block table via the following suggested flow chart(Figure 3). Any intentional erasure of the original invalid block information is prohibited.
Start
Set Block Address = 0
Increment Block Address
Create (or update)
Invalid Block(s) Table
No
Check "FFh" ?
*
Check "FFh" at the column address 517
of the first page in the block
Yes
No
Last Block ?
Yes
End
Figure 3. Flow chart to create invalid block table.
12
K9S5608V0C/B
K9S2808V0C/B
K9S6408V0C/B
SmartMediaTM
SmartMedia Technical Notes (Continued)
Error in write or read operation
Over its life time, the additional invalid blocks may be developed during its use. Refer to the qualification report for the actual data.The
following possible failure modes should be considered to implement a highly reliable system. In the case of status read failure after
erase or program, block replacement should be done. Because program status failure during a page program does not affect the data
of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased empty block
and reprogramming the current target data and copying the rest data of the replaced block. To improve the efficiency of memory
space, it is recommended that the read or verification failure due to single bit error be reclaimed by ECC without any block replacement. The said additional block failure rate does not include those reclaimed blocks.
Failure Mode
Write
Read
ECC
Detection and Countermeasure sequence
Erase Failure
Status Read after Erase --> Block Replacement
Program Failure
Status Read after Program --> Block Replacement
Read back ( Verify after Program) --> Block Replacement
or ECC Correction
Single Bit Failure
Verify ECC -> ECC Correction
: Error Correcting Code --> Hamming Code etc.
Example) 1bit correction & 2bit detection
Program Flow Chart
If ECC is used, this verification
operation is not needed.
Start
Write 00h
Write 80h
Write Address
Write Address
Wait for tR Time
Write Data
Write 10h
Verify Data
Read Status Register
No
*
Program Error
Yes
Program Completed
I/O 6 = 1 ?
or R/B = 1 ?
*
Program Error
Yes
No
No
*
I/O 0 = 0 ?
Yes
13
: If program operation results in an error, map out
the block including the page in error and copy the
target data to another block.
K9S5608V0C/B
K9S2808V0C/B
K9S6408V0C/B
SmartMediaTM
SmartMedia Technical Notes (Continued)
Erase Flow Chart
Read Flow Chart
Start
Start
Write 60h
Write 00h
Write Block Address
Write Address
Write D0h
Read Data
Read Status Register
ECC Generation
No
I/O 6 = 1 ?
or R/B = 1 ?
Reclaim the Error
No
Verify ECC
Yes
Yes
*
No
Erase Error
Page Read Completed
I/O 0 = 0 ?
Yes
Erase Completed
*
: If erase operation results in an error, map out
the failing block and replace it with another block.
Block Replacement
1st
∼
(n-1)th
{
nth
Block A
2
an error occurs.
(page)
1st
∼
(n-1)th
nth
Buffer memory of the controller.
{
Block B
1
(page)
* Step1
When an error happens in the nth page of the Block ’A’during the program operation.
* Step2
Copy the nth page data of the Block ’A’in the buffer memory to the nth page of another free block. (Block ’B’)
* Step3
Then, copy the data in the 1st ~ (n-1)th page of the Block ’A’to the same location of the Block ’B’.
* Step4
Do not erase or program to Block ’A’by creating an ’invalid Block’table or using other appropriate scheme.
14
K9S5608V0C/B
K9S2808V0C/B
K9S6408V0C/B
SmartMediaTM
Pointer Operation of the SmartMedia
Samsung NAND Flash has three address pointer commands as a substitute for the two most significant column addresses. ’00h’
command sets the pointer to ’A’area(0~255byte), ’01h’command sets the pointer to ’B’area(256~511byte), and ’50h’command sets
the pointer to ’C’ area(512~527byte). With these commands, the starting column address can be set to any of a whole
page(0~527byte). ’00h’or ’50h’is sustained until another address pointer command is inputted. ’01h’command, however, is effective
only for one operation. After any operation of Read, Program, Erase, Reset, Power_Up is executed once with ’01h’ command, the
address pointer returns to ’A’ area by itself. To program data starting from ’A’ or ’C’ area, ’00h’ or ’50h’ command must be inputted
before ’80h’command is written. A complete read operation prior to ’80h’command is not necessary. To program data starting from
’B’area, ’01h’command must be inputted right before ’80h’command is written.
Destination of the pointer
Command
Pointer position
Area
00h
01h
50h
0 ~ 255 byte
256 ~ 511 byte
512 ~ 527 byte
1st half array(A)
2nd half array(B)
spare array(C)
"A" area
(00h plane)
"B" area
(01h plane)
256 Byte
256 Byte
"A"
"B"
"C" area
(50h plane)
16 Byte
"C"
Internal
Page Register
Pointer select
commnad
(00h, 01h, 50h)
Pointer
Figure 4. Block Diagram of Pointer Operation
(1) Command input sequence for programming ’A’ area
The address pointer is set to ’A’area(0~255), and sustained
Address / Data input
00h
80h
Address / Data input
10h
00h
’A’,’B’,’C’area can be programmed.
It depends on how many data are inputted.
80h
10h
’00h’command can be omitted.
(2) Command input sequence for programming ’B’ area
The address pointer is set to ’B’area(256~512), and will be reset to
’A’area after every program operation is executed.
Address / Data input
01h
80h
Address / Data input
10h
01h
’B’, ’C’area can be programmed.
It depends on how many data are inputted.
80h
10h
’01h’command must be rewritten before
every program operation
(3) Command input sequence for programming ’C’ area
The address pointer is set to ’C’area(512~527), and sustained
Address / Data input
50h
80h
Address / Data input
10h
50h
Only ’C’area can be programmed.
80h
’50h’command can be omitted.
15
10h
K9S5608V0C/B
K9S2808V0C/B
K9S6408V0C/B
SmartMediaTM
System Interface Using CE don’t-care.
For an easier system interface, CE may be inactive during the data-loading or sequential read as shown below. The internal 528byte
page registers are utilized as separate buffers for this operation and the system design gets more flexible. In addition, for voice or
audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and reading would
provide significant savings in power consumption.
Figure 5. Program Operation with CE don’t-care.
CLE
CE don’t-care
≈
≈
CE
WE
ALE
I/O0~7
80h
Start Add.(3Cycle)
Data Input
(Min. 10ns)
Data Input
10h
(Max. 45ns)
tCS
tCH
tCEA
CE
CE
tREA
RE
tWP
WE
I/O0~7
out
Figure 6. Read Operation with CE don’t-care.
CLE
CE don’t-care
Must be held
low during tR.
≈
CE
RE
ALE
tR
R/B
WE
I/O0~7
00h
Start Add.(3Cycle)
Data output (Sequential)
16
K9S5608V0C/B
K9S2808V0C/B
K9S6408V0C/B
SmartMediaTM
Command Latch Cycle
CLE
tCLS
tCLH
tCS
tCH
CE
tWP
WE
tALS
tALH
ALE
tDH
tDS
Command
I/O0~7
Address Latch Cycle
tCLS
CLE
tWC
tCS
tWC
CE
tWP
tWP
tWP
WE
tWH
tALH tALS
tWH
tALH tALS
tALS
tALH
ALE
tDS
I/O0~7
tDH
tDS
tDH
A9~A16
A0~A7
tDS
A17~A24
A22: K9S6408V0X
A23: K9S2808V0X
A24: K9S5608V0X
17
tDH
K9S5608V0C/B
K9S2808V0C/B
K9S6408V0C/B
SmartMediaTM
Input Data Latch Cycle
tCLH
CLE
tCH
CE
tWC
tALS
tWP
≈
ALE
tWP
tWP
WE
tWH
tDH
tDS
tDH
tDS
tDH
≈
tDS
I/O0~7
DIN 511
DIN 1
≈
DIN 0
Serial Access Cycle after Read(CLE=L, WE=H, ALE=L)
tRC
≈
CE
tREH
RE
tREA
≈
tREA
tRP
tCHZ
tREA
tRHZ
Dout
I/O0~7
Dout
≈
tRHZ
Dout
≈
tRR
R/B
NOTES : Transition is measured ±200mV from steady state voltage with load.
This parameter is sampled and not 100% tested.
18
K9S5608V0C/B
K9S2808V0C/B
K9S6408V0C/B
SmartMediaTM
Status Read Cycle
tCLR
CLE
tCLS
tCLH
tCS
CE
tCH
tWP
WE
tCEA
tCHZ
tWHR
RE
tDS
I/O0~7
tDH
tIR
tREA
tRHZ
Status Output
70h
READ1 OPERATION(READ ONE PAGE)
CLE
tCEH
CE
tCHZ
tWC
WE
tWB
tCRY
tAR
ALE
tR
tRHZ
tRC
≈
RE
I/O0~7
00h or 01h A0 ~ A7
A9 ~ A16
Column
Address
R/B
A17 ~ A24
Dout N
Page(Row)
Address
A22: K9S6408V0X
A23: K9S2808V0X
A24: K9S5608V0X
Busy
19
Dout N+1
Dout N+2
Dout N+3
≈ ≈
tRR
Dout 527
tRB
K9S5608V0C/B
K9S2808V0C/B
K9S6408V0C/B
SmartMediaTM
READ1 OPERATION(INTERCEPTED BY CE)
CLE
CE
WE
tWB
tCHZ
tAR
ALE
tRC
tR
RE
tRR
I/O0~7
00h or 01h
A9 ~ A16
A0 ~ A7
A17 ~ A24
A22: K9S6408V0X
A23: K9S2808V0X
A24: K9S5608V0X
R/B
Dout N
Dout N+1
Dout N+2
Dout N+3
Page(Row)
Address
Column
Address
Busy
READ2 OPERATION(READ ONE PAGE)
CLE
CE
WE
tR
tWB
tAR
ALE
≈
tRR
I/O0~7
50H
A0 ~ A7
R/B
M Address
Dout
511+M
A9 ~ A16 A17 ~ A24
A22: K9S6408V0X
A23: K9S2808V0X
A24: K9S5608V0X
Dout
511+M+1
≈
RE
Dout 527
Selected
Row
A0~A3 : Valid Address
A4~A7 : Don′t care
512
16
Start
address M
20
K9S5608V0C/B
K9S2808V0C/B
K9S6408V0C/B
SmartMediaTM
SEQUENTIAL ROW READ OPERATION (Within a block especially for 64Mb-Cdie and 128Mb Bdie)
CLE
CE
WE
≈
≈
ALE
RE
Dout
N+1
Dout
N+2
≈
Ready
Dout
0
Dout
527
Dout
2
Dout
527
Busy
Busy
R/B
Dout
1
≈
Dout
N
A0 ~ A7 A9 ~ A16 A17 ~ A24
≈
00h
≈
I/O0~7
A22: K9S6408V0X
A23: K9S2808V0X
A24: K9S5608V0X
M
M+1
N
Output
Output
PAGE PROGRAM OPERATION
CLE
CE
tWC
tWC
tWC
WE
tWB
tPROG
ALE
I/O0~7
80h
A0 ~ A7 A9 ~ A16 A17 ~ A24
Sequential Data Column
Input Command Address
Page(Row)
Address
≈ ≈
A22: K9S6408V0X
A23: K9S2808V0X
A24: K9S5608V0X
RE
Din
Din
Din
10h
527
N
N+1
Program
1 up to 528 Byte Data
Command
Serial Input
≈
R/B
70h
21
I/O0
Read Status
Command
I/O0=0 Successful Program
I/O0=1 Error in Program
K9S5608V0C/B
K9S2808V0C/B
K9S6408V0C/B
SmartMediaTM
BLOCK ERASE OPERATION (ERASE ONE BLOCK)
CLE
CE
tWC
WE
tBERS
tWB
ALE
RE
I/O0~7
A22: K9S6408V0X
A23: K9S2808V0X
A24: K9S5608V0X
60h
A9 ~ A16 A17 ~ A24
DOh
70h
I/O 0
Busy
R/B
Auto Block Erase
Setup Command
Erase Command
≈
Page(Row)
Address
Read Status
Command
22
I/O0=0 Successful Erase
I/O0=1 Error in Erase
K9S5608V0C/B
K9S2808V0C/B
K9S6408V0C/B
SmartMediaTM
MANUFACTURE & DEVICE ID READ OPERATION
tCLR
CLE
CE
WE
tAR
ALE
RE
tREA
90h
I/O 0 ~ 7
Read ID Command
00h
1st
2nd
ECh
75h
Maker Code
Address. 1cycle
Device Code
3rd
A5
UniqueID Code
K9S6408V0X : E6h
K9S2808V0X : 73h
K9S5608V0X : 75h
NOTE :
The 3rd byte of device IDs represents whether there is Unigue ID or not. If A5h is read out, that means that the Smart Media has the Unigue ID.
ID Definition Table
90 ID : Access command = 90H
READ ID (1)
st
1 Byte
2nd Byte
3rd Byte
Value
Description
ECh
*75h
A5h
Maker Code
Device Code
Unique1D code
NOTE :
*Device Code : K9S6408V0X : E6h , K9S2808V0X : 73h , K9S5608V0X: 75h
23
K9S5608V0C/B
K9S2808V0C/B
K9S6408V0C/B
SmartMediaTM
DEVICE OPERATION
PAGE READ
Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00h to the command register along with three address cycles. Once the command is latched, it does not need to be written for the following page read operation. Three types of operations are available : random read, sequential read and sequential row read.
The random read mode is enabled when the page address is changed. The 528 bytes of data within the selected page are transferred
to the data registers in less than 10µs(tR). The system controller can detect the completion of this data transfer(tR) by monitoringing
the output of R/B pin. Once the data in a page is loaded into the registers, they may be read out in 50ns cycle time by pulsing RE
sequentially. High to low transitions of the RE clock output the data starting from the selected column address up to the last column
address.
After the data of the last column address is clocked out, the next page is automatically selected for sequential row read.
Waiting 10µs again allows reading the selected page. The sequential row read operation is terminated by bringing CE high. The way
the Read1 and Read2 commands work is like a pointer set to either the main area or the spare area. The spare area of bytes 512 to
527 may be selectively accessed by writing the Read2 command. Addresses A0 to A3 set the starting address of the spare area while
addresses A4 to A7 are ignored. Unless the operation is aborted, the page address is automatically incremented for sequential row
read as in Read1 operation and spare sixteen bytes of each page may be sequentially read. The Read1 command(00h/01h) is
needed to move the pointer back to the main area. Figures 7 through 10 show typical sequence and timings for each read operation.
Figure 7. Read1 Operation
CLE
CE
WE
ALE
tR
R/B
RE
I/O0~7
00h
Start Add.(3Cycle)
A0 ~ A7 & A9 ~ A24
Data Output (Serial Access)
A22: K9S6408V0X
A23: K9S2808V0X
A24: K9S5608V0X
(00h Command)
1st half array
(01h Command)*
2st half array
Data Field
Spare Field
1st half array
2st half array
Data Field
Spare Field
* After data access on 2nd half array by 01h command, the start pointer is automatically moved to 1st half
array (00h) at next cycle.
24
K9S5608V0C/B
K9S2808V0C/B
K9S6408V0C/B
SmartMediaTM
Figure 8. Read2 Operation
CLE
CE
WE
ALE
tR
R/B
RE
50h
I/O0~7
Start Add.(3Cycle)
A0 ~ A3 & A9 ~ A24
(A4 ~ A7 :
Don′t Care)
Data Output(Serial Access)
A22: K9S6408V0X
A23: K9S2808V0X
A24: K9S5608V0X
1st half array
Spare Field
2nd half array
Data Field
Spare Field
I/O0 ~ 7
tR
tR
R/B
00h
01h
≈
Figure 9. Sequential Row Read1 Operation
Start Add.(3Cycle)
Data Output
Data Output
Data Output
1st
2nd
(528 Byte)
Nth
(528 Byte)
A0 ~ A7 & A9 ~ A24
(01h Command)
(00h Command)
1st half array
1st half array
2nd half array
1st
2nd
Nth
Data Field
tR
2nd half array
1st
2nd
Nth
Block
Data Field
Spare Field
Spare Field
The Sequential Read 1 and Read 2 operations are allowed only within a block and after the last page of a block
is readout, the sequential read operation must be terminated by bringing CE high. When the page address
moves onto the next block, read command and address must be given.
25
K9S5608V0C/B
K9S2808V0C/B
K9S6408V0C/B
SmartMediaTM
I/O0~7
tR
tR
R/B
Start Add.(3Cycle)
50h
A0 ~ A3 & A9 ~ A24
(A4 ~ A7 :
Don′t Care)
≈
Figure 10. Sequential Row Read2 Operation
tR
Data Output
Data Output
Data Output
1st
2nd
(16Byte)
Nth
(16Byte)
A22: K9S6408V0X
A23: K9S2808V0X
A24: K9S5608V0X
1st
Block
Nth
Data Field
Spare Field
PAGE PROGRAM
The device is programmed basically on a page basis, however it does allow multiple partial page programing of a byte or consecutive
bytes up to 528, in a single page program cycle. The number of consecutive partial page programming operation within the same
page without an intervening erase operation has the limit by its density. (See the Table of Program/Erase Characteristics) It is advisable not to program more often than recommend. It might cause failures due to disturbance when it exceeds its limits. The failure
mode could be that data "1" of the erased cell might be changed into data"0"of the programmed cell.
The addressing may be done in any random order in a block. A page program cycle consists of a serial data loading period in which
up to 528 bytes of data may be loaded into the page register, followed by a non-volatile programming period where the loaded data is
programmed into the appropriate cell. Serial data loading can be started from the 2nd half array by moving pointer. About the pointer
operation, please refer to the attached technical notes.The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the three cycle address input and then serial data loading. The bytes other than those to be programmed do
not need to be loaded.The Page Program confirm command(10h) initiates the programming process. Writing 10h alone without previously entering the serial data will not initiate the programming process. The internal write-controller automatically executes the algorithms and timings necessary for program and verify, thereby freeing the system controller for other tasks. Once the program process
starts, the Read Status Register command may be entered, with RE and CE low, to read the status register. The system controller
can detect the completion of a program cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only the
Read Status command and Reset command are valid while programming is in progress. When the Page Program is completed, the
Write Status Bit(I/O 0) may be checked(Figure 11). The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains in Read Status command mode until another valid command is written to the command register.
Figure 11. Program & Read Status Operation
tPROG
R/B
I/O0~7
80h
Address & Data Input
A0 ~ A7 & A9 ~ A24
528 Byte Data
10h
70h
A22: K9S6408V0X
A23: K9S2808V0X
A24: K9S5608V0X
I/O0
Fail
26
Pass
K9S5608V0C/B
K9S2808V0C/B
K9S6408V0C/B
SmartMediaTM
BLOCK ERASE
The Erase operation is done on a block(16K Byte) basis. Block address loading is accomplished in two cycles initiated by an Erase
Setup command(60h). Only address A14 to (A22: K9S6408V0X, A23: K9S2808V0X, A24: K9S5608V0X) is valid while A9 to A13 is
ignored. The Erase Confirm command(D0h) following the block address loading initiates the internal erasing process. This two-step
sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external noise
conditions.
At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-verify. When
the erase operation is completed, the Write Status Bit(I/O 0) may be checked. Figure 12 details the sequence.
Figure 12. Block Erase Operation
tBERS
R/B
I/O0~7
60h
Address Input(2Cycle)
Block Add. : A9 ~ A24
I/O0
70h
D0h
A22: K9S6408V0X
A23: K9S2808V0X
A24: K9S5608V0X
Pass
Fail
READ STATUS
The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether
the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs
the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows
the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE
does not need to be toggled for updated status. Refer to Table3 for specific Status Register definitions. The command register
remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read
mode, a read command(00h or 50h) should be given before the sequential read cycle.
Read Status Register Definition
I/O #
Status
I/O 0
Program / Erase
Definition
"0" : Successful Program / Erase
"1" : Error in Program / Erase
"0"
I/O 1
I/O 2
I/O 3
"0"
Reserved for Future
Use
"0"
I/O 4
"0"
I/O 5
"0"
I/O 6
Device Operation
I/O 7
Write Protect
27
"0" : Busy
"1" : Ready
"0" : Protected
"1" : Not Protected
K9S5608V0C/B
K9S2808V0C/B
K9S6408V0C/B
SmartMediaTM
READ ID
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of
00h. Three read cycles sequentially output the manufacture code(ECH), the device code (K9S6408V0X : E6h , K9S2808V0X : 73h ,
K9S5608V0X: 75h), the UniqueID code(A5h) respectively. The command register remains in Read ID mode until further commands are
issued to it. Figure 13 shows the operation sequence.
Figure 13. Read ID Operation
tCLR
CLE
tCEA
CE
WE
tAR
ALE
RE
tWHR
I/O0~7
90h
tREA
00h
ECh
Address. 1cycle
Maker code
75h
A5h
UniqueID code
Device code
K9S6408V0X : E6h
K9S2808V0X : 73h
K9S5608V0X : 75h
RESET
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random
read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no
longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and
the Status Register is cleared to value C0h when WP is high. Refer to Table 4 for device status after reset operation. If the device is
already in reset state a new reset command will not be accepted by the command register. The R/B pin transitions to low for tRST
after the Reset command is written. Reset command is not necessary for normal operation. Refer to Figure 14 below.
Figure 14. RESET Operation
tRST
R/B
I/O0~7
FFh
Table 4. Device Status
Operation Mode
After Power-up
After Reset
Read 1
Waiting for next command
28
K9S5608V0C/B
K9S2808V0C/B
K9S6408V0C/B
SmartMediaTM
READY/BUSY
The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random
read operations. The R/B pin is normally high but transitions to low after program or erase command is written to the command register or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin is
an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. Because pull-up resistor value is related to tr(R/B) and
current drain during busy(ibusy) , an appropriate value can be obtained with the following reference chart(Figure 15). Its value can be
determined by the following guidance.
Rp
VCC
ibusy
Ready Vcc
R/B
open drain output
2.0V
0.8V
Busy
tf
tr
GND
Device
Figure 15. Rp vs tr ,tf & Rp vs ibusy
@ Vcc = 3.3V, Ta = 25°C , CL = 100pF
tr,tf [s]
Ibusy
300n
200n
290
3m
1.65
189
1.1
2m
tr
100n
96
4.2
0.825
tf
1K
4.2
4.2
4.2
2K
3K
Rp(ohm)
4K
Rp value guidance
Rp(min) =
3.2V
VCC(Max.) - VOL(Max.)
IOL + ΣIL
=
8mA + ΣIL
where IL is the sum of the input currents of all devices tied to the R/B pin.
Rp(max) is determined by maximum permissible limit of tr
29
1m
Ibusy [A]
381
3.3
K9S5608V0C/B
K9S2808V0C/B
K9S6408V0C/B
SmartMediaTM
Data Protection & Power up Sequence
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector
disables all functions whenever Vcc is below about 2V. WP pin provides hardware protection and is recommended to be kept at VIL
during power-up and power-down as shown in Figure 16. The two step command sequence for program/erase provides additional
software protection.
≈
Figure 16. AC Waveforms for Power Transition
~ 2.5V
VCC
≈
High
WP
WE
1µs
30
~ 2.5V
SmartMediaTM
SmartMedia Dimensions
Unit:mm
DIMENSIONS
22 PAD SOLID STATE FLOPPY DISK CARD (3.3V)
SOLID STATE PRODUCT OUTLINE
37.0±0.1
0.15±0.05
5.0±0.2
Index Label Area
10.0±0.2
Write Protect Area
Contact Area
(+0.1mm package body surface)
33.0±0.2
22.1(Max)
27.5
45.0±0.1
4.5(Min)
0
5.
0.5mm Chamfer 4.2(Min)
(3.3V Card)
0.76±0.08
1.5±0.1
27.0
0.000
2.540
5.080
7.620
10.160
12.700
2.140 TYP
0.400 TYP
22
12
I/O5
I/O6
I/O7
LVD
GND
R/B
RE
CE
vcc
I/O3
I/O2
I/O1
I/O0
WP
WE
ALE
CLE
vSS
I/O4
vcc
8.650
7.900
6.500
0.000
vSS
6.500
7.900
8.650
1
11
12.700
10.160
7.620
5.080
2.540
0.000
31