M76DW63000A M76DW62000A 64Mbit (x8/ x16, Multiple Bank, Boot Block) Flash Memory and 8Mbit/4Mbit SRAM, 3V Supply, Multiple Memory Product PRELIMINARY DATA FEATURES SUMMARY ■ MULTIPLE MEMORY PRODUCT – 64 Mbit (8Mb x8 or 4Mb x16), Multiple Bank, Page, Boot Block, Flash Memory – SRAM: 8Mbit (512K x 16) for M76DW63000A, or 4Mbit (256K x 16) for M76DW62000A ■ SUPPLY VOLTAGE – VCCF = VCCS = 2.7V to 3.3V ■ – VPPF = 12V for Fast Program (optional) ACCESS TIME: 70, 90ns ■ LOW POWER CONSUMPTION ■ ELECTRONIC SIGNATURE – Manufacturer Code: 0020h Figure 1. Package FBGA LFBGA73 (ZA) 8 x 11.6mm – Device Code: 227Eh + 2202h + 2201h FLASH MEMORY ■ ASYNCHRONOUS PAGE READ MODE – Page Width: 4 Words – Page Access: 25, 30ns – Random Access: 70, 90ns ■ PROGRAMMING TIME – 10µs per Byte/Word typical ■ VPP/WP PIN for FAST PROGRAM and WRITE PROTECT ■ TEMPORARY BLOCK UNPROTECTION MODE ■ COMMON FLASH INTERFACE – 4 Words/ 8 Bytes at-a-time Program ■ MEMORY BLOCKS – Quadruple Bank Memory Array: 8Mbits + 24Mbits + 24Mbits + 8Mbits – Parameter Blocks (at both Top and Bottom) ■ ■ DUAL OPERATIONS – While Program or Erase in a group of banks (from 1 to 3), Read in any of the other banks PROGRAM/ERASE SUSPEND and RESUME MODES – Read from any Block during Program Suspend – Read and Program another Block during Erase Suspend ■ – 64 bit Security Code ■ EXTENDED MEMORY BLOCK – Extra block used as security block or to store additional information ■ 100,000 PROGRAM/ERASE CYCLES per BLOCK SRAM ■ 8Mbit (512K x 16) or 4Mbit (256K x 16) ■ ACCESS TIME: 70ns ■ LOW VCCS DATA RETENTION: 1.5V ■ POWER DOWN FEATURES USING TWO CHIP ENABLE INPUTS UNLOCK BYPASS PROGRAM COMMAND – Faster Production/Batch Programming September 2003 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 1/27 M76DW63000A, M76DW62000A TABLE OF CONTENTS SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 3. LFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Address Inputs (A0-A21). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Data Inputs/Outputs (DQ8-DQ14). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Data Input/Output or Address Input (DQ15A–1).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Flash Chip Enable (EF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 VPP/Write Protect (VPP/WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Reset/Block Temporary Unprotect (RPF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Ready/Busy Output (RB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Byte/Word Organization Select (BYTE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 SRAM Chip Enable (E1S, E2S). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 SRAM Upper Byte Enable (UBS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 SRAM Lower Byte Enable (LBS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 VCCF Supply Voltage (2.7V to 3.3V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 VCCS Supply Voltage (2.7V to 3.3V).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 VSS Ground.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 4. Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 2. Main Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 3. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 4. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 5. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 6. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 5. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 6. Flash Memory DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 7. SRAM DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 7. Stacked LFBGA73 8x11.6mm, 10x12 array, 0.8mm pitch, Bottom View Package Outline14 Table 8. Stacked LFBGA73 8x11.6mm, 10x12 array, 0.8mm pitch, Package Mechanical Data. . . 15 2/27 M76DW63000A, M76DW62000A PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 9. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 FLASH MEMORY DEVICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 SRAM DEVICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 SRAM SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 8. SRAM Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 SRAM OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Standby/Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 9. SRAM Read Mode AC Waveforms, Address Controlled . . . . . . . . . . . . . . . . . . . . . . 19 Figure 10. SRAM Read AC Waveforms, G Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 11. SRAM Standby AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 10. SRAM Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 12. SRAM Write AC Waveforms, W Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 13. SRAM Write AC Waveforms, E1S Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 14. SRAM Write AC Waveforms, W Controlled with G Low. . . . . . . . . . . . . . . . . . . . . . 23 Figure 15. SRAM Write Cycle Waveform, UBS and LBS Controlled, G Low . . . . . . . . . . . . . . 23 Table 11. SRAM Write AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 16. SRAM Low VCCS Data Retention AC Waveforms, E1S or UBS / LBS Controlled . . 25 Table 12. SRAM Low VCCS Data Retention Characteristic. . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 13. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3/27 M76DW63000A, M76DW62000A SUMMARY DESCRIPTION The M76DW62000A is a low voltage Multiple Memory Product which combines two memory devices; a 64 Mbit Multiple Bank, Boot Block Flash memory (M29DW640D) and an 8 or 4Mbit SRAM. This document should be read in conjunction with the M29DW640D datasheet. Recommended operating conditions do not allow both the Flash and SRAM devices to be active at the same time. The memory is offered in an LFBGA73 (8 x 11.6mm, 0.8 mm pitch) package and is supplied with all the bits erased (set to ‘1’). Figure 2. Logic Diagram Table 1. Signal Names A0-A211 Address Inputs DQ0-DQ7 Data Inputs/Outputs DQ8-DQ14 Data Inputs/Outputs DQ15A–1 Data Input/Output or Address Input G Output Enable input W Write Enable input VCCF Flash Power Supply VPP/WP VPP/Write Protect VSS Ground VCCS SRAM Power Supply VSSS SRAM Ground NC Not Connected Internally VPP/WP VCCF VCCS 22 A0-A21 Flash Memory Control Functions 15 EF DQ0-DQ14 G DQ15A–1 W RPF BYTE M76DW63000A M76DW62000A RB Chip Enable input RPF Reset/Block Temporary Unprotect RB Ready/Busy Output BYTE Byte/Word Organization Select SRAM Control Functions E1S E1S, E2S Chip Enable inputs E2S UBS Upper Byte Enable input UBS LBS Lower Byte Enable input Note: 1. A21-A19 are not connected to the SRAM component of the M76DW63000A, and A21-A18 are not connected to the SRAM component of the M76DW62000A. LBS VSS AI08188B 4/27 EF M76DW63000A, M76DW62000A Figure 3. LFBGA Connections (Top view through package) 1 A NC B NC C NC 2 3 4 5 6 7 8 9 10 NC NC NC NC A7 LBS VPP /WP W A8 A11 D A3 A6 UBS RPF E2S A19 A12 A15 E A2 A5 A18 RB A20 A9 A13 A21 F NC A1 A4 A17 A10 A14 NC NC G NC A0 VSS DQ1 DQ6 NC A16 NC H EF G DQ9 DQ3 DQ4 DQ13 DQ15 /A-1 BYTE J E1S DQ0 DQ10 VCCF VCCS DQ12 DQ7 VSS DQ8 DQ2 DQ11 NC DQ5 DQ14 NC NC K M NC N NC NC NC AI08189 5/27 M76DW63000A, M76DW62000A SIGNAL DESCRIPTION See Figure 2 Logic Diagram and Table 1,Signal Names, for a brief overview of the signals connected to this device. Address Inputs (A0-A21). Addresses A0-A18 (for M76DW63000A), or A0-A17 (for M76DW62000A), are common inputs for the Flash Memory and the SRAM components. The other lines (A19-A21, or A18-21, respectively) are inputs for the Flash Memory component only. The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the internal state machine. The Flash memory is accessed through the Chip Enable (EF) and Write Enable (W) signals, while the SRAM is accessed through two Chip Enable signals (E1S and E2S) and the Write Enable signal (W). Data Inputs/Outputs (DQ0-DQ7). The Data I/O outputs the data stored at the selected address during a Bus Read operation. During Bus Write operations they represent the commands sent to the Command Interface of the Program/Erase Controller. Data Inputs/Outputs (DQ8-DQ14). The Data I/O outputs the data stored at the selected address during a Bus Read operation when BYTE is High, VIH. When BYTE is Low, VIL, these pins are not used and are high impedance. During Bus Write operations the Command Register does not use these bits. When reading the Status Register these bits should be ignored. Data Input/Output or Address Input (DQ15A– 1). When BYTE is High, VIH, this pin behaves as a Data Input/Output pin (as DQ8-DQ14). When BYTE is Low, VIL, this pin behaves as an address pin; DQ15A–1 Low will select the LSB of the addressed Word, DQ15A–1 High will select the MSB. Throughout the text consider references to the Data Input/Output to include this pin when BYTE is High and references to the Address Inputs to include this pin when BYTE is Low except when stated explicitly otherwise. Flash Chip Enable (EF). The Chip Enable input activates the memory, allowing Bus Read and Bus Write operations to be performed. When Chip Enable is High, V IH, all other pins are ignored. Output Enable (G). The Output Enable, G, controls the Bus Read operation of the device. Write Enable (W). The Write Enable, W, controls the Bus Write operation of the device. VPP/Write VPP/Write Protect (VPP/WP). The Protect pin provides two functions. The VPP function allows the Flash memory to use an external high voltage power supply to reduce the time required for Program operations. This is achieved 6/27 by bypassing the unlock cycles and/or using the multiple Word (2 or 4 at-a-time) or multiple Byte Program (2, 4 or 8 at-a-time) commands. The Write Protect function provides a hardware method of protecting the four outermost boot blocks (two at the top, and two at the bottom of the address space). When V PP/Write Protect is Low, VIL, the memory protects the four outermost boot blocks; Program and Erase operations in these blocks are ignored while VPP/Write Protect is Low, even when RPF is at VID. When VPP/Write Protect is High, VIH, the memory reverts to the previous protection status of the four outermost boot blocks (two at the top, and two at the bottom of the address space). Program and Erase operations can now modify the data in these blocks unless the blocks are protected using Block Protection. When V PP/Write Protect is raised to VPP the memory automatically enters the Unlock Bypass mode. When V PP/Write Protect returns to VIH or VIL normal operation resumes. During Unlock Bypass Program operations the memory draws IPP from the pin to supply the programming circuits. See the description of the Unlock Bypass command in the Command Interface section. The transitions from VIH to V PP and from V PP to VIH must be slower than tVHVPP. See the M29DW640D datasheet for more details. Never raise VPP/Write Protect to VPP from any mode except Read mode, otherwise the memory may be left in an indeterminate state. The VPP/Write Protect pin must not be left floating or unconnected or the device may become unreliable. A 0.1µF capacitor should be connected between the V PP/Write Protect pin and the VSS Ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during Unlock Bypass Program, I PP. Reset/Block Temporary Unprotect (RPF). The Reset/Block Temporary Unprotect pin can be used to apply a Hardware Reset to the memory or to temporarily unprotect all Blocks that have been protected. Note that if V PP/WP is at VIL, then the two outermost boot blocks will remain protected even if RPF is at VID. A Hardware Reset is achieved by holding Reset/ Block Temporary Unprotect Low, V IL, for at least tPLPX. After Reset/Block Temporary Unprotect goes High, V IH, the memory will be ready for Bus Read and Bus Write operations after tPHEL or tRHEL, whichever occurs last. See the M29DW640D datasheet for more details. M76DW63000A, M76DW62000A Holding RPF at VID will temporarily unprotect the protected Blocks in the memory. Program and Erase operations on all blocks will be possible. The transition from VIH to VID must be slower than tPHPHH. Ready/Busy Output (RB). The Ready/Busy pin is an open-drain output that can be used to identify when the Flash memory is performing a Program or Erase operation. During Program or Erase operations Ready/Busy is Low, VOL. Ready/Busy is high-impedance during Read mode, Auto Select mode and Erase Suspend mode. After a Hardware Reset, Bus Read and Bus Write operations cannot begin until Ready/Busy becomes high-impedance. The use of an open-drain output allows the Ready/ Busy pins from several memories to be connected to a single pull-up resistor. A Low will then indicate that one, or more, of the memories is busy. Byte/Word Organization Select (BYTE). The Byte/Word Organization Select pin is used to switch between the x8 and x16 Bus modes of the Flash memory. When Byte/Word Organization Select is Low, V IL, the Flash memory is in x8 mode, when it is High, V IH, the Flash memory is in x16 mode. SRAM Chip Enable (E1S, E2S). The Chip Enable inputs activate the SRAM memory control logic, input buffers and decoders. E1 S at VIH or E2S at VIL deselects the memory and reduces the power consumption to the standby level. E1S and E2S can also be used to control writing to the SRAM memory array, while W remains at VIL. It is not allowed to set EF at VIL, E1S at VIL and E2S at VIH at the same time. SRAM Upper Byte Enable (UBS). The Upper Byte Enable enables the upper bytes for SRAM (DQ8-DQ15). UBS is active low. SRAM Lower Byte Enable (LBS). The Lower Byte Enable enables the lower bytes for SRAM (DQ0-DQ7). LBS is active low. VCCF Supply Voltage (2.7V to 3.3V). VCCF provides the power supply for all operations (Read, Program and Erase). The Command Interface is disabled when the VCCF Supply Voltage is less than the Lockout Voltage, VLKO . This prevents Bus Write operations from accidentally damaging the data during power up, power down and power surges. If the Program/ Erase Controller is programming or erasing during this time then the operation aborts and the memory contents being altered will be invalid. A 0.1µF capacitor should be connected between the VCCF Supply Voltage pin and the VSS Ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during Program and Erase operations, ICC3. VCCS Supply Voltage (2.7V to 3.3V). VCCS provides the power supply for the SRAM control pins. VSS Ground. VSS is the ground reference for all voltage measurements in the Flash and SRAM chips. The device features two VSS pins both of which must be connected to the system ground. 7/27 M76DW63000A, M76DW62000A FUNCTIONAL DESCRIPTION The Flash and SRAM components have separate power supplies. They are distinguished by three chip enable inputs: EF for the Flash memory and, E1S and E2S for the SRAM. Recommended operating conditions do not allow both the Flash and the SRAM to be in active mode at the same time. The most common example is simultaneous read operations on the Flash and the SRAM which would result in a data bus contention. Therefore it is recommended to put the SRAM in the high impedance state when reading the Flash and vice versa (see Table 2 Main Operation Modes for details). Figure 4. Functional Block Diagram VCCF VPP/WP EF RB RPF BYTE Flash Memory 64 Mbit (x8 or x16) A[n]-A21 A0-A[m] G VCCS W E1S DQ0-DQ15/A-1 SRAM 8Mbit or 4Mbit (x16) E2S UBS LBS VSS AI08190B Note: Where n=19 and m=18 for M76DW63000A, and n=18 and m=17 for M76DW62000A. 8/27 M76DW63000A, M76DW62000A Table 2. Main Operation Modes EF RPF G W Read VIL VIH VIL VIH SRAM must be disabled Data Output Write VIL VIH VIH VIL SRAM must be disabled Data Input Standby VIH VCC ±0.3 X X Any SRAM mode is allowed Hi-Z Output Disable X VIH VIH VIH Any SRAM mode is allowed Hi-Z Reset X VIL X X Any SRAM mode is allowed Hi-Z VIL VIH VIL VIH VIL VIL VIL VIH VIL VIH VIL VIH Data out Hi-Z VIL VIH VIL VIH VIH VIL Hi-Z Data out X VIL VIL VIH VIL VIL Data in Word Write X VIL VIL VIH VIL VIH Data in Hi-Z X VIL VIL VIH VIH VIL Hi-Z Data in X X VIH X X X Hi-Z X X X X VIH VIH Hi-Z X X X VIL X X Hi-Z VIH VIH VIL VIH VIL VIL Hi-Z VIH VIH VIL VIH VIL VIH Hi-Z VIH VIH VIL VIH VIH VIL Hi-Z Flash Memory Operation Mode(2) Read Flash Memory must be disabled SRAM Write Flash Memory must be disabled Standby/ Power Down Output Disable Any Flash Memory mode is allowable Any Flash Memory mode is allowable E1S E2S UBS LBS DQ15-DQ8 DQ7-DQ0 Data out Word Read Note: 1. X = Don’t Care = VIL or VIH. 2. This table is valid when BYTE = VIH. This table is also valid when BYTE = VIL , with the only difference that DQ15-DQ8 are always high impedance when the Flash Memory component is being accessed. 3. For the Block Protect and Unprotect features, refer to the M29DW640D datasheet. Only the In-System Technique is available in the stacked product. 4. To read the Manufacturer Code, the Device Code, the Block Protection Status and the Extended Block indicator bit, refer to the “Auto Select Command” in the M29DW640D datasheet. 9/27 M76DW63000A, M76DW62000A MAXIMUM RATING Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not im- plied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 3. Absolute Maximum Ratings Value Symbol Parameter Max Ambient Operating Temperature (1) –40 85 °C TBIAS Temperature Under Bias –50 125 °C TSTG Storage Temperature –65 150 °C Input or Output Voltage –0.5 VCCF +0.3 V VCCF Flash Supply Voltage –0.6 4 V VID Identification Voltage –0.6 13.5 V VPPF Program Voltage –0.6 13.5 V VCCS SRAM Supply Voltage –0.5 3.8 V TA VIO Note: 1. Depends on range. 10/27 Unit Min M76DW63000A, M76DW62000A DC AND AC PARAMETERS This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measurement Conditions summarized in Table 4, Operating and AC Measurement Conditions. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. The operating and AC measurement parameters given in this section (see Table 4 below) correspond to those of the stand-alone Flash and SRAM devices. For compatibility purposes, the M29DW640D voltage range is restricted to VCCS in the stacked product. Table 4. Operating and AC Measurement Conditions Flash Memory SRAM 70 70 Parameter Units Min Max Min Max VCCF Supply Voltage 2.7 3.6 – – V VCCS Supply Voltage – – 2.7 3.3 V –40 85 –40 85 °C Ambient Operating Temperature Load Capacitance (CL) 30 30 Input Rise and Fall Times pF 10 Input Pulse Voltages Input and Output Timing Ref. Voltages Figure 5. AC Measurement I/O Waveform 3.3 ns 0 to VCCF 0 to VCCF V VCCF/2 VCCF/2 V Figure 6. AC Measurement Load Circuit VCCF VCCF VCCF/2 VPP 0V VCCF 25kΩ AI08186 DEVICE UNDER TEST CL 0.1µF 25kΩ 0.1µF CL includes JIG capacitance AI08187 Table 5. Device Capacitance Symbol CIN COUT Parameter Input Capacitance Output Capacitance Max Unit VIN = 0V, f=1 MHz Test Condition Typ 12 pF VOUT = 0V, f=1 MHz 15 pF Note: Sampled only, not 100% tested. 11/27 M76DW63000A, M76DW62000A Table 6. Flash Memory DC Characteristics Symbol Parameter Test Condition M76DW63000A, M76DW62000A Min Unit Max 0V ≤ VIN ≤ VCC ±1 µA Output Leakage Current 0V ≤ VOUT ≤ VCC ±1 µA Supply Current (Read) EF = VIL, G = VIH, f = 6MHz 10 mA ICC2 Supply Current (Standby) EF = VCC ±0.2V, RPF = VCC ±0.2V 100 µA ICC3 (1,2) Supply Current (Program/ Erase) VPP/WP = VIL or VIH 20 mA VPP/WP = VPP 20 mA ILI Input Leakage Current ILO ICC1(2) Program/Erase Controller active VIL Input Low Voltage –0.5 0.8 V VIH Input High Voltage 0.7VCC VCC +0.3 V VPP Voltage for VPP/WP Program Acceleration VCC = 3.0V ±10% 11.5 12.5 V IPP Current for VPP/WP Program Acceleration VCC = 3.0V ±10% 15 mA VOL Output Low Voltage IOL = 1.8mA 0.45 V VOH Output High Voltage IOH = –100µA VID Identification Voltage 11.5 12.5 V Program/Erase Lockout Supply Voltage 1.8 2.3 V VLKO VCC –0.4 Note: 1. Sampled only, not 100% tested. 2. In Dual operations the Supply Current will be the sum of I CC1(read) and I CC3 (program/erase). 12/27 V M76DW63000A, M76DW62000A Table 7. SRAM DC Characteristics M76DW63000A Symbol Parameter Unit Min ILI Input Leakage Current ILO Output Leakage Current M76DW62000A Test Condition Typ Max Min Typ Max 0V ≤ VIN ≤ VCCS ±1 ±1 µA 0V ≤ VOUT ≤ VCCS, SRAM Outputs Hi-Z ±1 ±1 µA E1S ≥ VCCS – 0.2V VIN ≥ VCCS – 0.2V or VIN ≤ 0.2V ICCS ICC VCC Standby Current Supply Current f = fmax (A0-A182 and DQ0DQ15 only) f = 0 (GS, WS, UBS and LBS) 8 25 7 15 µA E1S ≥ VCCS – 0.2V VIN ≥ VCCS – 0.2V or VIN ≤ 0.2V, f=0 8 25 7 15 µA f = fmax = 1/AVAV, VCCS = 3.3V, IOUT = 0 mA 5.5 12 5.5 12 mA f = 1MHz, VCCS = 3.3V, IOUT = 0 mA 1.5 3 1.5 3 mA VIL Input Low Voltage –0.3 0.8 –0.3 0.8 V VIH Input High Voltage 2.2 VCCS +0.3 2.2 VCCS +0.3 V VOL Output Low Voltage VCCS = VCC min IOL = 2.1mA 0.4 V VOH Output High Voltage VCCS = VCC min IOH = –1.0mA 0.4 2.4 2.4 V Note: 1. Sampled only, not 100% tested. 2. A0-A18 for the M76DW63000A, A0-A17 for the M76DW62000A. 13/27 M76DW63000A, M76DW62000A PACKAGE MECHANICAL Figure 7. Stacked LFBGA73 8x11.6mm, 10x12 array, 0.8mm pitch, Bottom View Package Outline D D1 FD FE E SD SE E1 BALL "A1" e b ddd A A2 A1 BGA-Z50 Note: Drawing is not to scale. 14/27 M76DW63000A, M76DW62000A Table 8. Stacked LFBGA73 8x11.6mm, 10x12 array, 0.8mm pitch, Package Mechanical Data millimeters inches Symbol Typ Min A Max Typ Min 1.400 A1 Max 0.0551 0.250 0.0098 A2 0.910 0.0358 b 0.400 0.350 0.450 0.0157 0.0138 0.0177 D 8.000 7.900 8.100 0.3150 0.3110 0.3189 D1 7.200 0.2835 ddd 0.100 11.500 11.700 0.0039 E 11.600 0.4567 0.4528 0.4606 E1 8.800 e 0.800 – – FD 0.400 0.0157 FE 1.400 0.0551 SD 0.400 – – 0.0157 – – SE 0.400 – – 0.0157 – – 0.3465 – – 0.0315 15/27 M76DW63000A, M76DW62000A PART NUMBERING Table 9. Ordering Information Scheme Example: M76DW 6 2 0 0 0 A 70 Z T Device Type M76 = MMP (Flash + SRAM) Architecture D = Dual Operation Operating Voltage W = VCCF = VCCS = 2.7V to 3.3V Flash Device Size (Die1 Density) 6 = 64 Mbit SRAM Device Size (Die2 Density) 2 = 4 Mbit 3 = 8 Mbit Die3 0 = Die3 Density Die4 0 = Die4 Density Flash Specification Details 0 = Multiple Bank Stacked Specification Details A = 0.15µm Flash & SRAM Speed 70 = 70ns 90 = 90ns Package and Temperature Range Z = LFBGA73: 8 x 11.6mm, 0.8mm pitch Option T = Tape & Reel packing Note: This product is also available with the Extended Block factory locked. For further details and ordering information contact your nearest ST sales office. Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you. 16/27 M76DW63000A, M76DW62000A FLASH MEMORY DEVICE The M76DW62000A contains one 64 Mbit Flash memory. For detailed information on how to use the Flash memory refer to the M29DW640D datasheet, which is available on the STMicroelectronics web site, www.st.com. SRAM DEVICE SRAM SUMMARY DESCRIPTION The SRAM is an 8Mbit or 4Mbit asynchronous random access memory which features a super low voltage operation and low current consumption with an access time of 70ns under all conditions. The memory operations can be performed using a single low voltage supply, 2.7V to 3.3V, which is the same as the Flash voltage supply. Figure 8. SRAM Logic Diagram 256Kb x 16 RAM Array 2048 x 2048 SENSE AMPS A0-A10 ROW DECODER DATA IN DRIVERS DQ0-DQ7 DQ8-DQ15 COLUMN DECODER UBS WS A11-A18 or A11-A17 GS LBS POWER-DOWN CIRCUIT UBS E1S E2S LBS AI07939B 17/27 M76DW63000A, M76DW62000A SRAM OPERATIONS There are five standard operations that control the SRAM component. These are Bus Read, Bus Write, Standby/Power-down, Data Retention and Output Disable. A summary is shown in Table 2, Main Operation Modes Read. Read operations are used to output the contents of the SRAM Array. The SRAM is in Read mode whenever Write Enable, WS, is at VIH, Output Enable, GS, is at VIL, Chip Enable, E1 S, is at VIL, Chip Enable, E2S, is at VIH, and Byte Enable inputs, UBS and LBS are at V IL. Valid data will be available on the output pins after a time of tAVQV after the last stable address. If the Chip Enable or Output Enable access times are not met, data access will be measured from the limiting parameter (tE1LQV, tE2HQV, or tGLQV) rather than the address. Data out may be indeterminate at tE1LQX, tE2HQX and tGLQX, but data lines will always be valid at tAVQV (see Table 10, Table 10, Figures 9 and 10, SRAM Read AC Characteristics). Write. Write operations are used to write data to the SRAM. The SRAM is in Write mode whenever W and E1S are at VIL, and E2S is at VIH. Either the Chip Enable inputs, E1 S and E2S, or the Write Enable input, WS, must be deasserted during address transitions for subsequent write cycles. A Write operation is initiated when E1S is at VIL, E2S is at V IH and W is at VIL. The data is latched on the falling edge of E1S, the rising edge of E2S or the falling edge of W S, whichever occurs last. The Write cycle is terminated on the rising edge of E1S, the rising edge of W or the falling edge of E2S, whichever occurs first. 18/27 If the Output is enabled (E1S=VIL, E2S=VIH and GS=VIL), then W will return the outputs to high impedance within tWLQZ of its falling edge. Care must be taken to avoid bus contention in this type of operation. The Data input must be valid for t DVWH before the rising edge of Write Enable, for t DVE1H before the rising edge of E1S or for tDVE2L before the falling edge of E2S, whichever occurs first, and remain valid for tWHDX, tE1HAX or tE2LAX (see Table 11, SRAM Write AC Characteristics, Figures 12, 13, 14 and 15). Standby/Power-Down. The SRAM component has a chip enabled power-down feature which invokes an automatic standby mode (see Table 10, SRAM Read AC Characteristics, Figure 11, SRAM Standby AC Waveforms). The SRAM is in Standby mode whenever either Chip Enable is deasserted, E1S at V IH or E2S at VIL. It is also possible when UBS and LB S are at VIH. Data Retention. The SRAM data retention performance as VCCS goes down to VDR are described in Table 12, SRAM Low VCCS Data Retention Characteristic, and Figure 16, SRAM Low V CCS Data Retention AC Waveforms, E1S or UBS / LBS Controlled. In E1S controlled data retention mode, the minimum standby current mode is entered when E1S ≥ VCCS – 0.2V and E2S ≤ 0.2V or E2S ≥ VCCS – 0.2V. In E2S controlled data retention mode, minimum standby current mode is entered when E2S ≤ 0.2V. Output Disable. The data outputs are high impedance when the Output Enable, GS, is at VIH with Write Enable, W S, at VIH. M76DW63000A, M76DW62000A Figure 9. SRAM Read Mode AC Waveforms, Address Controlled tAVAV A0-A17 VALID tAVQV tAXQX DQ0-DQ15 DATA VALID DATA VALID AI07942 Note: E1S = Low, E2S = High, G = Low, UBS and/or LBS = High, W = High. Figure 10. SRAM Read AC Waveforms, G Controlled tAVAV A0-A17 VALID tE1LQV tE1HQZ E1S tE1LQX tE2HQV tE2LQZ E2S tE2HQX tBLQV tBHQZ UBS, LBS tBLQX tGLQV tGHQZ G tGLQX DQ0-DQ15 DATA VALID AI07943b Note: Write Enable (W) = High. Address Valid prior to or at the same time as E1S, UBS and LB S going Low. Figure 11. SRAM Standby AC Waveforms E1S E2S ICC tPU tPD 50% AI07913b 19/27 M76DW63000A, M76DW62000A Table 10. SRAM Read AC Characteristics SRAM Symbol Alt Parameter Unit Min Max tAVAV tRC Read Cycle Time tAVQV tACC Address Valid to Output Valid tAXQX tOH Address Transition to Output Transition tBHQZ tBHZ UBS, LBS Disable to Hi-Z Output 25 ns tBLQV tAB UBS, LBS Access Time 70 ns tBLQX tBLZ UBS, LBS Enable to Low-Z Output tE1LQV tE2HQV tACS1 Chip Enable 1 Low or Chip Enable 2 High to Output Valid tE1LQX tE2HQX tCLZ1 Chip Enable 1 Low or Chip Enable 2 High to Output Transition tE1HQZ tE2LQZ tHZCE Chip Enable High or Chip Enable 2 Low to Output Hi-Z 25 ns tGHQZ tOHZ Output Enable High to Output Hi-Z 25 ns tGLQV tOE Output Enable Low to Output Valid 35 ns tGLQX tOLZ Output Enable Low to Output Transition tPD (1) Chip Enable 1 High or Chip Enable 2 Low to Power Down tPU (1) Chip Enable 1 Low or Chip Enable 2 High to Power Up Note: 1. Sampled only. Not 100% tested. 20/27 70 ns 70 10 ns 5 ns 70 10 ns ns 5 ns 70 0 ns ns ns M76DW63000A, M76DW62000A Figure 12. SRAM Write AC Waveforms, W Controlled tAVAV A0-A17 VALID tAVWH tE1LWH tWHAX E1S E2S tE2HWH tAVWL tWLWH W tBLWH UBS, LBS G tGHQZ DQ0-DQ15 tDVWH Note 2 tWHDZ INPUT VALID AI07944b Note: 1. W, E1S, E2S, UBS and/or LBS must be asserted to initiate a write cycle. Output Enable (G) = Low (otherwise, DQ0-DQ15 are high impedance). If E1S, E2S and W are deasserted at the same time, DQ0-DQ15 remain high impedance. 2. The I/O pins are in output mode and input signals must not be applied. 21/27 M76DW63000A, M76DW62000A Figure 13. SRAM Write AC Waveforms, E1S Controlled tAVAV A0-A17 VALID tAVE1H tAVE2L tAVE1L tE1LE1H tE1HAX tAVE2H tE2HE2L tE2LAX E1S E2S tWLE1H tWLE2L W tBLE1H tBLE2L UBS, LBS G tDVE1H tDVE2L tGHQZ DQ0-DQ15 Note 3 tE1HDZ tE2LDZ INPUT VALID AI07945b Note: 1. WS, E1S, E2S, UBS and/or LBS must be asserted to initiate a write cycle. Output Enable (GS) = Low (otherwise, DQ0-DQ15 are high impedance). If E1S, E2S and W are deasserted at the same time, DQ0-DQ15 remain high impedance. 2. If E1S, E2S and W are deasserted at the same time, DQ0-DQ15 remain high impedance. 3. The I/O pins are in output mode and input signals must not be applied. 22/27 M76DW63000A, M76DW62000A Figure 14. SRAM Write AC Waveforms, W Controlled with G Low tAVAV A0-A17 VALID tAVWH tE1LWH tE2HWH tWHAX E1S E2S tBLWH UBS, LBS tAVWL tWLWH W tWHQX tWLQZ tWHDZ tDVWH DQ0-DQ15 INPUT VALID AI07946b Note: 1. If E1S, E2S and W are deasserted at the same time, DQ0-DQ15 remain high impedance. Figure 15. SRAM Write Cycle Waveform, UBS and LB S Controlled, G Low tAVAV A0-A17 VALID tAVBH tE1LBH tE2HBH E1S E2S tAVBL tBLBH tBHAX UBS, LBS tWLBH W tDVBH DQ0-DQ15 tBHDZ INPUT VALID AI07947b Note: 1. If E1S, E2S and W are deasserted at the same time, DQ0-DQ15 remain high impedance. 23/27 M76DW63000A, M76DW62000A Table 11. SRAM Write AC Characteristics SRAM Symbol Alt Parameter Unit Min Max tAVAV tWC Write Cycle Time 70 ns tAVE1L, tAVE2H, tAVWL, tAVBL tAS Address Valid to Beginning of Write 0 ns tAVE1H, tAVE2L tAW Address Valid to Chip Enable 1 Low or Chip Enable 2 High 60 ns tAVWH tAW Address Valid to Write Enable High 60 ns tBLWH tBLE1H tBLE2L tAVBH tBW UBS, LBS Valid to End of Write 60 ns tBLBH tBW UBS, LBS Low to UBS, LBS High 60 ns tDVE1H, tDVE2L, tDVWH tDVBH tDW Input Valid to End of Write 30 ns tE1HAX, tE2LAX, tWHAX tBHAX tWR End of Write to Address Change 0 ns tE1HDZ , tE2LDZ, tWHDZ tBHDZ tHD Address Transition to End of Write 0 ns tE1LE1H, tE1LBH tE1LWH tCW1 Chip Enable 1 Low to End of Write 60 ns tE2HE2L, tE2HBH, tE2HWH tCW2 Chip Enable 2 High to End of Write 60 ns tGHQZ tGHZ Output Enable High to Output Hi-Z tWHQX tDH Write Enable High to Input Transition 5 ns tWLBH tWP Write Enable Low to UBS, LBS High 50 ns tWLQZ tWHZ Write Enable Low to Output Hi-Z tWLWH tWLE1H tWLE2L tWP Write Enable Pulse Width 24/27 25 25 50 ns ns ns M76DW63000A, M76DW62000A Figure 16. SRAM Low VCCS Data Retention AC Waveforms, E1S or UBS / LBS Controlled DATA RETENTION MODE VCCS VCCS (min) VCCS (min) tCDR E1S or tR UBS, LBS AI07918b Table 12. SRAM Low VCCS Data Retention Characteristic M76DW63000A Symbol Parameter M76DW62000A Test Condition Unit Min VCCS = 1.5V, E1S ≥ VCCS – 0.2V, VIN ≥ VCCS – 0.2V or VIN ≤ 0.2V Typ Max 4 12 Min Typ Max 3 10 µA 3.3 V ICCDR Supply Current (Data Retention) VDR Supply Voltage (Data Retention) tCDR Chip Disable to Power Down 0 0 ns Operation Recovery Time 70 70 ns tR 1.5 3.3 1.5 2. Sampled only. Not 100% tested. 25/27 M76DW63000A, M76DW62000A REVISION HISTORY Table 13. Document Revision History Date Version 16-Apr-2003 1.0 First Issue 19-May-2003 1.1 M76DW63000A, 8Mbit SRAM, added 12-Jun-2003 1.2 M76DW63000A, 8Mbit SRAM, corrected to 512Kx16 on first page 24-Sep-2003 1.3 Voltage supply range extended 2.7V working at all speed options 26/27 Revision Details M76DW63000A, M76DW62000A Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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