M69AW024BE 16 Mbit (1M x16) 3V Asynchronous PSRAM FEATURES SUMMARY ■ ■ ■ ■ ■ ■ SUPPLY VOLTAGE: 2.7 to 3.3V ACCESS TIME: 60ns LOW STANDBY CURRENT: 70µA DEEP POWER DOWN CURRENT: 10µA COMPATIBLE WITH STANDARD LPSRAM TFBGA48 PACKAGE RoHS COMPLIANT (directive 2002/95/EC of the European Parliament) Figure 1. Package BGA TFBGA48 (ZB) 6x8 mm April 2005 1/25 M69AW024BE TABLE OF CONTENTS FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1. Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 3. TFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Address Inputs (A0-A19). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Data Inputs/Outputs (DQ8-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Chip Enable (E1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Chip Enable (E2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Upper Byte Enable (UB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Lower Byte Enable (LB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 VCC Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 VSS Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Power On Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Deep Power-down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 3. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 4. Figure 5. Figure 6. Table 5. Table 6. Table 7. Figure 7. Figure 8. Figure 9. 2/25 Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Read and Standby Modes AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Address Access after G Controlled Read AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . 14 UB/LB Controlled Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 M69AW024BE Table 8. Write Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 10.Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 11.W Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 12.Write Enable and UB/LB Controlled, Byte Write AC Waveforms 1 . . . . . . . . . . . . . . . . . 18 Figure 13.Write Enable and UB/LB Controlled, Byte Write AC Waveforms 2 . . . . . . . . . . . . . . . . . 18 Figure 14.Write Enable and UB/LB Controlled, Byte Write AC Waveforms 3 . . . . . . . . . . . . . . . . . 19 Figure 15.Write Enable and UB/LB Controlled, Byte Write AC Waveforms 4 . . . . . . . . . . . . . . . . . 19 Table 9. Standby, Power-Down and Power-Up AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 16.Power-up Mode AC Waveforms - 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 17.Power-up Mode AC Waveforms - 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 18.Power-Down Entry ad Exit AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 19.Standby Mode Entry AC Waveforms, after Read or Write . . . . . . . . . . . . . . . . . . . . . . . 21 PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 20.TFBGA48 6x8mm - 6x8 ball array, 0.75 mm pitch, Package Outline, Bottom View . . . . 22 Table 10. TFBGA48 6x8mm - 6x8 ball array, 0.75 mm pitch, Package Mechanical Data. . . . . . . . 22 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 11. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 12. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3/25 M69AW024BE SUMMARY DESCRIPTION The M69AW024BE is a 16 Mbit (16,777,216 bit) CMOS memory, organized as 1,024,576 words by 16 bits, and is supplied by a single 2.7V to 3.3V supply voltage range. M69AW024BE is a member of STMicroelectronics PSRAM memory family, based on the one-transistor per-cell architecture. These devices are manufactured using dynamic random access memory cells, to minimize the cell size, and maximize the amount of memory that can be implemented in a given area. However, through the use of internal control logic, the device is fully static in its operation, requiring no external clocks or timing strobes, and has a standard Asynchronous SRAM Interface. The internal control logic of the M69AW024BE handles the periodic refresh cycle, automatically, and without user involvement. Write cycles can be performed on a single byte by using Upper Byte Enable (UB) and Lower Byte Enable (LB). The device can be put into standby mode using Chip Enable (E1) or in deep power down mode by using Chip Enable (E2). Power-Down mode achieves a very low current consumption by halting all the internal activities. Since the refresh circuitry is halted, the duration of the power-down should be less than the maximum period for refresh, if the user has not finished with the data contents of the memory. Figure 2. Logic Diagram Table 1. Signal Names A0-A19 Address Input DQ0-DQ15 Data Input/Output E1, E2 Chip Enable, Power Down G Output Enable W Write Enable W UB Upper Byte Enable E1 LB Lower Byte Enable VCC Supply Voltage VSS Ground NC Not Connected (no internal connection) VCC 20 16 A0-A19 E2 DQ0-DQ15 M69AW024BE G UB LB VSS 4/25 AI07406b M69AW024BE Figure 3. TFBGA Connections (Top view through package) 1 2 3 4 5 6 A LB G A0 A1 A2 E2 B DQ8 UB A3 A4 E1 DQ0 C DQ9 DQ10 A5 A6 DQ1 DQ2 D VSS DQ11 A17 A7 DQ3 VCC E VCC DQ12 NC A16 DQ4 VSS F DQ14 DQ13 A14 A15 DQ5 DQ6 G DQ15 A19 A12 A13 W DQ7 H A18 A8 A9 A10 A11 NC AI07409 5/25 M69AW024BE SIGNAL DESCRIPTIONS See Figure 2., Logic Diagram, and Table 1., Signal Names, for a brief overview of the signals connected to this device. Address Inputs (A0-A19). The Address Inputs select the cells in the memory array to access during Read and Write operations. Data Inputs/Outputs (DQ8-DQ15). The Upper Byte Data Inputs/Outputs carry the data to or from the upper part of the selected address during a Write or Read operation, when Upper Byte Enable (UB) is driven Low. Data Inputs/Outputs (DQ0-DQ7). The Lower Byte Data Inputs/Outputs carry the data to or from the lower part of the selected address during a Write or Read operation, when Lower Byte Enable (LB) is driven Low. Chip Enable (E1). When asserted (Low), the Chip Enable, E1, activates the memory state machine, address buffers and decoders, allowing Read and Write operations to be performed. When de-asserted (High), all other pins are ignored, and the device is put, automatically, in low-power Standby mode. Chip Enable (E2). The Chip Enable, E2, puts the device in Deep Power-down mode when it is driven Low. This is the lowest power mode. 6/25 Output Enable (G). The Output Enable, G, provides a high speed tri-state control, allowing fast read/write cycles to be achieved with the common I/O data bus. Write Enable (W). The Write Enable, W, controls the Bus Write operation of the memory’s Command Interface. Upper Byte Enable (UB). The Upper Byte Enable, UB, gates the data on the Upper Byte Data Inputs/Outputs (DQ8-DQ15) to or from the upper part of the selected address during a Write or Read operation. Lower Byte Enable (LB). The Lower Byte Enable, LB, gates the data on the Lower Byte Data Inputs/Outputs (DQ0-DQ7) to or from the lower part of the selected address during a Write or Read operation. VCC Supply Voltage. The VCC Supply Voltage supplies the power for all operations (Read or Write) and for driving the refresh logic, even when the device is not being accessed. VSS Ground. The VSS Ground is the reference for all voltage measurements. M69AW024BE Figure 4. Block Diagram ARBITRATION LOGIC INTERNAL CLOCK GENERATOR E2 W VCC DYNAMIC MEMORY ARRAY INPUT/OUTPUT BUFFER E1 G ROW DECODER ADDRESS REFRESH CONTROLLER CONTROL LOGIC DQ0-DQ7 DQ8-DQ15 COLUMN DECODER LB UB VCC VSS POWER CONTROLLER ADDRESS AI07410 7/25 M69AW024BE OPERATION Operational modes are determined by device control inputs W, E1, E2, LB and UB as summarized in the Operating Modes table (see Table 2.). Power On Sequence Because the internal control logic of the M69AW024BE needs to be initialized, the following power-on procedure must be followed before the memory is used: – Apply power and wait for VCC to stabilize – Wait tCHEL while driving both Chip Enable signals (E1 and E2) High – Activate the memory by driving Chip Enable (E1) Low. Read Mode The device is in Read mode when: – Write Enable (W) is High and – Output Enable (G) Low and – the two Chip Enable signals are asserted (E1 is Low, and E2 is High). The time taken to enter Read mode (tELQV, tGLQV or tBLQV) depends on which of the above signals was the last to reach the appropriate level. Data out (DQ15-DQ0) may be indeterminate during tELQX, tGLQX and tBLQX, but data will always be valid during tAVQV. Write Mode The device is in Write mode when – Write Enable (W) is Low and – Chip Enable (E1) is Low and – the two Chip Enable signals are asserted (E1 is Low, and E2 is High) 8/25 – one of Upper Byte Enable (UB) or Lower Byte Enable (LB) is Low, while the other is High. The Write cycle begins just after the event (the falling edge) that causes the last of these conditions to become true (tAVWL, tAVEL or tAVBL). The Write cycle is terminated by the earlier of a rising edge on Write Enable (W) or Chip Enable (E1). If the device is in Write mode (Chip Enable (E1) is Low, Output Enable (G) is Low, Upper Byte Enable (UB) or Lower Byte Enable (LB) is Low), then Write Enable (W) will return the outputs to high impedance within tWHDZ of its falling edge. Care must be taken to avoid bus contention in this type of operation. Data input must be valid for tDVWH before the rising edge of Write Enable (W), or for tDVEH before the rising edge of Chip Enable (E1), whichever occurs first, and remain valid for tBHDZ, tWHDZ, tEHDZ. Standby Mode The device is in Standby mode when: – Chip Enable (E1) is High and – Chip Enable (E2) is High. The input/output buffers and the decoding/control logic are switched off, but the dynamic array continues to be refreshed. In this mode, the memory current consumption, ISB, is reduced, and the data remains valid. Deep Power-down Mode The device is in Deep Power-down mode when: – Chip Enable (E2 is Low). M69AW024BE Table 2. Operating Modes Operation E2 E1 W G LB UB A0-A19 DQ0-DQ7 DQ8DQ15 ICC Data Retention Standby (Deselect) VIH VIH X (1) X (1) X (1) X (1) X (1) Hi-Z Hi-Z ISB Yes Output Disabled (2) VIH VIL VIH VIH X (1) X (1) Note (4) Hi-Z Hi-Z ICC Yes Output Disabled (No Read) VIH VIL VIH VIL VIH VIH Valid Hi-Z Hi-Z ICC Yes Upper Byte Read VIH VIL VIH VIL VIH VIL Valid Hi-Z Output Valid ICC Yes Lower Byte Read VIH VIL VIH VIL VIL VIH Valid Output Valid Hi-Z ICC Yes Word Read VIH VIL VIH VIL VIL VIL Valid ICC Yes Upper Byte Write VIH VIL VIL VIH VIH VIL Valid Invalid Input Valid ICC Yes Lower Byte Write VIH VIL VIL VIH VIL VIH Valid Input Valid Invalid ICC Yes Word Write VIH VIL VIL VIH VIL VIL Valid Input Valid Input Valid ICC Yes Power-down (3) VIL X (1) X (1) X (1) X (1) X (1) X (1) Hi-Z Hi-Z IPD No Note: 1. 2. 3. 4. Output Valid X = VIH or VIL. Output Disable mode should not be kept longer than 1µs. Power-down mode can be entered from Stand-by state, and all DQ pins are in Hi-Z state. Can be either VIL or VIH but must be valid before Read or Write. 9/25 M69AW024BE MAXIMUM RATING Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Table 3. Absolute Maximum Ratings Symbol Parameter Min Max Unit IO Output Current –50 50 mA TA Ambient Operating Temperature –30 85 °C (1) °C TLEAD Lead Temperature During Soldering TSTG Storage Temperature –55 125 °C VCC Core Supply Voltage –0.5 3.6 V VIO Input or Output Voltage –0.5 3.6 V Note: 1. Compliant with the JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU. 10/25 M69AW024BE DC AND AC PARAMETERS This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measurement Conditions summarized in Table 4., Operating and AC Measurement Conditions. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. Table 4. Operating and AC Measurement Conditions M69AW024BE Parameter –60 Unit Min Max VCC Supply Voltage1 2.7 3.3 V Ambient Operating Temperature –30 85 °C Load Capacitance (CL) 50 pF Output Circuit Protection Resistance (R1) 50 Ω Input Rise and Fall Times 4 ns 0 to VCC V Input and Output Timing Ref. Voltages VCC/2 V Output Transition Timing Ref. Voltages VRL = 0.3VCC; VRH = 0.7VCC V Input Pulse Voltages Input Transition Time (tτ) between VIL and VIH(2) 5 ns Note: 1. All voltages are referenced to VSS. 2. The Input Transition Time used in AC measurements is 5ns. For other input transition times, see Table 9. Figure 5. AC Measurement Load Circuit Figure 6. AC Measurement I/O Waveform VCC/2 I/O Timing Reference Voltage R1 VCC VCC/2 DEVICE UNDER TEST OUT CL 0V Output Transition Timing Reference Voltage (1) VCC 0V 0.7VCC 0.3VCC AI07753c CL includes JIG capacitance AI07222c Note: 1. This waveform is given for Hi-Z and data transition AC parameters only (see Note 8. below Table 7., Read and Standby Modes AC Characteristics). 11/25 M69AW024BE Table 5. Capacitance Symbol CIN Test Condition Parameter Max Unit VIN = 0V 5 pF VOUT = 0V 8 pF Input Capacitance on all pins (except DQ) COUT (1) Output Capacitance Min Note: 1. Outputs deselected. Table 6. DC Characteristics Symbol ICC1 (1) Parameter Operating Supply Current ILI Input Leakage Current ILO IPD ISB Test Condition VCC = 3.3V, VIN = VIH or VIL, E1 = VIL, E2 = VIH, IOUT = 0mA Min Max Unit tRC/tWC = Min 20 mA tRC/tWC = 1µs 3.0 mA 0V ≤ VIN ≤ VCC –1 1 µA Output Leakage Current 0V ≤ VOUT ≤ VCC –1 1 µA Deep Power Down Current VCC = 3.3V, VIN = VIH or VIL, E2 ≤ 0.2V 10 µA 3.1V ≤ VCC ≤ 3.3V, VIN ≤ 0.2V or ≥ VCC –0.2V, E1 ≥ VCC –0.2V and E2 ≥ VCC –0.2V), IOUT = 0mA 100 µA 2.7V ≤ VCC ≤ 3.1V, VIN ≤ 0.2V or ≥ VCC –0.2V, E1 ≥ VCC –0.2V and E2 ≥ VCC –0.2V), IOUT = 0mA 70 µA Standby Supply Current CMOS VIH (2) Input High Voltage 2.7V ≤ VCC ≤ 3.3V 0.8VCC VCC + 0.2 V VIL (3) Input Low Voltage 2.7V ≤ VCC ≤ 3.3V –0.3 0.2VCC V 3.1V ≤ VCC ≤ 3.3V, IOH = –0.5mA 2.5 V 2.7V ≤ VCC ≤ 3.1V, IOH = –0.5mA 2.2 V VOH VOL Output High Voltage Output Low Voltage IOL = 1mA Note: 1. Average AC current, Outputs open, cycling at tAVAX (min). 2. Maximum DC voltage on inputs and I/O pins is VCC + 0.2V. During voltage transitions, data inputs may overshoot to VCC + 1.0V for a period of up to 5ns. 3. Minimum DC voltage on input or I/O pins is –0.3V. During voltage transitions, data inputs may overshoot to VSS + 1.0V for a period of up to 5ns. 12/25 0.4 V M69AW024BE Table 7. Read and Standby Modes AC Characteristics M69AW024BE Symbol tAVAX, tELEH Alt. Parameter –60 Unit Min Max 70 1000 ns tRC Read Cycle Time tELQV(3) tCE Chip Enable Access Time 60 ns tGLQV(3) tOE Output Enable Access Time 40 ns tAVQV(3,5) tAA Address Access Time 60 ns tBLQV(3) tBA LB, UB Low to Output Valid 30 ns tAXQX, tGHQX, tBHQX, tEHQX tOH Output Hold Time after Chip Enable Low 5 ns tELQX(4,8) tCLZ Chip Enable Low to Output Low-Z 5 ns tGLQX(4,8) tOLZ Output Enable Low to Output Low-Z 0 ns tBLQX(4,8) tBLZ LB, UB Low to Output Low-Z 0 ns tEHQZ(8) tCHZ Chip Enable High to Output Hi-Z 20 ns tGHQZ(8) tOHZ Output Enable High to Output Hi-Z 20 ns tBHQZ(8) tBHZ LB, UB High to Output Hi-Z 20 ns tAVEL tASC Address Set-up Time to Chip Enable Low –5 ns tAVGL tASO Address Valid to Output Enable Low 10 ns tAXAV(5) tAX tEHAX(6) tCHAH Chip Enable High to Address Hold Time –5 ns tGHAX tOHAH Output Enable High to Address Hold Time –5 ns tWHGL(7) tWHOL Write Enable High to Output Enable Low (Read Operations) 10 tEHEL tCP Chip Enable High Pulse Width 10 (1,2) (8) Address Invalid Time 10 1000 ns ns ns Note: 1. The maximum value of this timing is applicable if E1 is kept Low with addresses unchanged.If needed by the system operation, please contact your local ST representative for relaxation of the 1000ns limitation. 2. Addresses should not be changed during tAVAX(min). 3. These parameters are measured according to the conditions on input and output timing reference voltage shown on Figure 6., AC Measurement I/O Waveform. 4. The output load capacitance is 5pF without any other load. 5. These timings are given for E1 Low. 6. tAVAX(min) must be satisfied. 7. If the current value of tWHGL is lower than the minimum value given in the above table, tAVQV during the following Read operation may increase by tWHGL(current) – tWHGL(min). 8. All timings are measured according to the conditions for output transition timing reference voltage shown on Figure 6., AC Measurement I/O Waveform. 13/25 M69AW024BE Figure 7. Read Mode AC Waveforms tELEH A0-A19 ADDRESS VALID VALID tAVEL tAVEL tEHAX tELQV E1 tEHEL tGLQV tEHQZ G tGHQZ tBLQV LB, UB tBHQZ tBLQX tGLQX tEHQX tELQX DQ0-DQ15 VALID DATA OUTPUT AI09936 Note: E2 = High and W = High. Figure 8. Address Access after G Controlled Read AC Waveforms tAVAX tAVAX A0-A19 ADDRESS VALID ADDRESS VALID tAVQV tAVQV tAXAV tAXAV E1 tGLQV tAVGL G tGHQX UB, LB tGLQX DQ0-DQ15 tAXQX DATA OUT tGHQZ DATA OUT AI09937 Note: 1. E2 = High and W = High. 2. During the two consecutive Read operations, the Output Enable signal, G, can either remain Low, or be toggled. 14/25 M69AW024BE Figure 9. UB/LB Controlled Read AC Waveforms tAXAV tAXAV tAVAX A0-A19 ADDRESS VALID tAVQV E1 Low G Low tBLQV tBLQV LB tBHQZ UB tBLQX DQ0-DQ7 tBLQV tBLQX tBHQX VALID DATA OUT tBHQZ tBHQX VALID DATA OUT tBHQZ tBLQX DQ8-DQ15 tBHQX VALID DATA OUTPUT ai09938b Note: E2 = High and W = High. 15/25 M69AW024BE Table 8. Write Mode AC Characteristics M69AW024BE Symbol tAVAX, Alt. Parameter –60 Unit Min Max 1000 tWC Chip Enable Write Cycle Time 70 tAS Address Set-up Time to Chip Enable Low 0 ns tCW Chip Enable Write Pulse Width 45 ns tWP Write Enable Write Pulse Width 45 ns tBLBH(3) tBW LB, UB Pulse (Write Operation) 45 ns tBHWL(4) tBS LB, UB Byte Masking Set-up Time –5 ns tWHBL(5) tBH LB, UB Hold Time –5 ns tBHAX(6) tWR Write Recovery Time 0 ns tEHEL tCP Chip Enable High Pulse 10 ns tWHWL tWHP Write Enable High Pulse 10 1000 ns tBHBL tBHP LB, UB High Pulse 10 1000 ns tDVEH, tDVWH, tDVBH tDS Data Set-up Time 15 ns tEHDZ, tWHDZ, tBHDZ, tGHDZ tDH Data Hold Time 0 ns tGHEL(7) tOHCL Output Enable High to Chip Enable Low Set-up Time –5 ns tGHAV(8) tOES Output Enable Set-up Time 0 ns tBLBH2 tBWO LB, UB Low to LB, UB High for Page Access 30 ns tELAX(1,2) tAVEL, tAVBL, tAVWL(2) tELEH(3) tWLBH, tWLWH(3) tBLWH, tWHAX, tEHAX, ns Note: 1. The maximum value of this timing is applicable if E1 is kept Low without any address change. If needed by system operation, please contact your local ST representative for relaxation of the 1000ns limitation. 2. Minimum value must be equal to or greater than the sum of the write pulse (tELEH, tWLBH or tBLBH and the write recovery time tWHAV. 3. Write pulse is defined from the falling edge of E1, W, or LB/UB, whichever occurs last. 4. Applicable to Byte Masking only. Byte Masking set-up time is defined from the falling edge of E1 or W whichever occurs last. 5. Applicable to Byte Masking only. Byte Masking hold time is defined from the rising edge of E1 or W whichever occurs first. 6. Write recovery is defined from the rising edge of E1, W, or LB/UB, whichever occurs first. 7. If G is Low after tGHEL(min), the read cycle is initiated. In other words, G must be brought High within tGHEL (min) after E1 is brought Low. Once the read cycle is initiated, new write pulse should be input after tAVAX or tELEH minimum value. 8. If G is Low after new address input, the read cycle is initiated. In other words, G must be brought High at the same time or before new address valid. Once the read cycle is initiated, new write pulse should be input after tAVAX or tELEH minimum value. 16/25 M69AW024BE Figure 10. Write AC Waveforms tELAX A0-A19 ADDRESS VALID ADDRESS VALID tEHAX,tWHAX, tBHAX tAVEL tELEH tAVEL E1 tEHEL tAVWL tWLWH tAVWL W tBHAX tAVBL tWHWL tBLWH tAVBL LB, UB tGHEL tBHBL G tDVEH tDVWH tDVBH tEHDZ tWHDZ tBHDZ VALID DATA INPUT DQ0-DQ15 ai09939 Note: 1. E2 must be High during the Write cycle. Figure 11. W Controlled, Write AC Waveforms A0-A19 tAVAX tAVAX tAXAV ADDRESS VALID ADDRESS VALID tGHAX E1 tWHAX Low tAVWL tWLWH tAVWL tWLWH tWHAX W tWHWL LB, UB tGHAV G tDVWH tGHDZ DQ0-DQ15 tWHDZ VALID DATA INPUT tDVWH tWHDZ VALID DATA INPUT AI09940 Note: 1. E2 must be High during the Write cycle. 17/25 M69AW024BE Figure 12. Write Enable and UB/LB Controlled, Byte Write AC Waveforms 1 tAVAX tAVAX A0-A19 ADDRESS VALID ADDRESS VALID tAXAV E1 Low tAVWL tWLBH tWLBH tAVWL W tBHAX tBHAX tWHWL tWHBL LB tBHWL tBHWL tWHBL UB tDVBH tBHDZ VALID DATA INPUT DQ0-DQ7 tDVBH tBHDZ VALID DATA INPUT DQ8-DQ15 AI09941 Note: 1. E2 and G must be High during the Write cycle. Figure 13. Write Enable and UB/LB Controlled, Byte Write AC Waveforms 2 tAVAX tAVAX A0-A19 E1 ADDRESS VALID ADDRESS VALID Low tAVBL tBLWH tWHWL W tWHAX tWHAX tBHWL tWHBL LB tAVBL tBHWL tWHBL tBLWH UB tDVWH DQ0-DQ7 tWHDZ VALID DATA INPUT tDVWH DQ8-DQ15 tWHDZ VALID DATA INPUT AI09942 Note: 1. E2 and G must be High during the Write cycle. 18/25 M69AW024BE Figure 14. Write Enable and UB/LB Controlled, Byte Write AC Waveforms 3 tAVAX tAVAX A0-A19 E1 ADDRESS VALID tAXAV Low tAVBL ADDRESS VALID tWHWL tBLBH W tBHAX tWHBL tBHWL LB tAVBL tBHWL tBLBH tBHAX tWHBL UB tDVBH tBHDZ VALID DATA INPUT DQ0-DQ7 tBVWH tBHDZ VALID DATA INPUT DQ8-DQ15 AI09943 Note: 1. E2 and G must be High during the Write cycle. Figure 15. Write Enable and UB/LB Controlled, Byte Write AC Waveforms 4 tAVAX tAVAX A0-A19 E1 ADDRESS VALID ADDRESS VALID Low W tBHAX tAVBL tBLBH tBLBH tAVBL tBHAX LB tBLBH2 tAVBL tBHBL tDVBH tBHDZ tDVBH tBHDZ VALID DATA INPUT DQ0-DQ7 VALID DATA INPUT tBHAX tBLBH tBLBH2 tAVBL tBLBH tBHAX UB tBHBL tDVBH DQ8-DQ15 tBHDZ tDVBH VALID DATA INPUT tBHDZ VALID DATA INPUT AI09944 Note: 1. E2 and G must be High during the Write cycle. 19/25 M69AW024BE Table 9. Standby, Power-Down and Power-Up AC Parameters M69AW024BE Symbol Alt. Parameter –60 Min Unit Max tCLEL tCSP E2 Low Setup Time for Power Down Entry 10 ns tELCH tC2LP E2 Low Hold Time after Power Down Entry 80 ns tCHEL(1) tCHH E1 High Hold Time following E2 High after Power-Down Exit E1 High Hold Time following E2 High after Power-Up 300 µs tEHCH tCHS E1 High Setup Time following E2 High after Power-Down Exit 0 ns tEHGH tCHOX E1 High to G Invalid Time for Standby Entry 10 ns tEHWH(2) tCHWX E1 High to W Invalid Time for Standby Entry 10 ns tτ(3) tτ Input Transition Time 1 tEHCH2 tC2LH Power-Up Time 50 Note: 1. 2. 3. 4. 25 ns µs Applicable both to Power-Down and Power-Up. Some data might be written into any address location if tEHWL (min) is not satisfied. The Input Transition Time used in AC measurements is 5ns. TBD = to be defined. Figure 16. Power-up Mode AC Waveforms - 1 E1 tEHCH tEHCH2 tCHEL E2 VCC VCC min 0V AI07740b Note: tEHCH2 is defined from VCC reaching VCC(min). Figure 17. Power-up Mode AC Waveforms - 2 E1 tEHEL E2 VDD VDDmin AI09945 Note: tCHEL is defined from VCC reaching VCC(min) and applicable both for E1 and E2 signals. 20/25 M69AW024BE Figure 18. Power-Down Entry ad Exit AC Waveforms E1 tEHCH E2 tCLEL DQ0-D15 tELCH tCHEL Hi-Z Power-Down Entry Power-Down Mode Power-Down Exit AI09946 Note: The Power-Down mode timing can also be used as a Reset timing if the Power-up mode timing cannot be satisfied. Figure 19. Standby Mode Entry AC Waveforms, after Read or Write E1 E1 tEHGH High tEHWH G G High W W Active (Read) Standby Active (Write) Standby AI07741b Note: Both tEHGH and tEHWH define the earliest entry timing for Standby mode. If one of these timings is not satisfied, it takes a tAVAX(min) delay to enter Standby mode from E1 rising edge. 21/25 M69AW024BE PACKAGE MECHANICAL Figure 20. TFBGA48 6x8mm - 6x8 ball array, 0.75 mm pitch, Package Outline, Bottom View D D1 FD FE SD SE BALL "A1" E E1 ddd e e b A A2 A1 BGA-Z26 Note: Drawing is not to scale. Table 10. TFBGA48 6x8mm - 6x8 ball array, 0.75 mm pitch, Package Mechanical Data millimeters inches Symbol Typ Min A Typ Min 1.200 A1 0.0102 0.900 b Max 0.0472 0.260 A2 0.350 0.450 0.0354 0.0138 0.0177 D 6.000 5.900 6.100 0.2362 0.2323 0.2402 D1 3.750 – – 0.1476 – – ddd 22/25 Max 0.100 0.0039 E 8.000 7.900 8.100 0.3150 0.3110 0.3189 E1 5.250 – – 0.2067 – – e 0.750 – – 0.0295 – – FD 1.125 – – 0.0443 – – FE 1.375 – – 0.0541 – – SD 0.375 – – 0.0148 – – SE 0.375 – – 0.0148 – – M69AW024BE PART NUMBERING Table 11. Ordering Information Scheme Example: M69AW024BE 60 ZB 8 F Device Type M69 = 1T/1C Memory Cell Architecture Mode A = Asynchronous Operating Voltage W = 2.7 to 3.3V Array Organization 024 = 16 Mbit (1M x16) Option 1 B = 2 Chip Enable Option 2 E = E die Speed Class 60 = 60ns Package ZB = TFBGA48 6x8mm - 6x8 ball array, 0.75 mm pitch Temperature Range 8 = –30 to 85 °C Packing Option F = RoHS Compliant Package, Tape & Reel Packing The notation used for the device number is as shown in Table 11.. For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest STMicroelectronics Sales Office. 23/25 M69AW024BE REVISION HISTORY Table 12. Document Revision History Date Rev. 28-Jun-2004 0.1 First Issue 29-Jun-2004 0.2 Table 11., Ordering Information Scheme updated. 22-Mar-2005 1.0 tEHQX added in Table 7., Read and Standby Modes AC Characteristics. tGHDZ and tBHDZ added in Table 8., Write Mode AC Characteristics. Figure 19., Standby Mode Entry AC Waveforms, after Read or Write updated. RoHS Packing option added in FEATURES SUMMARY and Table 11., Ordering Information Scheme. TLEAD parameter added in Table 3., Absolute Maximum Ratings 05-Apr-2005 2.0 Figure title modified and Note 2 added below Figure 8. 24/25 Revision Details M69AW024BE Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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